FACULTY OF ENGINEERING & TECHNOLOGY

LAB REPORT

DigitaI SignaI Processing
ETM 4096

TRMESTER 2 (2011/2012)

DSP2 Design Of A Digital Filter With Matlab (plus Demo on DSP Starter Kit)


Ayu FemiIia Rizki
1091105580

uaLe of LxperlmenL 10 november 2011
uaLe of 8eporL Submlsslon 24 november 2011


C8ILC1IVL
@o develop a slmple embedded sysLem scheduler
@o undersLand how Lo use !lL compller

IN1kCDUC1ICN
!lL (!ens llle LdlLor)

ls a free Wlndows (32blL) based LexL edlLor and source code edlLor whlch
ls almed prlmarlly aL compuLer programmers worklng wlLh C/C++ buL lL ls noL llmlLed Lo LhaL
@he program ls avallable ln Lngllsh and Cerman !ens llle LdlLor ls sLlll avallable and free Lo
download and Lo use lL may be dlsLrlbuLed Lo oLhers buL only free of charge @hls sofLware
cannoL be used ln wlndows 7 operaLlng sysLem @hus ln Lhls lab sesslon we were uslng wlndows
x operaLlng sysLem
kLSUL1 AND DISCUSSICN
arL 1 uslng @lmer lnLerrupL
ln Lhls experlmenL we were uslng mode 2 Llmer lnLerrupL @hls mode ls 16blL Llmer
8elow ls Lhe calculaLlon Lo seL @2 and @2 so LhaL Lhe Llmer Llcks for 3ms
216 63336
ocn cc
1
]


1
11.0592MHz
ps
@herefore Lhe Llmer ls able Lo counL up from 0 Lo 63333 ln 63336s by below equaLlon
= ocn cc
= ps
= ps
@o calculaLe reload value for 3ms use below equaLlon
= ps - ps
= ps
@haL value ls dlvlded by 1 machlne cycle becomes 60336 8y converLlng 60336
10
lnLo
hexadeclmal value we geL LC78
16
uL LC Lo @2 and 78 @2
uL 8CA2 value Lhe same as @2 value and 8CA2 value as @ value @hls
requlremenL ls only for Llmer mode 2 only @hls ls because ln Llmer mode 2 Lhe reload
value (@2 and @) wlll be reseL Lo 0 afLer one Llme usage So 8CA2 and 8CA2 wlll
hold Lhe reload value and Lhen lL wlll recharge Lhe value lnLo @2 and @ respecLlvely

arL 2 llashlng Lu
CuesLlon 2
/**
Malnc

Slmple Llmer lS8 demonsLraLlon program
uslng uC/31 compller
**/
#lnclude reg32h
#lnclude lrq32h // lnclue Lhls flle Lo use l8C_vLC@8
macro

unslgned char blL Lu_sLaLe
unslgned char blL Lu_pln [ 0x87 // dlrecLly accesslng
Lhe pln
#deflne Lu_uu8A@ln 100
near unslgned led_duraLlon_counL // Lo place Lhls varlable
ln lnLernal 8AM
vold Lu_lnlL(vold)
vold Lu_updaLe(vold)
// luncLlon proLoLype
// n@L lS8 ls noL expllcLly called and does noL requlre a
proLoLype
vold @lmer_2_lnlL(vold)
// lnsLall Lhe lnLerrupL vecLor
l8C_vLC@8(@lmer_2_@lck@lML82)
/* */
vold maln(vold)

Lu_lnlL()
@lmer_2_lnlL() // SeL up @lmer 2
LA 1 // Clobally enable lnLerrupLs
whlle(1) // An empLy Super oop

/* */
vold @lmer_2_lnlL(vold)

@2Cn 0x04 // oad @lmer 2 conLrol reglsLer
@2 0xLC // oad @lmer 2 hlgh byLe
8CA2 0xLC // oad @lmer 2 reload capL reg hlgh
byLe
@2 0x78 // oad @lmer 2 low byLe
8CA2 0x78 // oad @lmer 2 reload capL reg low
byLe

// @lmer 2 lnLerrupL ls enabled and lS8 wlll be called
// whenever Lhe Llmer overflows see below
L@2 1
// SLarL @lmer 2 runnlng
@82 1


/* */
// @hls lS8 ls called every Llmer Llck (3ms)
vold @lmer_2_@lck(vold) lnLerrupL

// musL manually clear Llmer 2 overflow flag
@l2 0
// call Lask
Lu_updaLe()

/* */
vold Lu_lnlL(vold)

Lu_sLaLe 0
Lu_pln 0
led_duraLlon_counL 0

/* */
vold Lu_updaLe(vold)

led_duraLlon_counL++
lf (led_duraLlon_counL Lu_uu8A@ln)
led_duraLlon_counL 0
lf (Lu_sLaLe1)
Lu_sLaLe 0
Lu_pln 0

else
Lu_sLaLe 1
Lu_pln 1



/* */

CuesLlon 3
@he flashlng frequency of Lhe Lu can be calculaLed as below
=

cn

=

s

= E

arL 3 SLepper MoLor ConLrol
CuesLlon 4
#lnclude sLdloh
#lnclude reg31h

// S@L MoLor Lype M33S048L8 wlred as unl
A8 S@L M@8
// ( brand nM8 Mlnlbea LlecLronlcs Ld )
/****************
u@0 20
u@1 21
u@2 22
u@3 23
****************/
consL char paLLern 1 3 4 6 2 10 8 9
#deflne ASL_MASk 0x7

vold run_moLor_phase(char dlrecLlon)

sLaLlc char phase
lf (dlrecLlon)
phase (++phase) ASL_MASk
else
phase (phase) ASL_MASk
2 paLLernphase


vold run_moLor_sLep(char dlrecLlon char speed shorL
sLeps)

shorL l
for (l0 lsLeps l++)
run_moLor_phase(dlrecLlon)
_walL_ms(speed)



/*******************
* MAln SLarL here!
*******************/
vold maln(vold)
for( )
run_moLor_sLep(0 13 2000)




arL 4 Slmple MulLl @asklng
CuesLlon 3
#lnclude sLdloh
#lnclude reg31h
#lnclude reg32h
#lnclude lrq32h
// S@L MoLor Lype M33S048L8 wlred as unl
A8 S@L M@8
// ( brand nM8 Mlnlbea LlecLronlcs Ld )
unslgned char blL Lu_sLaLe
unslgned char blL Lu_pln [ 0x87 // dlrecLly accesslng
Lhe pln
#deflne Lu_uu8A@ln 100
near unslgned led_duraLlon_counL // Lo place Lhls varlable
ln lnLernal 8AM
vold Lu_lnlL(vold)
vold Lu_updaLe(vold)
// luncLlon proLoLype
// n@L lS8 ls noL expllcLly called and does noL requlre a
proLoLype
vold @lmer_2_lnlL(vold)
// lnsLall Lhe lnLerrupL vecLor
l8C_vLC@8(@lmer_2_@lck@lML82)
/* */
consL char paLLern 1 3 4 6 2 10 8 9
#deflne ASL_MASk 0x7
vold run_moLor_phase(char dlrecLlon)

sLaLlc char phase
lf (dlrecLlon)
phase (++phase) ASL_MASk
else
phase (phase) ASL_MASk
2 paLLernphase


vold run_moLor_sLep(char dlrecLlon char speed shorL
sLeps)

shorL l
for (l0 lsLeps l++)
run_moLor_phase(dlrecLlon)
_walL_ms(speed)



/*******************
* MAln SLarL here!
*******************/
vold maln(vold)
for( )
Lu_lnlL()
@lmer_2_lnlL() // SeL up @lmer 2
LA 1 // Clobally enable lnLerrupLs
run_moLor_sLep(0 10 2000)



vold @lmer_2_lnlL(vold)

@2Cn 0x04 // oad @lmer 2 conLrol reglsLer
@2 0xec // oad @lmer 2 hlgh byLe
8CA2 0xec // oad @lmer 2 reload capL reg hlgh
byLe
@2 0x78 // oad @lmer 2 low byLe
8CA2 0x78 // oad @lmer 2 reload capL reg low
byLe

// @lmer 2 lnLerrupL ls enabled and lS8 wlll be called
// whenever Lhe Llmer overflows see below
L@2 1
// SLarL @lmer 2 runnlng
@82 1


/* */
// @hls lS8 ls called every Llmer Llck (3ms)
vold @lmer_2_@lck(vold) lnLerrupL

// musL manually clear Llmer 2 overflow flag
@l2 0
// call Lask
Lu_updaLe()


/* */
vold Lu_lnlL(vold)

Lu_sLaLe 0
Lu_pln 0
led_duraLlon_counL 0


/* */
vold Lu_updaLe(vold)

led_duraLlon_counL++
lf (led_duraLlon_counL Lu_uu8A@ln)
led_duraLlon_counL 0
lf (Lu_sLaLe1)
Lu_sLaLe 0
Lu_pln 0

else
Lu_sLaLe 1
Lu_pln 1

arL 3 WrlLlng Lo 7SegmenL ulsplay
CuesLlon 6
/**
Malnc

Slmple Llmer lS8 demonsLraLlon program
uslng uC/31 compller
**/
#lnclude sLdloh
#lnclude reg31h
#lnclude reg32h
#lnclude lrq32h // lnclue Lhls flle Lo use l8C_vLC@8
macro
unslgned char blL Lu_sLaLe
unslgned char blL Lu_pln [ 0x87 // dlrecLly accesslng
Lhe pln
#deflne Lu_uu8A@ln 100
near unslgned led_duraLlon_counL // Lo place Lhls varlable
ln lnLernal 8AM
vold Lu_lnlL(vold)
vold Lu_updaLe(vold)
// luncLlon proLoLype
// n@L lS8 ls noL expllcLly called and does noL requlre a
proLoLype
vold @lmer_2_lnlL(vold)
// lnsLall Lhe lnLerrupL vecLor
l8C_vLC@8(@lmer_2_@lck@lML82)
/* */
consL char Lu8 0x01 0x02 0x04 0x08 0x10 0x20
0x40 0x80
consL char paLLern 1 3 4 6 2 10 8 9
#deflne ASL_MASk 0x7
vold run_moLor_phase(char dlrecLlon)

sLaLlc char phase
lf (dlrecLlon)
phase (++phase) ASL_MASk
else
phase (phase) ASL_MASk
2 paLLernphase

vold run_moLor_sLep(char dlrecLlon char speed shorL
sLeps)

shorL l
for (l0 lsLeps l++)
run_moLor_phase(dlrecLlon)
_walL_ms(speed)


vold maln(vold)

for( )
char cnL
2 0xll
for ()

for (cnL0cnL8 cnL++)

2 LucnL
_walL_ms(300)


@lmer_2_lnlL() // SeL up @lmer 2
LA 1 // Clobally enable lnLerrupLs
run_moLor_sLep(0 13 300)
//whlle(1) // An empLy Super oop



/* */
vold @lmer_2_lnlL(vold)

@2Cn 0x04 // oad @lmer 2 conLrol reglsLer
@2 0xlC // oad @lmer 2 hlgh byLe
8CA2 0xlC // oad @lmer 2 reload capL reg hlgh
byLe
@2 0x18 // oad @lmer 2 low byLe
8CA2 0x18 // oad @lmer 2 reload capL reg low
byLe

// @lmer 2 lnLerrupL ls enabled and lS8 wlll be called
// whenever Lhe Llmer overflows see below
L@2 1
// SLarL @lmer 2 runnlng
@82 1

/* */
// @hls lS8 ls called every Llmer Llck (3ms)
vold @lmer_2_@lck(vold) lnLerrupL

// musL manually clear Llmer 2 overflow flag
@l2 0
// call Lask
Lu_updaLe()

/* */
vold Lu_lnlL(vold)

Lu_sLaLe 0
Lu_pln 0
led_duraLlon_counL 0

/* */
vold Lu_updaLe(vold)

led_duraLlon_counL++
lf (led_duraLlon_counL Lu_uu8A@ln)
led_duraLlon_counL 0
lf (Lu_sLaLe1)
Lu_sLaLe 0
Lu_pln 0

else
Lu_sLaLe 1
Lu_pln 1




/* */

CCNCLUSICN
AfLer dolng Lhls lab experlmenL l can conclude LhaL we have Lo be aware of Lhe compller
sofLware compaLlblllLy such as Lhe requlremenL of Lhe operaLlng sysLem And Lhen when uslng
Llmer lnLerrupL Lhe mode of Lhe Llmer used musL be consldered for Lhe reload Llmlng
calculaLlon And for seven segmenL seLLlng we should know whaL Lype of Lhe 7segmenL
wheLher lL ls common anode or common caLhode