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Block diagram
W1 X0 1 2 W1 X0 X1 X (14)W Y (4) X (5) Y (13) Z Y0 6 5 4 X Y Y0 VEE CONTROL VEE 7 10 Y1 W0 W Z Z1 Z0 Y1 11 Z0 13 Z 16 VDD 15 W0
VSS VEE W1 X0 X1 Y0
X1
14 W
W0 (15)
12 Z1
VSS
CONTROL
Truth table
CONTROL 0 1 ON W0 X0 Y0 Z0 W1 X1 Y1 Z1
Standard ICs
= 0V, Ta = 25C)
Limits 0.3 ~ + 18 0.3 ~ + 18 1000 (DIP), 500 (SOP), 400 (SSOP) 40 ~ + 85 55 ~ + 150 0.3 ~ VDD + 0.3 Unit V V mW C C V
EE
= VSS = 0V)
Unit Conditions Measurement circuit
Max.
VDD (V) 5
10 15 5
Fig.1
V A A
10 15 15 15 5 10 15 5
Fig.1
Fig.1 Fig.1
VIN = VDD / 2
Fig.2
10 15 15 15 5 10 15
Fig.2
Fig.3
VI = VDD or GND
Standard ICs
Switching characteristics (unless otherwise noted, Ta = 25C, VEE = VSS = 0V, RL = 10 k, CL = 50pF)
Parameter Symbol Min. Propagation delay time Switch INOUT tPLH tPHL Propagation delay time CONTOUT tPZH tPHZ Propagation delay time CONTOUT Max. propagation frequency Feedthrough attenuation Sine wave distortion Input capacitance (control) Input capacitance (switch) tPZL tPLZ fMax. FT D CC CS Typ. 35 15 12 360 160 120 360 160 120 15 0.7 0.02 5 10 Max. MHz MHz % pF pF ns ns ns Unit Conditions Measurement circuit
VDD (V) 5 10 15 5 10 15 5 10 15
Fig.4
Fig.5, 6
Fig.5, 6
1 VIN = 5VP-P sine wave, frequency that enables 20 log10 VOUT / VIN = 3dB 2 VIN = 5VP-P sine wave, frequency that enables 20 log10 VOUT / VIN = 50dB at channel off 3 VIN = 5VP-P sine wave
Measurement circuits
VDD VDD CONT IIN VIN VDD
COMMON CHANNEL OUT / IN IN / OUT
VDD or GND
CONT
RON = RL
VIN VOUT
VIN
VEE V
RL = 10k
GND
GND
Fig. 2 ON resistance
Standard ICs
VDD
VDD or GND
CONT
VDD or GND
GND or VDD
VEE
GND
VDD
VDD or GND
CONT
Output RL CL
50%
VEE P.G.
GND
tPLH
tPHL
VDD
50%
OUT
Output
50%
Standard ICs
VDD VDD
CONT
RL
CL Input 50%
P.G.
GND
OUT Output
50% 10%
VEE
GND
tPZL
tPLZ
VDD
VDD or GND
CONT
VEE
~
VEE
RL CL
D GND
Standard ICs
7.62
1 1.5 0.1
0.11
0.3 0.1
2.54
0.5 0.1
1.27
0.4 0.1
0.3Min. 0.15
0 ~ 15
DIP16
BU4551BFV
SOP16
6.4 0.3
1.15 0.1
0.1
0.65
0.22 0.1
0.3Min. 0.1
SSOP-B16
0.15 0.1
0.15 0.1
1 0.51Min.