library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.

all; ENTITY alu32bit IS port(a, b : in std_logic_vector(31 downto 0); -- a and b are busses operation : in std_logic_vector(4 downto 0); z,c : out std_logic; f : out std_logic_vector(31 downto 0)); END alu32bit; architecture alu_instance of alu32bit is begin process(operation) Variable car : std_logic := '0'; Variable temp : std_logic_vector(32 downto 0); begin temp := "000000000000000000000000000000000"; case operation is when "00000" => temp := ("0" & a) + b; --add car := temp(32); when "00001" => temp := ("0" & a) + b + car; --adc car := temp(32); when "00010" => temp := ("0" & a) - b; --sub car := temp(32); when "00011" => temp := ("0" & a) + 1; --inc car := temp(32); when "00100" => temp(31 downto 0) := a and b; --and car := '0'; when "00101" => temp(31 downto 0) := a or b; --or car := '0'; when "00110" => temp(31 downto 0) := a xor b; --xor car := '0'; when "00111" => temp(31 downto 0) := not a; --not car := '0'; when "01000" => temp(31) := '0'; --shr temp(30 downto 0) := a(31 downto 1); car := a(0); when "01001" => temp(0) := '0'; --shl temp(31 downto 1) := a(30 downto 0); car := a(31); when "01010" => temp(31) := a(0); --ror temp(30 downto 0) := a(31 downto 1); car := a(0); when "01011" => temp(31) := car; -- rorc temp(30 downto 0) := a(31 downto 1); car := a(0);

when "01100" => temp(0) := a(31); --rol temp(31 downto 1) := a(30 downto 0); car := a(31); when "01101" => temp(0) := car; -- rolc temp(31 downto 1) := a(30 downto 0); car := a(31); when "01110" => --clr temp := "000000000000000000000000000000000"; when "01111" => --clc car := '0'; temp(31 downto 0) := a; when "10000" => --stc car := '1'; temp(31 downto 0) := a; when others => temp(31 downto 0) := a; end case; if (temp(31 downto 0) = "00000000000000000000000000000000" and operation /= "10001") then -- clz z <= '1'; else z <= '0'; end if; c <= car; f <= temp(31 downto 0); end process; end alu_instance;