Files

cd 32_32_16_16/model/scripts/
qsub -P bnormal -l "cputype=amd64|emt64,mem_free=8G" -o

V -cwd -b y perl td_scripts.pl 0 0 TC_C_8_8_32_32_16_16
0 400 0 -1
cd cd 32_32_16_8/model/scripts/
0 400 0 -1
0 400 0 -1
0 400 0 -1
0 400 0 -1
0 400 0 -1
0 400 0 -1
rm -rf *.log
0 400 0 -1
0 400 0 -1
cd -
td_log.log -e err.log TC_MULTI_BLKS_SNGL_CFG 1
cd 32_32_16_16/inc/model/scripts/
qsub -P bnormal -l "cputype=amd64|emt64,mem_free=8G" -o td_log.log -e err.log V -cwd -b y perl td_scripts.pl 0 0 32_32_16_16 TC_MULTI_BLKS_SNGL_CFG 1 1 195 0
0
cd cd 32_32_16_8/inc/model/scripts/
0
0
qsub -P bnormal -l "cputype=amd64|emt64,mem_free=8G" -o td_log.log -e err.log
V -cwd -b y perl td_scripts.pl 0 0 64_32_16_16 TC_MULTI_BLKS_SNGL_CFG 1 1 195
0
0
0
0
0
0
cd cd 32_32_16_16/dec/model/scripts/
1
1
1

1
1
1
1
1
1
cd -
perl td_scripts.pl 0 0 TC_C_8_8_64_64_16_8 TC_MULTI_BLKS_SNGL_CFG 0 1 1 0 -1



qdel
qdel
qdel
qdel
qdel
qdel
qdel
qdel
qdel
3481607
3481609
3481610
3481611
3481612
3481613
3481614
3481615
3481616
cd
_8
cd
_16
cd
8
cd
_8
cd
_16
cd
8
cd
_8
cd
_16
cd
8
cp
cp
cp
cp
cp
cp
cp
cp
cp
./64_64_16_8/model/scripts/
TC_MULTI_BLKS_SNGL_CFG 0 1 100
-rf
-rf
-rf
-rf
-rf
-rf
-rf
-rf
-rf
perl td_scripts.pl 0 0 TC_C_8_8_64_64_16

0 -1
0 -1
perl td_scripts.pl 0 0 TC_C_8_8_64_64_8_
0 -1
0 -1
0 -1
0 -1
0 -1
0 -1
0 -1
$PROJECT_HOME/turbo_decoder/model
./64_64_16_8/
./64_64_16_16/
./64_64_8_8/
./64_32_16_8/
./64_32_16_16/
./64_32_8_8/
./32_32_16_8/
./32_32_16_16/
./32_32_8_8/
cp -rf $PROJECT_HOME/turbo_decoder/sim ./64_64_16_8/

cp -rf $PROJECT_HOME/turbo_decoder/src ./64_64_16_8/
turbo_decoder
|
|
|- model
| |-ccode
| |-scripts
| |-vectors
|
|- sim
|- src
| |-radxi2 (LTE only)
| |-radxi4 ( for both LTE and WiMAX)
|- work
| |- Data_Width
| | |- DW_6
| | | |- TC_1
| | | | |- scripts
| | | | |- system_test
| | | | |- sim
| | | | | |- config/td-setup.vh
| | | | |- vectors
| | | |- TC_2
| | | | |- scripts
| | | | |- system_test
| | | | |- sim
| | | | | |- config/td-setup.vh
| | | | |- vectors
| | |- DW_7
| | |- DW_8
| | |- Report
| |
| |- LLR_Growth
| |- Max Iter
| |- CRC
| |- Memory Read Latency
| |- Write O/P
| |- O/P read type (Cut through or Store Forward)
1. Path for RTL source files [D]

2. Radix-2 LTE/Radix-4 LTE or Radix-4 WiMAX (802.16d/802.16e) [D]
3. Single or Multiple blocks (Multiple blocks for all 4 combinatiomnms of SW an
d GB)[D]
4. Single Or Regression[D]
5. Controlling dumps (if single all dumps enabled else only byte packeddata dum
p must be enabled)[D]
6. Automactic parsing of reports
7. Comparing byte packed data as well as iteration count of C and RTL in decidi
ng pass/fail
8. Processing clocks [D]
9. Tasks file to include setup file to decide on the stanndard so that data is
fed accordingly [D]
10. Regression for all block sizes [D]
11. Multiple blocks regression : [D]
for(each combination of SW/GB )
for(each block size (0 index to Max index) increasing/ Decreasing/ rando
m
$testcase = "perl td_scripts.pl 0 $tc[$i] DW 0 1 1 6144 0"
12.
To be clarified with KP
=======================
1. Auto configuration will decide only # of decoders to be used ,
The SW and GB will not be auto configured
2. Log correction factor postponed
3. CRC is compile time configurable to CRC24A/CRC24B

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cd 32_32_16_16/model/scripts/

qsub -P bnormal -l "cputype=amd64|emt64,mem_free=8G" -o

td_log.log -e err.log TC_MULTI_BLKS_SNGL_CFG 1

td_log.log -e err.log TC_MULTI_BLKS_SNGL_CFG 1

td_log.log -e err.log TC_MULTI_BLKS_SNGL_CFG 1

td_log.log -e err.log TC_MULTI_BLKS_SNGL_CFG 1

td_log.log -e err.log TC_MULTI_BLKS_SNGL_CFG 1

td_log.log -e err.log TC_MULTI_BLKS_SNGL_CFG 1

td_log.log -e err.log TC_MULTI_BLKS_SNGL_CFG 1

td_log.log -e err.log TC_MULTI_BLKS_SNGL_CFG 1

td_log.log -e err.log TC_MULTI_BLKS_SNGL_CFG 1

V -cwd -b y perl td_scripts.pl 0 0 64_32_16_16 TC_MULTI_BLKS_SNGL_CFG 1 1 195

perl td_scripts.pl 0 0 TC_C_8_8_64_64_16_8 TC_MULTI_BLKS_SNGL_CFG 0 1 1 0 -1

perl td_scripts.pl 0 0 TC_C_8_8_64_32_8_8 TC_MULTI_BLKS_SNGL_CFG 0 1 100 0 -1

perl td_scripts.pl 0 0 TC_C_8_8_64_32_16_16 TC_MULTI_BLKS_SNGL_CFG 0 1 100 0 -1

perl td_scripts.pl 0 0 TC_C_8_8_64_64_16

cp -rf $PROJECT_HOME/turbo_decoder/sim ./64_64_16_8/

1. Path for RTL source files [D]

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