7ILLIAM 3TALLINGS

#OMPUTER /RGANIZATION
AND !RCHITECTURE

#HAPTER 
)NTRODUCTION

!RCHITECTURE  /RGANIZATION 

!RCHITECTURE IS THOSE ATTRIBUTES VISIBLE TO THE

PROGRAMMER

)NSTRUCTION SET NUMBER OF BITS USED FOR DATA

REPRESENTATION )/ MECHANISMS ADDRESSING
TECHNIQUES

EG )S THERE A MULTIPLY INSTRUCTION

/RGANIZATION IS HOW FEATURES ARE IMPLEMENTED

#ONTROL SIGNALS INTERFACES MEMORY TECHNOLOGY

EG )S THERE A HARDWARE MULTIPLY UNIT OR IS IT DONE BY
REPEATED ADDITION

!RCHITECTURE  /RGANIZATION 

!LL )NTEL X FAMILY SHARE THE SAME BASIC

ARCHITECTURE

4HE )"- 3YSTEM FAMILY SHARE THE SAME

BASIC ARCHITECTURE

4HIS GIVES CODE COMPATIBILITY

/RGANIZATION DIFFERS BETWEEN DIFFERENT VERSIONS

!T LEAST BACKWARDS

3TRUCTURE  &UNCTION

3TRUCTURE IS THE WAY IN WHICH COMPONENTS RELATE

TO EACH OTHER

&UNCTION IS THE OPERATION OF INDIVIDUAL

COMPONENTS AS PART OF THE STRUCTURE

&UNCTION

!LL COMPUTER FUNCTIONS ARE

$ATA PROCESSING
$ATA STORAGE
$ATA MOVEMENT
#ONTROL

&UNCTIONAL VIEW

&UNCTIONAL VIEW OF A COMPUTER

Data
Storage
Facility
Data
Movement
Apparatus

Control
Mechanism

Data
Processing
Facility

/PERATIONS 

$ATA MOVEMENT

EG KEYBOARD TO SCREEN

Data
Movement
Apparatus

Data
Storage
Facility
Control
Mechanism

Data
Processing
Facility

/PERATIONS 

3TORAGE

EG )NTERNET DOWNLOAD TO DISK

Data
Movement
Apparatus

Data
Storage
Facility

Control
Mechanism

Data
Processing
Facility

/PERATION 

0ROCESSING FROMTO STORAGE

EG UPDATING BANK STATEMENT

Data
Movement
Apparatus

Data
Storage
Facility

Control
Mechanism

Data
Processing
Facility

/PERATION 

0ROCESSING FROM STORAGE TO )/

EG PRINTING A BANK STATEMENT

Data
Movement
Apparatus

Data
Storage
Facility

Control
Mechanism

Data
Processing
Facility

3TRUCTURE 4OP ,EVEL

Computer

Peripherals

Central
Processing
Unit
Computer

Main
Memory

Systems
Interconnection

Input
Output
Communication
lines

3TRUCTURE 4HE #05

CPU
Computer

Arithmetic
and
Login Unit

Registers

I/O
System
Bus
Memory

CPU

Internal CPU
Interconnection

Control
Unit

3TRUCTURE 4HE #ONTROL 5NIT

Control Unit
CPU
ALU

Sequencing
Login

Control
Internal
Unit
Bus
Registers

Control Unit
Registers and
Decoders

Control
Memory

/UTLINE OF THE "OOK 

#OMPUTER %VOLUTION AND 0ERFORMANCE

#OMPUTER )NTERCONNECTION 3TRUCTURES
)NTERNAL -EMORY
%XTERNAL -EMORY
)NPUT/UTPUT
/PERATING 3YSTEMS 3UPPORT
#OMPUTER !RITHMETIC
)NSTRUCTION 3ETS

/UTLINE OF THE "OOK 

#05 3TRUCTURE AND &UNCTION

2EDUCED )NSTRUCTION 3ET #OMPUTERS
3UPERSCALAR 0ROCESSORS
#ONTROL 5NIT /PERATION
-ICROPROGRAMMED #ONTROL
-ULTIPROCESSORS AND 6ECTOR 0ROCESSING
$IGITAL ,OGIC !PPENDIX

)NTERNET 2ESOURCES
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)NTERNET 2ESOURCES
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777 #OMPUTER !RCHITECTURE (OME 0AGE

#05 )NFO #ENTER
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!RCHITECTURE

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!RCHITECTURE

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