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MICROPROCESSORS & MICROCONTROLLERS

CONTENTS
1) Introduction 2) Microprocessors and Microcontrollers 3) CISC & RISC CPU Architectures 4) Harvard & Von-Neumann CPU architecture 5) Computer software 6) The 8051 Architecture: Introduction 7) Architecture of 8051 8) Pin diagram of 8051 9) Memory organization 10) External Memory Interfacing 11) Stacks.

(6 Hours)

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1. INTRODUCTION:
The past 3 decades have seen the introduction of a technology that has radically changed the way in which we analyze and control the world around us. The microprocessor or computer on a chip first became a commercial reality in 1971 with the introduction of the 4 bit 4004 by Intel Corporation. Other companies also followed the lead of Intel so that by the late 1970s we could choose from half a dozen microprocessor types. The 70s decade saw the growth of a number of personal computer users from a handful of hobbyists and hackers to millions of business, industrial, government, and defense, educational and private users now enjoying the advantages of inexpensive computing. A by product of microprocessor development was microcomputer. The same fabrication techniques and programming concepts that make possible the general purpose microprocessor also yielded the microcomputer.

2. MICROPROCESSORS & MICROCONTROLLERS: 2.1 Microprocessors:

A microprocessor is a general purpose central processing unit (CPU). Although known as a Computer on Chip the Microprocessor in no senses a complete digital computer. Block diagram of a Microprocessor CPU which contains ALU; Program counter (PC), a stack pointer (SP) ,some working registers , a clock timing circuit and interrupt circuit s is shown in the following figure

Fig 1.1 Microprocessor CPU Block Diagram The hardware design of a microprocessor is arranged such that a very small or very large system can be configured around the CPU as the application demands as shown in Fig1.2. The prime use of the Microprocessor is to read data, perform extensive calculations on that data, and store those calculations in a mass storage device or display the results for human use.

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The programs used by microprocessor are stored in the mass storage device and loaded into RAM as user directs. A few microprocessor programs are stored in ROM. The ROM based programs are primarily small fixed programs that operate peripherals and other fixed devices that are connected to the system. The first microprocessor was the 4004 by Intel, in 1971 by Intel, containing an arithmetic unit. The first portable embedded system built using 4004 was a calculator. Intel came out with first home computer in 1974 based on 8080, which was an 8 processor. The most popular IBM PC was introduced in 1979 had Intel 8088. Since then Intel introduced 80286/386/486 and lately Pentium class of processors. To make a microcomputer one must add memory usually RAM and ROM, memory decoders, an oscillator and a number of Input/output devices such as serial and parallel ports. Figure 1.2 shows the block diagram of such a microcomputer.

Fig 1.2 Block diagram of a microcomputer

2.2 Microcontroller:
A microcontroller is a programmable digital processor with necessary peripherals. The design has all the features found in microprocessor CPU: ALU,PC, SP and registers. It also has other features needed to make a complete computer: ROM, RAM, Parallel I/O, serial I/O, Counters and clock circuits. A microcontroller can be compared to a Swiss knife with multiple functions incorporated in the same Integrated Circuits. Block diagram of a typical Microcontroller which is a true computer on a chip is shown in fig 1.3. The prime use of microcontroller is to control the operation of a machine using a fixed program that is stored in ROM and that does not change over the lifetime of the system.

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Fig 1.3(a) Block diagram of a Microcomputer

Fig 1.3 (b) Internal Structure of a typical Microcontroller

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2.3 Microprocessors versus Microcontrollers: MICROPROCESSORS MICROCONTROLLERS

Contains ALU, general purpose registers, stack Contains the circuitry of microprocessor and in pointer, program counter, clock timing circuit and addition it has built in ROM, RAM, I/O devices, interrupt circuit. timers and counters. Have many instructions to move data between Have one or two instructions. memory and CPU. Have one or two bit handling instructions. Access times for memory and I/O devices are more. Microprocessor based systems require more hardware. Have many instructions for handling the memory. Less access times for built in memory and I/O devices. Microcontroller based system require less hardware, reducing the PCB size and increasing the reliability. Less flexible from the design point of view. Has separate memory map for data and code. More number of pins are multifunctional.

They are more flexible in design point of view. Has single memory map for data and code. Less number of pins is multifunctional.

2.4 Development/Classification of microcontrollers: The evolution of microcontrollers can be rightly termed as silent as the impact or application of a microcontroller is not well known to a common user, although microcontroller technology has undergone significant change since early 1970's. Development of some popular microcontrollers is given as follows. 4 bit (2300 PMOS trans, 108 Intel 4004 1971 kHz) Intel 8048 8 bit 1976 Intel 8031 8 bit (ROM-less) . Intel 8051 8 bit (Mask ROM) 1980 Microchip PIC16C64 8 bit 1985 Motorola 68HC11 8 bit (on chip ADC) . Intel 80C196 16 bit 1982 Atmel AT89C51 8 bit (Flash memory) . Microchip PIC 16F877 8 bit (Flash memory + ADC) . We use more number of microcontrollers compared to microprocessors. Microprocessors are primarily used for computational purpose, whereas microcontrollers find wide application in devices needing real time processing and control. Application of microcontrollers is numerous. Starting from domestic applications such as in washing machines, TVs, air conditioners, microcontrollers are used in automobiles, process control industries,
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cell phones, electrical drives, robotics and in space applications. 2.5 Criterion for selecting a microcontroller: It must meet the task at hand efficiently and cost effectively: a) Speed b) Packaging c) Power consumption d) RAM and ROM e) Number of I/O pins f) Timer g) Upgradation h) Cost per Unit Availability of assembler, debugger, C language compiler and emulator, technical support both at in and out house. Wide availability and reliable sources of the microcontrollers.

3. CISC & RISC CPU Architectures:

Two most common types of computers are: 3.1 Complex Instruction Set Computer 3.2 Reduced Instruction Set Computer

3.1 Complex Instruction Set Computer (CISC):

Memory in those days was expensive. Bigger programs required more storage which included more money. There was a need to reduce the number of instructions per program. This was achieved by having multiple operations within single instruction. Multiple operations leads to many different kinds of instructions .Access to memory in turn makes the instruction length variable and fetch-decode execute time unpredictable making it more complex. Thus hardware was made to understand the complexity of instruction set. The computer having such instruction set was named as Complex Instruction Set Computer (CISC). Intel 8051 is an example for CISC architecture. The features of CISC are as follows: Large number of instructions. Execution time for each instruction may be different Execution time for an instruction may take several clock cycles. Efficient use of memory space. Single instruction will perform a complex operation. Robustness of instruction speed given priority over speed of instruction. Works faster for complex instruction, but may be slow for single tasks. Emphasis on complex hardware to store a large instruction set Number of instructions per program is minimized Most instructions refer to memory Instructions are executed by micro program. Variable format of instruction. Many instructions and many addressing modes. Single register set Not pipelined or less pipelined. Conditional jump is usually based on status register bits.

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3.2 Reduced Instruction Set Computer (RISC): In applications which require more of input, output related operations having few simple instructions that are of the same length allows memory access only with explicit load and store instructions. Hence each instruction performs less work but instruction execution time among different instructions is consistent. This would lead to instruction execution by hardware including multiple numbers of registers inside CPU. The computer using such instructions is called Reduced Instruction Set Computer (RISC). PIC microcontroller manufactured by Microchip Company is an example for RISC architecture. The features of RISC are as follows: Most instructions are executed in one clock cycle. Instructions are design optimized using pipelining technique. Reduced complexity in hardware. Less hardware space for transitions in silicon for each instruction. Large register set. Variables and intermediate results stored in registers. Complex operations are performed as a series of simple RISC instructions. Instructions are fixed length and format. There are few instructions. Emphasis on software for each task. Program consists large code size Instructions are executed by hardware. Few addressing modes, mostly register to register addressing modes. Complex addressing modes are synthesized in software Multiple register set Complexity in compiler design. Conditional jump can be based on a bit anywhere in the memory.

4. HARVARD & PRINCETON (VON-NEUMANN) CPU ARCHITECTURE:

4.1 Princeton (Von-Neumann) CPU Architecture: It is named after the mathematician and early computer scientist John Von Neumann. The computer has single storage system (memory) for storing data as well as program to be executed. Processor needs two clock cycles to complete an instruction. Pipelining the instructions is not possible with this architecture. In the first clock cycle the processor gets the instruction from memory and decodes it. In the next clock cycle the required data is taken from memory. For each instruction this cycle repeats and hence needs two cycles to complete an instruction.

Fig 1.4: Princeton (Von-Neumann) Architecture. 4.2 Harvard CPU Architecture: The name is originated from "Harvard Mark I" a relay based old computer and is as shown in fig 1.5. The computer has two separate memories for storing data and program. Processor can complete an instruction in one cycle if appropriate pipelining strategies are implemented. In the first stage of pipeline the instruction to be executed can be taken from program memory. In the second stage of pipeline data is taken from the data memory using the decoded instruction or address.
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Most of the modern computing architectures are based on Harvard architecture. But the number of stages in the pipeline varies from system to system.

Fig 1.5: Harvard Architecture.

5. COMPUTER SOFTWARE:
A set of instructions written in a specific sequence for computer to solve a specific task is called a program, and software is collection of programs. The program stored in the computer memory in the form of 0s and 1s and it is called as machine level instructions. Since it would be difficult to remember machine codes in the form of binary numbers an intermediate level of language for programming, between higher and machine level was developed and is known as assembly level language. Assembly language programs are written using assembly instructions known as mnemonics. For example in CLR A, instruction CLR means clear and A means accumulator. The program mnemonics are converted to machine codes in the form of binary by software called Assembler. The Assembly language programming requires a detailed knowledge of the architecture with which the program is executed. In order to overcome the drawback of assembly language programming higher level language like C, C++ is introduced where an interpreter or a compiler takes care of translating a higher level source code into machine codes.

6. THE 8051 ARCHITECTURE: INTRODUCTION:

The salient features of the 8051 architecture are as follows: Eight bit CPU with registers A (Accumulator) and B 16 bit Program counter (PC) and a data pointer (DPTR) 8 Bit Program Status Word (PSW) 8 Bit Stack Pointer 4K Code Memory (Internal ROM or EPROM) Internal Memory of 128 Bytes (RAM) 4 register each with 8 registers R0 R7. Each of 8 byte size. 16 bytes which may be addressed at the bit level. 80 bytes of general purpose data memory. 32 I/O Pins arranged as 4 , 8 Bit ports Two 16 Bit Timer/Counter :T0, T1 Full Duplex serial data receiver/transmitter Control Registers : TCON,TMOD,SCON,PCON,IP and IE Two External and three Internal Interrupt sources Oscillator and clock circuits

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7. ARCHITECTURE OF 8051: The block diagram of generic 8051 is as shown in fig 1.6, is housed in a 40 pin DIP (Dual Inline Package), with all of the features unique to a microcontroller: Internal RAM & ROM I/O ports with programmable pins. Timers & Counters Serial Data Communication It is called as MCS51 by the Intel Corporation. It is generally referred as the system on chip.

Fig 1.6: 8051 Block Diagram 7.1 Accumulator (Location-0E0 h): 8 bit register. Data Transfer between 8051 and external memory.
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Can be used as general purpose register. Results of arithmetic and logic are stored in accumulator. 7.2 B Register (Location-0F0 h): 8 bit register Used for direct multiplication and division along with accumulator Accumulator and B are referred as Math registers. Can be used as general purpose register. 7.3 Program Counter: 16 bit register No internal address Holds address of next instruction. Cannot be accessed by the programmer. Incremented automatically and altered by some instructions.

7.4 Data Pointer (Location- 83h& 82h): 16 bit register; used as two 8 bit registers DPH (83 h) and DPL (82 h). Holds address of external data memory or program memory. Only register used to access 16 bit external memory. 7.5 Program Status Word(PSW) (Location- 0D0h): 8 bit register This indicates the status of the accumulator, because of arithmetic and logical operations. Have 5 flags, 4 for mathematical operations and one general purpose flag. The selection of register banks is done by setting and clearing bits RS1 and RS0 in the PSW. The details of the PSW are mentioned in fig 1.7.

Fig 1.7: Program Status Word Details

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7.6 Stack Pointer (Location: 081h): Temporary storage of information by CPU. 8 bit wide Default value stored is 07h. Instructions used to store and recover data from the stack are PUSH and POP respectively. 7.7 XTAL1 and XTAL2 (pin 19 and 18):

Fig 1.8: Crystal connection The heart of 8051 is the circuitry that generates the clock pulses by which all internal operations are synchronized. Pins XTAL1 and XTAL2 are provided for connecting resonator to form an oscillator. The crystal frequency is the basic internal frequency of the microcontroller. 8051 is designed to operate between 1MHz to 16MHz and generally operates with a crystal frequency 11.04962 MHz. The oscillator formed by the crystal, capacitor and an on-chip inverter generates a pulse train at the frequency of the crystal. The clock frequency f establishes the smallest interval to accomplish any simple instruction. 7.8 Address Latch Enable (ALE) (Pin 30): AD0-AD7 is multiplexed in Port 0. To demultiplex these lines to obtain the lower half of address i.e., A0 A7, an external latch and ALE signal of 8051 is used. 7.9 Reset(RST) (Pin 9): Used to reset 8051. For proper reset operation the RST pin must be held high for at least 2 machine cycles, while oscillator is running. 7.10 7.11 Program Store Enable (PSEN) (Pin-29): It is active low output control signal, used to activate the enable signal of external ROM/EPROM. It is activated every 6 oscillator periods while reading external memory. Thus this signal acts as read strobe to external program memory. External Access (EA) (Pin-31): When EA pin is high (connected to Vcc), the program fetches the codes, from the internal ROM, for address 0000h to 0FFFh, and beyond this address range fetches codes from the external ROM (1000h 0FFFFh). When EA pin is low (connected to Vss/GND), all addresses 0000h 0FFFFh are fetched from external ROM only. 7.12 Ports:
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8051 has 32 I/O pins configured as 4, 8 bit parallel ports (P0 P3). All 4 ports are bidirectional, can be configured as either input or output or both. All port pins are multi functional except pins of Port 1. Each port consists of latch, output driver and input buffer. PORT0(Pins 31-39): Port -0 has 8 pins identified as P0.0-P0.7. The structure of a Port-0 pin is shown in fig 1.9. Port-0 can be configured as a normal bidirectional I/O port or it can be used for address/data interfacing for accessing external memory. When control is '1', the port is used for address/data interfacing. When the control is '0', the port can be used as a normal bidirectional I/O port.

Fig. 1.9 Port -0 Pin Structure Let us assume that control is '0'. When the port is used as an input port, '1' is written to the latch. In this situation both the output MOSFETs are 'off'. Hence the output pin floats. This high impedance pin can be pulled up or low by an external source. When the port is used as an output port, a '1' written to the latch again turns 'off' both the output MOSFETs and causes the output pin to float. An external pull-up is required to output a '1'. But when '0' is written to the latch, the pin is pulled down by the lower MOSFET. Hence the output becomes zero. When the control is '1', address/data bus controls the output driver MOSFETs. If the address/data bus (internal) is '0', the upper MOSFET is 'off' and the lower MOSFET is 'on'. The output becomes '0'. If the address/data bus is '1', the upper transistor is 'on' and the lower transistor is 'off'. Hence the output is '1'. Hence for normal address/data interfacing (for external memory access) no pull-up resistors are required. Port-0 latch is written to with 1's when used for external memory access.

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PORT-1 (Pins 1-8): Port-1 has 8 pins (P1.1-P1.7) .The structure of a port-1 pin is shown in fig 1.10.

Fig 1.10 Port 1 Pin Structure Port-1 does not have any alternate function i.e. it is dedicated solely for I/O interfacing. When used as output port, the pin is pulled up or down through internal pull-up. To use port-1 as input port, '1' has to be written to the latch. In this input mode when '1' is written to the pin by the external device then it reads fine. But when '0' is written to the pin by the external device then the external source must sink current due to internal pull-up. If the external device is not able to sink the current the pin voltage may rise, leading to a possible wrong reading. PORT-2(Pins 21-28): Port-2 has 8-pins (P2.0-P2.7) . The structure of a port-2 pin is shown in fig 1.11

Fig. 1.11 PORT 2 Pin Structure Port-2 is used for higher external address byte or a normal input/output port. The I/O operation is similar to Port-1. Port-2 latch remains stable when Port-2 pin are used for external memory access. Here again due to internal pull-up there is limited current driving capability.
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PORT-3 ((Pins 10-17):

Fig. 1.12 PORT 3 Pin Structure: Each pin of Port-3 can be individually programmed for I/O operation or for alternate function. The alternate function can be activated only if the corresponding latch has been written to '1'. To use the port as input port, '1' should be written to the latch. This port also has internal pull-up and limited current driving capability. Alternate functions of Port-3 pins: P3.0 RxD P3.1 TxD P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 7.13 Power Supply Pins (Vcc- pin 40, Vss/GND- pin 20): 8051 operates using DC power supply of +5 V with respect ground, with a rated power supply current of 125 mA. T0 T1

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8. PIN DIAGRAM OF 8051:

Fig.1.13 Pin configuration of 8051

9. MEMORY ORGANIZATION:
The 8051 has Harvard architecture which uses the same address in different memories for code and data The internal circuitry accesses the current memory based on the nature of operation in the program. 9.1 Internal RAM: The 128 bytes internal RAM is organized into 3 distinct areas, as shown in fig 1.14: o 32 bytes from address 00h to 1fh that make up 32 working registers organized as 4 memory banks of 8 registers each. The 4 register banks are numbered 0 to 3 and are made up of 8 registers named R0 to R7. Each register can be addressed by name or by its RAM addresses. Thus R0 of bank3 is R0 (if bank3 is selected) or address 18h (where bank3 is selected). Bits RS0 and RS1 in the PSW determine which bank of registers is currently in use at any time when program is running. Register banks not selected can be used as general purpose RAM. Bank0 is selected by default on reset. o A bit addressable area of 16 bytes occupies RAM byte addresses 20h to 2fh, forming total of 128 bits. An addressable bit may be specified by its bit address of 00h to 7fh or 8 bits may form any byte address from 20h to 2fh.For example bit address 4fh is also bit 7 of byte address 29h. Addressable bits are useful when the program need only remember a binary event. o A general purpose RAM area above the bit area from 30h to 7f h, addressable as byte.

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Fig.1.14. Internal RAM structure 9.2 Special Function Registers (SFR): Specific function register (SFR) are addressed using addresses from 80h to 0FFh. Some SFRs are also bit addressable as is the case for the bit area of RAM. This feature allows the programmer the programmer to change only what needs to be altered leaving the remaining bits in that SFR unchanged. Not all of the addresses from 80h to 0FFh are used for SFRs. Only the addressed ones can be used in programming SFRs and equivalent internal RAM addresses are shown in Fig.1.15. SFR Memory Map: The set of Special Function Registers (SFRs) contain important registers such as Accumulator, Register B, and I/O Port latch registers, Stack pointer, Data Pointer, Processor Status Word (PSW) and various control registers. Some of these registers are bit addressable (they are marked with a * in the Fig. 1.15 below).
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The PC is not part of the SFR and has no internal RAM address. SFRs are named in certain opcodes by their function names as A, TH0 and can also be referred by their addresses. ADDRESS Special Function Registers 0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H 0C0H 0B8H 0B0H 0A8H 0A0H 98H 90H 88H IP* P3* IE* P2* SCON* P1* TCON* P0* 80H 80H 81h 82h 83h 84h 85h 86h TMOD TL0 SP DPL TL1 DPH TH0 TH1 PCON SBUF PSW* (T2CON)* (RCAP2L) (RCAP2H) (TL2) (TH2) ACC* B*

Fig.1.15 Special Function Registers and the addresses

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9.3 Internal ROM: 8051 is organized so that data memory and program code memory can be two entirely different physical memory entities. Each has the same address ranges. The internal program ROM occupies code address space 000h to 0FFFh. The PC is normally used to address program code bytes from address 0000h to 0FFFFh. Program addresses higher than 0FFFh which exceed the internal ROM capacity will cause the 8051 to automatically fetch code bytes from external memory, addresses 00h to 0FFFFh by connecting the external access pin (EA) to ground.

10.EXTERNAL MEMORY INTERFACING:

The system designer is not limited by the amount of internal ROM and RAM available on chip. Two separate external memory spaces are made available by the 16 bit Program Counter PC and DPTR and by different control pins for enabling the external ROM and RAM chips, respectively. The figure 1.16 shows the connection between an 8051 and external memory.

Fig.1.16 Diagram for Interfacing of External Memory External program memory is fetched if either of the following two conditions is satisfied. Enable Address) is low: The microcontroller by default starts searching for program from external program memory. PC is higher than 0FFFH for 8051. tells the outside world whether the external memory fetched is program memory or data memory. is user configurable. is processor controlled. Accessing external memory: Access to external program memory uses the signal as the read strobe. Access to external data memory uses For external program memory, always 16 bit address is used.
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(Program store enable)

(alternate function of P3.7 and P3.6).

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11. THE STACK: The stack refers to an area of internal RAM that is used to store and retrieve data quickly. The 8 bit Stack Pointer (SP) register is used by the 8051 to hold internal RAM address that is called the top of the stack. The address in SP register is the location in internal RAM where the last byte of the data was stored by stack operation. When data is to be placed on the stack, the SP increments before storing data on the stack so that the stack grows up as data is stored. Whenever data is retrieved from the stack, the byte is read from the stack and then the SP decrements to point to the next available byte of stored data. Operation of the Stack and Stack Pointer: Operation of the stack is shown in the figure 1.17. The SP is set to 07 when the 8051 is reset and can be changed to any internal RAM address by the programmer. The stack is limited in height to the size of internal RAM. Since SP=07h, when the 8051 is powered up, the first location of stack RAM is 08h, which also belongs to register R0 of bank 1. In other words bank 1 and stack are using the same memory space. If in a given program we need to use bank 1 and 2 with stack operation there occurs conflict between stack and the register contents of bank 1. The stack can overwrite valuable data in register banks, bit addressable RAM and scratched pad RAM areas. It is programmers responsibility to make it sure that the stack does not grow beyond predefined bounds. The stack is normally placed high in the internal RAM by an appropriate choice of the number placed in SP register, to avoid conflict with registers or RAM.

Fig 1.17: Stack Operation

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