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  • Project 2 Design Group 6

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    Nageshwar Reddy
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    Bus Controller Main Memory OR1200 CPU Instruction Cache Wishbone I / F Timer D S P Power Management Debug I / F Interrupts Hardware accelerator Hardware accelerator. Bus controller Test cases for read hit, read miss, write hit, write miss.

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    Bus Controller Main Memory OR1200 CPU Instruction Cache Wishbone I / F Timer D S P Power Management Debug I / F Interrupts Hardware accelerator Hardware accelerator. Bus controller Test cases for read hit, read miss, write hit, write miss.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPTX, PDF, TXT or read online from Scribd
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    10 views8 pages

    Project 2 Design Group 6

    Uploaded by

    Nageshwar Reddy
    Bus Controller Main Memory OR1200 CPU Instruction Cache Wishbone I / F Timer D S P Power Management Debug I / F Interrupts Hardware accelerator Hardware accelerator. Bus controller Test cases for read hit, read miss, write hit, write miss.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 8

    Project 2 Design

    Bingwei Liu Nagesh

    Architecture
    CPU0 L1 L1 CPU1

    Snooping

    Snooping

    Bus

    Bus Controller Main Memory

    OR1200 CPU
    Instruction Cache Wishbone I/F
    Timer D S P Power Management Debug I/F Interrupts Hardware accelerator Hardware accelerator

    F D E M W
    Data Cache

    Wishbone I/F

    Interfaces
    PM I/F DB I/F POWER MANAGEMENT DEBUG CPU/DSP / TICK TIMER DCache 16KB DWB System I/F

    ICache 16KB

    IWB

    INT I/F

    PIC

    Modify L1

    1-way 8KB Virtual Addressing

    2-way 16KB Physical Index

    2-way 16K L1
    4 19 9

    Tag: 19 bits Index: 9 bits Block Offset: 2 bits Byte Offset: 2 bits

    Cache Coherence

    TO DOs
    Modify L1 Add a main memory Design the bus controller Test cases for read hit, read miss, write hit, write miss

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