library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alu is
generic (N: natural:=8);
port(a,b:in bit_vector(N-1 downto 0) ;
s:in bit_vector(4 downto 0);
z:out bit_vector(2*N-1 downto 0));
end alu;
architecture alu_a of alu is
begin
process(a,b,s)
variable z1:bit_vector(2*N-1 downto 0);
variable a2,b2:integer;
variable a1,b1:std_logic_vector(N-1 downto 0);
begin
a1:=To_StdLogicVector(a);
b1:=To_StdLogicVector(b);
a2:=CONV_INTEGER(a1);
b2:=CONV_INTEGER(b1);
case s is
when "00000" => if a(7)='1' and b(7)='1'then
z1:="00000001" & To_bitvector(a1 + b1);
else
z1:="00000000" & To_bitvector(a1 + b1);
end if;
when "00001"=>z1:="00000000" & To_bitvector(a1 - b1);
when "00010"=>z1:=To_bitvector(a1 * b1);
when "00011"=>z1:="00000000" & To_bitvector(conv_std_lo
gic_vector(a2 / b2,8));
when "00100"=>z1:="00000000" & To_bitvector(a1 - 1) ;
when "00101"=>z1:="00000000" & To_bitvector(b1-1);
when "00110"=>z1:="00000000" & To_bitvector(a1+1);
when "00111"=>z1:="00000000" & To_bitvector(b1+1);
when "01000"=>z1:="00000000" & To_bitvector(a1 or b1);
when "01001"=>z1:="00000000" & To_bitvector(a1 and b1);
when "01010"=>z1:="00000000" & To_bitvector(a1 nor b1);
when "01011"=>z1:="00000000" & To_bitvector(a1 nand b1);
when "01100"=>z1:="00000000" & To_bitvector(a1 xor b1);
when "01101"=>z1:="00000000" & To_bitvector(a1 xnor b1);
when "01110"=>z1:="00000000" & To_bitvector(not a1);
when "01111"=>z1:="00000000" & To_bitvector(not b1);
when "10000"=>z1:="00000000" & To_bitvector((not a1) + 1
);
when "10001"=>z1:="00000000" & To_bitvector((not b1) + 1
);
when "10010"=>z1:="00000000" & a sll 1;
when "10011"=>z1:="00000000" & b sll 1;
when "10100"=>z1:="00000000" & a srl 1;
when "10101"=>z1:="00000000" & b srl 1;
when "10110"=>z1:="00000000" & a sla 1;
when "10111"=>z1:="00000000" & b sla 1;
when "11000"=>z1:="00000000" & a sra 1;
when "11001"=>z1:="00000000" & b sra 1;

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end case;
z<=z1;
end process;
end alu_a;

"11010"=>z1:="00000000" & a rol 1;

"11011"=>z1:="00000000" & b rol 1;
"11100"=>z1:="00000000" & a ror 1;
"11101"=>z1:="00000000" & b ror 1;
others =>z1:="0000000000000000";