07B21EC702 Basic Electronic Devices and Circuits Lab

List of Experiments:
1. To study the forward and reverse bias (volt-ampere) characteristics of a simple pn junction diode. Also determine the forward resistance of the diode and develop a linearized model. 2. Realization of desired wave shapes using clipper and clamper circuits. (Use sinusoidal/square wave as an input signal.). 3. To study the performance of a half/full wave rectifier in terms of ripple factor and efficiency. 4. To study the forward and reverse bias volt-ampere characteristics of a zener diode. Also determine the breakdown voltage, static and dynamic resistances. Draw inferences from the same. 5. To set up a voltage regulator circuit using zener diode for minimum and maximum current specifications. 6. To determine the operating point for a given load by plotting the output characteristics of a common emitter BJT. Also determine the input characteristics. 7. Design a single-stage RC coupled JFET amplifier for the given parameters in common source configuration and study the gain variation with frequency. 8. To determine the frequency response of single-stage RC coupled BJT amplifier and study the effect of the emitter bypass capacitor on the response. 9. To study op-amp as a square wave generator. (Op-amp schmitt trigger). 10. To design and study Wien Bridge Oscillator using op-amp. 11. To verify the truth tables of OR, AND, NOR, NAND and XOR gates.

Experiment No. -1 Aim: - i) To study the forward and reverse bias (volt-amp) characteristics of a p-n junction diode. ii) Determine the forward resistance of the diode and develop a linearized model. Components Required: 1N4001 Resistor (1k) DC regulated power supply Multimeter - One -One -One - One

Theory: The diode is a semiconductor device formed from a junction of n-type and ptype semiconductor materials. The lead connected to p-type material is called as anode and the lead connected to n-type material is called cathode.

Fig1: (a) Diode Symbol (b) Actual diode When diode is in forward bias (higher potential is connected to the anode lead), current flows through it. As the voltage across diode increases, current also increases. It is observed that the rate of change in current increases with increase in the voltage across diode. After some potential drop across the diode, the rate of change in current increases rapidly. The potential drop after which current increases rapidly is called as Cut in Voltage. It is measured by drawing a tangent on the slope of the V-I Characteristics from where current increases drastically. For Germanium diode is it around 0.2-0.3V, while for Silicon diode it is 0.4-0.7V. When diode is in reverse bias (higher potential is connected to the cathode lead), ideally no current flows through it, practically a very small leakage current (in micro ampere) flows due to some impurity charge carriers. In the p-n junction diode the value of reverse breakdown voltage is very high (-600V for 1N4001). If this voltage is applied in the reverse bias, then very high value of current will flow and diode will get damaged. The characteristic curve for an ideal diode and practical diode is shown in Fig2.

Fig2. V-I characteristics of Ideal and Practical Diode. While analyzing circuits, the practical diode is usually replaced with a simpler model. In the simplest form, the ideal diode is modeled by a switch as shown in Fig (3). The switch is closed when the diode is forward biased and open when reverse biased. The real diode is modeled as shown in Fig (4). Rf and Rr are the resistances offered by the diode in the forward bias and reverse bias respectively. Vy is the cut-in voltage of the diode.

Fig3. Equivalent model of ideal diode

Fig4. Equivalent model of practical diode.

Circuit Diagram:

Procedure: 1. Study the characteristics of the diode in the data sheet. Copy all the specification for the diode in your final lab report. 2. Connect the circuit as shown in Circuit Diagram 3. Connect voltmeter across diode and resistor respectively. 4. Vary the input voltage (as shown as 15Vdc in figure) from -5 to 5 volt in the step of 0.1 volt and note down the reading across diode and resistor. 5. Calculate the current flowing through the resistance. 6. Now plot the graph between the current flowing through the diode and potential across the diode. 7. From this graph, obtain the cut-in voltage for the diode. From the point where current increases sharply, draw a line to x-axis. The point where it intersects on the x-axis is called cut-in voltage. 8. Measure the slope of the curve to calculate the resistance offered by the diode in the forward bias as well as reverse bias. Forward bias resistance is named as Rf and reverse bias resistance is named as Rr as shown in Fig4. Observation: Sr. No. Resistor Voltage(Vr) Current (I)=Vr/R Diode Voltage(Vd) Slope (Vd/I)

Results: Vy = Rr = Rf =

Learning Outcomes

Experiment 2: Aim
Realization of desired wave shapes using clipper and clamper circuits. (Use sinusoidal/square wave as an input signal.).

Components Required
1. 2. 3. 4. 5. 6. 7. 8. 9. 0.1 MFD capacitor 01 100 MFD capacitor 01 100 K ohm resistance 01 10 K ohm resistance 01 1 K ohm resistance 01 Diodes IN4007 02 DC Power Supply Connecting wires Breadboard

Theory
The circuit with which the waveform is shaped by removing (or clipping) a portion of the input signal without distorting the remaining part of the alternating waveform is called a clipper. Clipping circuits are also referred to as voltage (or current) limiters, amplitude selectors, or slicers. These circuits find extensive use in radars, digital computers, radio and television receivers etc. In a clipping circuit, the output voltage will be proportional to the input voltage as long as the input lies between the specified reference levels. Outside this range, the output is clipped it remains essentially constant, no longer dependent on the input. Clipping circuits find important uses in wave shaping and signal processing applications. Often in the development of electronic circuits it is required that voltages be limited in some manner to avoid circuit damage. Furthermore, the limiting or clipping of voltages can be very useful in the development of wave-shaping circuits. A typical clipper circuit is shown in Figure 1. In this circuit the output voltage can never be greater than 3 V. The ideal diode becomes forward biased at Vo equal to 3 V and this ties the output directly to the 3 V supply. The waveform can be clipped on the negative side by placing the series combination of a diode and power supply in parallel with the diode and power supply already shown.

Figure 1: Diode clipping circuit showing input and output waveforms While clipper circuits are concerned primarily with limiting or cutting off part of the waveform, clampers are used primarily to shift the DC level. For example, if we have a clock signal that swings between 0v and 5V but our application requires a clock signal from -5V to 0V, we can provide the proper DC offset with a passive clamper circuit. A typical clamper circuit is shown in Figure 2. For this circuit to work properly the pulse width needs to be much less than the RC time constant of 10 ms. The input square wave with a frequency of 1 KHz and a pulse width of 0.5 ms meets this requirement. The diode and power supply as shown will prevent the output voltage from exceeding 3 V (i.e., all of the region above 3 V can be viewed as a forbidden region for output voltage). Because of the time constant requirement the voltage across the capacitor can not change significantly during the pulse width, and after a short transient period the voltage across the capacitor reached a steady state offset value. The output voltage is simply the input voltage shifted by this steady state offset. Also, observe that the peak-to-peat output voltage is equal to the peak-to-peak input voltage. This is true because the voltage across the capacitor can not change instantaneously and the full change of voltage on the input side of the capacitor will likewise be seen on the output side of the capacitor.

Figure 2: Diode clamper circuit showing input and output waveforms

Procedure: A. Clipper Circuits:

A.1: Connect the circuit in Figure 3.1 and set the input voltage Vs to a 1 kHz sine wave of at least 1V peak amplitude. Sketch the shape of the output voltage waveform for this "clipper" circuit. A.2: Add a dc voltage source V1 as shown in Figure 3.2 to the circuit, and set the input signal to a 10kHz triangular wave of 20 volts peak to peak. Vary V1 over the range 0 to 15 volts. For each value of V1 , observe and sketch the output waveform . A.3: Add a second diode and voltage source V2 (Figure 3.3). Connect V2 in the polarity shown or you might burn the diodes! Experiment with different levels of V1 and V2. Make sketches and comment. This circuit is similar to the limiting circuits used in FM radio receivers. Set V1 to about +8V and reverse the polarity of V2 to a positive voltage of +5V. V1 and V2 now have the same polarity. (Note: V2 must be less than V1, or you will burn the diodes). Sketch the waveform. Comment. A.4: Connect the circuit in Figure 3.4. Let VS be a 1 kHz triangular wave with amplitude of 20 V peak to peak. Sketch 3 output waveforms with different values of V1 between 1V and 10 V.

Fig 3.1

Fig 3.2

Fig 3.3

Fig 3.4

B. Clamper Circuits:
B.1: Connect the circuit shown in Figure 4.1. Set Vi to a 50 Hz triangular wave with a peak amplitude of 10V. Draw the output waveform. B.2: Connect the circuit shown in Figure 4.2. Set Vi to a 50 Hz square wave with a peak amplitude of 12V. Draw the output waveform.

Fig 4.1

Fig 4.2

Observations:
Draw the Output waveforms of the clipper circuit as obtained in steps A.1 to A.4, and the output waveforms of the clamper circuits as obtained in steps B.1 and B.2.

Results:
a). Did the outputs of the clipper circuits in the steps A.1 to A.4 of the procedure work as expected?

b). Did the outputs of the clamper circuits in the steps B.1 to B.2 of the procedure work as expected?

Learning Outcomes (Summary):

Answer the following questions: self-study

Q.1 :

Q.2:

Q.3:

Q.4:

Q.5:

Q.6:

Exp No: 3 Aim:

To study of the performance of half /full wave rectifier in term of ripple factor and efficiency.

COMPONENT REQUIRED: Sl.No Component Diode 1 2 3 4 5 6 Resistance Transformer Bread board Connecting wires CRO

Specifications IN4007

quantity 1 half wave & 4 full wave 1k 1 1

THEORY Half wave and full wave bridge rectifier: In half wave rectification, single diode act as a half wave rectifier. The A.C. supply to be rectified is applied in series with diode and load resistance RL. A.C. supply is given through a transformer. During positive half cycles of input A.C. voltage, this make diode forward biased and hence it conducts current. During negative half cycles, diode is reverse biased and it conducts no current. Therefore, current flow through the diode during positive half cycles of A.C. input voltage only. it is blocked during negative half cycles. Full wave bridge rectifier, current flow through the load in the same direction for both half cycles of input A.C. its contain four diode D1, D2, D3, D4 connected to form bridge. The A.C supply to be rectified is applied to the diagonally opposite end of the bridge trough the transformer. Between two other ends of the bridge, the load resistance

RL is connected. During the positive half cycle of A.C. input voltage D1 & D3 forward biased while diode D2 &D4 are reversed biased. Therefore only diode D1& D3 conduct. These two diode will be in series through the load. Current flow through load. During negative half cycles diodes D2&D4 becomes forward biased whereas D1 and D3 become reverse biased. Therefore only D2&D3 conduct .these diodes will be in series through the load RL. Current flow through load. CIRCUIT DIAGRAM

Half wave rectifier

Full wave bridge rectifier Procedure: 1. Connect the circuit as shown in figure. 2. Apply A.C. supply through transformer; 3. Find the current through load resistance. 4. Observed voltage wave across the load on CRO.

4 find the value of ripple factor and efficiency Plot the graph between VBE and IB for VCE. Calculation for half wave rectifier Ripple Factor

Efficiency of half wave rectifier Efficiency, is the ratio of the dc output power to ac input power

Calculation of full wave bridge rectifier:

Ripple Factor The ripple factor for a Full Wave Rectifier is given by

Efficiency Efficiency, h is the ratio of the dc output power to ac input power

Result: Voltage wave form across the load: Ripple factor: Efficiency:

Learning outcomes:

Exp No: 4 Aim:

To study the forward and reverse bias volt-ampere characteristics of a zener diode. Also determine the breakdown voltage, static and dynamic resistances. COMPONENT REQUIRED: Sl.No Component Zener Diode 1 2 3 4 5 Resistance Bread board Connecting wires Dc supply 0-10v 1k 1

Specifications VZ=6.8V

quantity 1

THEORY The circuit diagram to plot the VI characteristics of a zener diode is shown. Zener doide is a special diode with increased amounts of doping. This is to compensate for the damage that occurs in the case of a pn junction diode when the reverse bias exceeds the breakdown voltage and thereby current increases at a rapid rate. Applying a positive potential to the anode and a negative potential to the cathode of the zener diode establishes a forward bias condition. The forward characteristic of the zener diode is same as that of a pn junction diode i.e. as the applied potential increases the current increases exponentially. Applying a negative potential to the anode and positive potential to the cathode reverse biases the zener diode. As the reverse bias increases the current increases rapidly in a direction opposite to that of the positive voltage region. Thus under reverse bias condition breakdown occurs. It occurs because there is a strong electric filed in the region of the junction that can disrupt the bonding forces within the atom and generate carriers. The breakdown voltage depends upon the amount of doping. For a heavily doped diode depletion layer will be thin and breakdown occurs at low reverse voltage and the breakdown voltage is sharp. Whereas a lightly doped diode has a higher breakdown voltage. This explains the zener diode characteristics in the reverse bias region.

The maximum reverse bias potential that can be applied before entering the zener region is called the Peak Inverse Voltage referred to as PIV rating or the Peak Reverse Voltage Rating (PRV rating).

CIRCUIT DIAGRAM

Procedure: 1. Connect the circuit as shown in figure. 2. Apply DC supply as shown in the figure. 3. Measure the value of VZ and IZ, VR Reverse biased. 4. Reapeat the all step with opposite polarity of zener diode. 5 Measure the value of VZ and IZ, VF Reverse biased. 5. Plot the curve between Voltage and current for forward and reverse biased zener diode. OBERVATION: S.No 1 2 3 5 Forward biased VF VZ IZ Reverse biased VR VZ IZ

Result:
Plot for reverse biased and forward biased zener diode: Bread down voltage value: Static resistance = Vz/Iz Dynamic resistance value: change in zener voltage/change in current through zener diode.

Learning outcomes:

Experiment No.6 Aim : To determine the operating point for a given load by plotting the output characteristics of a common emitter BJT. Also determine the input characteristics. Components Required: 1. 2N2222 silicon transistor or the equivalent 2. DC power supply 3. Resistors: 1-1k, 1-100, assorted values from stock 4. Potentiometers: 1-1M, 1-50k, 1-10k (preferable 10-turn) 5. Digital multi-meters 6. Breadboard

Theory The transistor bias method discussed in this experiment is the common emitter, Figure 1. The common terminal is the one that will be common to input and output in an ac amplifier.

Figure 1: Input and Output Voltages and Currents for NPN and PNP Transistors in the CE Configuration

The transistor bias arrangement used most frequently is called the common emitter configuration, in which the emitter terminal is grounded. In the common emitter configuration the input current and voltage are IB and VBE respectively. The output current and voltage are IC and VCE. The ratio of collector current to base current is called the current gain, :

I I

C B

= h FE

The relationship between and is:

, where is the current transfer ratio

and is also called common base dc current gain. Figure 2 shows the input characteristics of the common emitter biasing configuration. These characteristics display the relationship between base current and base-to-emitter voltage for a constant collector-to-emitter voltage:

Figure 2

Figure 3 shows the output characteristics of the common emitter configuration. These characteristics display collector (or emitter) current versus collector-to-emitter voltage, for a constant base current:

Figure 3
Load Line : The operating point of a BJT can be found graphically using the concept of load line .A load line is the relationship between iC and vCE that is imposed on BJT by the external circuit . For a given value of iB , the iC and vCE characteristics curve of a BJT is the relationship between iC and VCE as is set by BJT internals. The intersection of the load line with the BJT characteristics represent a pair of iC and vCE values which satisfy both conditions and , therefore ,is the operating point of BJT (often called the Q point or Quiescent Point . The equation of load line include only iC and vCE as unknowns. iC

VCE

Figure 4

Circuit Diagram

Figure 5

Procedure 1. To determine the input characteristics of the common emitter configuration, connect the Fig 5.

2.

Adjust the 1M and 10k potentiometers to set VCE and VBE as shown in Table 1. Measure and record the voltage across the 1k resistor VRB, for each combination of VCE and VBE in Table 1 in your lab log. It may be necessary to use two DMMs in order to keep VCE constant. To determine the output characteristics of the common emitter configuration, set 10k potentiometer in the circuit of Figure 4 to its maximum setting. This will cause VCE to decrease to approximately 0V. Then adjust the 1M potentiometer to set IB to 10A--note that when VRB is 10mV, IB is 10A. Next adjust the 10k potentiometer for all values of VCE in Table 2 making sure that IB remains constant. Measure and record, in Table 2 in your lab log, the voltage across the 100 resistor VRC for each combination of VCE and IB in Table 2. Calculate the values of IB in Table 1, and plot the input characteristics of the common emitter bias circuit using the values of Table 1.

3.

4. 5.

6.

Calculate the values of IC in Table 2, and plot the output characteristics of the common emitter bias circuit using the values of Table 2. 7.For each value of VCE in Table 2, calculate the value of for the output characteristic corresponding to IB = 30A.

Observations Input Characteristics

Table 1 VCE = VBE VRB VCE =

V R

RB B

VBE

VRB

V R

RB B

0.64V 0.65V 0.66V 0.67V 0.68V 0.69V 0.70V

0.64V 0.65V 0.66V 0.67V 0.68V 0.69V 0.70V

Output Characteristics:

Table 2 IB = 10A VCE VRC

IC = V RC RC

IB = 20A VRC
IC = V RC RC

IB = 30A VRC
IC = V RC RC

IB = 40A VRC
IC = V RC RC

IB = 50A VRC
IC = V RC RC

0.2V 0.4V 0.8V 1V 3V 5V

Results: Learning Outcomes (Summary).

Experiment No. 7 Aim: - Design a single stage RC coupled JFET amplifier for the given parameters in common source configuration and study the gain variation with frequency. Components Required: N-channel JFET (2N5951, MPF 102 or equivalent) DC regulated power supply Capacitor (0.01F, 1F and 10F) Resistance (1M, 1K, 10K, 2.2K) Theory: The JFET transistor is a three terminal device. The terminals are labeled as drain (D), source (S) and gate (G). The current flows from drain to source. The magnitude of current is controlled by the voltage VGS applied between gate and source. For N-channel JFETS, VP and VGS are always negative. The Common Source Amplifier is one of the three basic FET transistor amplifier configurations. In comparison to the BJT common-emitter amplifier, the FET amplifier has much higher input impedance, but a lower voltage gain. The JFET offers very high input impedance along with very low noise figures. It is very suitable for extremely low-level audio applications as in audio preamplifiers. The biasing of JFET amplifier is same as biasing of BJT amplifier as shown below. In the common source JFET amplifier resistor RS is connected between source terminal and ground, while RG is connected in between gate terminal and ground. Thus gate is kept at zero potential. If drain current ID begins to rise above its intended quiescent value, the voltage drop across RS will increase. Since the gate source voltage VGS in the difference between the gate potential and the voltage across RS, a rise in the voltage across RS will cause VGS to drop, lowering ID back to its original value. And vice versa happens if ID begins to drop below its design value. The voltage gain of the circuit can be expressed as AV = gmRD Circuit Diagram:

Figure1. Common Source Amplifier

Procedure: 1. Connect the circuit as shown in figure. 2. Measure the operating point by keeping input voltage zero volts. 3. Apply a sinusoidal signal with frequency 1 kHz, and amplitude 100mV. 4. Observe the output. 5. Plot the input and output voltage waveforms 6. Now by changing the input voltage measure the output voltage and plot it. From the slope, calculate the gain and transconductance using the above formula. 7. Change the input signal frequency by keeping the same input voltage and plot the frequency response on semilog paper. 8. Observation:

Sr. No

Input Voltage

Frequency (Constant)

Output Voltage

gain

Sr. No.

Input voltage Frequency (constant)

Output voltage

gain

Result : Gain = Learning Outcomes

Transconductance =

Bandwidth =

Experiment No. 8 Aim: To determine the frequency response of single-stage RC coupled BJT amplifier and study the effect of the emitter bypass capacitor on the response. Components Required: Resistors: 2.2 K, 50 ohm, 30 K, 3.3 K, 10 K, 4.7 K Capacitors: 10 F (3) Transistor: BC547 Theory:

The behavior of an amplifier, that is, its gain, input resistance, and output resistance, over a given range of frequencies is called its frequency response. Ideally an amplifier should have an uniform frequency response over the wide range of signal frequencies. In case of BJT amplifiers we use coupling capacitors Ci (to couple input signal with amplifier) and Co (to couple output signal with load) so that the DC operating point does not perturbed due to the connection of input signal source and load to the amplifier. The bypass capacitor CE is used to bypass emitter resistor RE so that gain can be increased. In addition to these three physical capacitors, there are stray capacitances such as pnjunction capacitances inside the transistors. All these capacitances affect the frequency response of an amplifier. To study the effect of all the capacitors on the frequency response we have to perform the small signal analysis of RC coupled BJT amplifier. Fig. 1 shows the small-signal model of BJT that includes junction capacitances. Capacitance C is the base-emitter capacitance, and C is the collector-base capacitance.

rx B ib

C C

+
C r v gmv rce

E Figure 1. Small-signal model of BJT

The lower end and the upper end of the frequency range are affected by the presence of these physical and junction capacitors. In this experiment we are going to study the variation of gain as a function of frequency of applied signal.

Circuit Diagram:

VCC = +12 V

Rs 50

R1 30 k vin

RC 4.7 k

+
Ci 10 F

Co 10 F vout RL

vs

BC547
R2 10 k RE 2.2 k

+
CE 10 F

Figure 2. Common emitter amplifier with emitter degeneration bypass capacitor and DC blocking capacitors Procedure

Assemble the common emitter amplifier circuit shown in Figure 2 around a BC547 npn BJT and apply the power supply Vcc=+12 V. Without connecting the signal source measure the operating point values of voltage and currents (eg. IC, VCE) . Perform the D.C operating point analysis and compare your results with measured values. Connect the signal source vs with peak-to-peak amplitude of 20 mV. Vary the frequency and note down the peak-to-peak amplitude of vout. Plot the magnitude of the gain of the amplifier in dB vs. frequency (f). Use a logarithmic scale for the frequency. The gain expressed is dB is calculated using

gain in dB = 20 log

vout , vs

in which the common logarithm (base 10) is used. Note down the lower and upper cut-off frequency of an amplifier.
Observations: 1. Vin =

Observation No.

Frequency (kHz)

Vout (V)

Gain (dB)

Lower cut-off frequency fL = Upper cut-off frequency fU =

2. Disconnect the emitter bypass capacitor CE and repeat the above procedure. Results Learning Outcomes (Summary).

Experiment No:9 Aim: To study Op-Amp as a square wave generator(Schmitt Trigger circuit). Components Required: S.No. 1. 2. 3. Name of Component Op-Amp Resistor Dual Power supply Specification IC 741 1k,11k 12-15V DC

Circuit Diagram:

Theory: The Schmitt trigger is essentially a comparator in which the reference voltage is derived from a divided fraction of the output voltage. As in the comparator, the output is forced to either a positive or negative saturation limit whenever the magnitude of input voltage exceeds that of the threshold voltage. Unlike the comparator, the Schmitt trigger remembers its most recent positive or negative output and hold its output voltage even when the input voltage returns to zero. As seen from the circuit diagram, the threshold voltage is the voltage across the resistor R1 and can be found using the voltage divider rule. When vo=+Vsat, the upper threshold voltage is given by,

Vut =

R1 (+Vsat ) R1 + R2

When vo=-Vsat ,lower threshold voltage is given by,

Vlt =

R1 (Vsat ) R1 + R2

The output voltage of an Op-Amp is given by,

Vo = A(v1 v 2 ) = Avid
When the input voltage crosses the upper threshold,v2 becomes more than v1.Thus the output,as given from the above equation,results in switch from +Vsat to Vsat. And when input voltage falls below the lower threshold voltage,output switches from Vsat to +Vsat.This results in a square wave generation. Procedure: 1.Select upper and lower threshold voltage levels(say 1V).Assume the value of R1(say 1k). 2.Using the Vut expression(Vsat=Vcc),obtain the value of R2(for given R1,R2=11k). 3.Set up the circuit as shown in figure. 4.Apply a sine wave of frequency 5Vp-p,1kHz at input(pin2) and observe the output(pin6) on CRO. 5.Also observe for what input voltage does the switching stops. Observation:

Result: It is observed that the output switches between +Vsat and Vsat whenever the input voltage crosses the threshold voltage. Learning Outcome: If the upper and lower threshold voltages are made larger than the input noise voltages,this circuit eliminates the false output transitions.

Experiment No. 10 WEIN BRIDGE OSCILLATOR AIM:

To design and study Wien Bridge Oscillator using op-amp for a given oscillation frequency f0 = _____.

COMPONENTS REQUIRED:

Sl.No 1. 2. 3. 4. 5. 6. 7. 8.

Components and Instruments Resistor Capacitor Breadboard Probes Oscilloscope 15 V Power supply OPAMP 741 Multimeter

Value and Rating 1k, 3k,10k (or) 470, 1k, 10k 8.2nF(or) 6.8nF

Quantity 1,1,2 Nos. correspondingly 2 Nos. 1 No. 2 Nos. 1 No. 1 No. 1 No. 1 No.

THEORY: PRINCIPLE:

The purpose of this experiment is to explore the design of sine wave oscillators. A sine wave oscillator is basically a rudimentary function generator. Thus, we will, in effect, be exploring the basic principles of the design of function generators. The design of Wien bridge oscillator relies on the principle of utilizing positive feedback to produce unstable circuit behavior.

Positive feedback

Figure 10 -1 shows the basic block diagram for positive feedback. The gain of the feed forward network is A(s), and the gain of the feedback network is .

V (s) S

V I

A(s) B(s)

V (s) o

VF

Figure 10 -1 Basic block diagram for positive feedback

The gain of this block diagram is given in equation 1.

VO ( s ) A( s ) = VS ( s ) 1 A( s ) ( s )

A f ( s) =

(1)

Notice that the denominator can become zero, which would cause the transfer function to be infinite. Thus the system could have a non-zero output with zero input amplitude. In such a case, the system is said to be unstable. This occurs when the loop gain, L(s), is:
L( s ) = A( s ) ( s ) = 1 Which results in

A f (s)

(2)

The A(s) (s) product plays a key role in oscillator design and is called the loop gain. Since positive feedback causes instability, systems are usually designed to avoid positive feedback. But in the case of an oscillator, unstable behavior is desired to generate the oscillation. Thus some amount of positive feedback is normally used in the design of oscillators. In fact, a sine wave oscillator can be constructed by designing a circuit such that the loop gain is unity. For oscillation to occur the loop gain must be exactly one. Remember that the loop gain is a function of frequency; therefore both,

L( s ) = 1 and L( s) = 0 + N 360

(3)

are required for oscillation. Oscillation will occur at a frequency such that the above two conditions are met. In equation (3) N is the number of rotations or cycles. Wien Bridge oscillator investigated in this experiment consists of two separable parts. The A(s) network will be the amplifier part, and the (s) network will be the frequency determining part. It is not always possible to do this, but for oscillator in this experiment it is possible and also possible for phase RC oscillator.

Wien bridge oscillator

Figure 10 -2 shows the Wien bridge oscillator. The A(s) gain network is the inverting gain section of the op-amp. The (s) feedback network is the section between Va and Vo.
R2 2X.XK

R1 + RS 10K 2 3 1k 6

V0

Va

CS

CP 8.2 n

RP 10K

8.2 n

Figure 10 - 2 The Wien bridge oscillator

The magnitude and phase characteristics of A(s) are given by equation 4.

R2 and A(s) = 180 R1

A( s) =

(4)

Since oscillation occurs when L = 1 from Eq. 2 and 3 above the magnitude and phase characteristics of (s) must be equivalent to:
R1 and ( s ) = 180 + N 360 R2

( s ) =

(5)

This will happen for one value of R2 and at one frequency.

Design:

Figure 10-3 Altered Wein Bridge Oscillator The circuit in figure 10-2 can be altered as in figure 10-3. A practical oscillator circuit uses an op-amp and RC bridge circuit, with the oscillator frequency set by the R and C components. Resistors RS and RP and capacitors CS and CP form the frequency adjustment elements, and resistors R1 and R2 form the feedback path. The opamp output is connected as the bridge input at points a and c. the bridge circuit output at points b and d is the input to the input to the opamp.

Neglecting the loading effect and output impedances of the OPAMP, the analysis of the bridge circuit results in
R2 R S C P = + R1 R P C S

(6)

and f0 = 1 2 RS C S RP C P (7)

If, in particular, the values are RS=RP=R and CS=CP=C, the resulting oscillator frequency is

f0 = and

1 2RC

(8)

R2 =2 R1

(9)

Thus the ratio of R2 to R1 greater than 2 will provide sufficient loop gain for the circuit to oscillate at the frequency calculated using equation 8.

Design Example:

To design the RC elements of a Wien bridge oscillator for operation at f0 = 10kHz Using equal values of R and C, we can select R=100 k and calculate the required value of C using equation 8 1 1 = = 159 pF 2f 0 R 6.28 10 10 3 100 10 3

C=

)(

We can use R2= 300k and R1 = 100k to provide take place.

R2 greater than 2 for oscillation to R1

Procedure:

1. Connect the circuit shown in Figure 10 2. 2. Use a variable resistor for R2. 3. Adjust R2 so that the circuit oscillates and V0 is sinusoidal. 4. Record the value of R2 and the frequency of oscillation, f0. 5. Sketch V0. 6. Change CS= CP = 4.7 nF. 7. Measure and record the new fo and R2.
Observations:

Results:

(Attach graph sheet)

Learning outcomes: (summary)

Experiment No.11
AIM: To verify the truth table of OR,AND,NOT ,NAND and XOR gates. COMPONENTS REQUIRED : IC number 7400 7404 7408 7432 7486,74386 Description Quad 2-input NAND gates Hex inverters Quad 2-input AND gates Quad 2-input OR gates Quad EXCLUSIVE-OR gates

THEORY: In digital electronic circuits, two discrete voltages levels are recognized as two logic levels viz. logic 1 and logic 0. These are also known as HIGH and LOW logic levels. Depending upon the actual voltages, there are two types of logic circuits: (i) positive logicin which the higher voltage level corresponds to 1 (HIGH) and lower voltage levels corresponds to 0 (LOW), and (ii) negative logic-in which lower level correspond to logic 1 (HIGH) and the higher level corresponds to 0 (LOW). Figure 1.1(a) and (b) shows the positive and negative logic voltages levels. It may be noted that a specified range of voltages (as shown by the shaded regions in Fig. 1.1 ) represents the 1 or 0 logic level.

CIRCUIT DIAGRAM:

PROCEDURE: (i) AND gate: Identify the terminals of the 7408 quad, 2-input IC AND gate. Connect +5.0 V dc Between Vcc and GND terminals. Use +5 V for logic 1 and 0 V for logic 0. A section of the IC is shown in Fig 1.2 (a). Measure the output voltages given in Table 1.3 and verify the results with the truth table of AND gate given in Table 1.1. Check if the output voltages for the logic levels 1 and 0 correspond to the values given in Fig 1.1(a). Table 1.3 Various input combinations

A 0V 0V 5V 5V

B 0V 5V 0V 5V

(ii) OR gate: Repeat (i) for a 7432 quad, 2- input IC OR gate, a section of which is shown in Fig. 1.2 (b). (iii) NoT gate: Repeat (i) for a 7404 hex IC inverter, a section of which is shown in Fig.1.2 (c). (iv) NAND gate: Repeat (i) for a 7400 quad, 2- input IC NAND gate, a section of which is shown in Fig.1.2 (d). (v) EX-OR gate: Repeat (i) for a 7486 quad, IC EX-OR gate, a section of which is shown in Fig. 1.2 (e).

Figure .1.2

OBSERVATIONS:

RESULTS : LEARNING OUTCOMES: