Single Cycle Mi Ps

MIPS Processor Design
Department of Computer Science Faculty of Computer and Information Sciences Hosei University, Tokyo 184-8584 Japan http://cis.k.hosei.ac.jp/yamin/
Single-Cycle MIPS CPU p.1/31
Single-Cycle MIPS CPU

R-format instruction ( add, sub, and, or, slt )
31 26 25 21 20 16 15 11 10 6 5 0
op 6 bits
rs 5 bits
rt 5 bits
rd 5 bits
shamt 5 bits
func 6 bits
I-format instruction ( lw, sw, beq )

31 26 25 21 20 16 15 0
op 6 bits
rs 5 bits
rt 5 bits
immediate 16 bits
J-format instruction ( j )
31 26 25 0
op 6 bits
address 26 bits
9 Instructions Implemented in CPU Design

add $17, $18, $19 # $17=$18+$19 6-bit op 0 000000 5-bit rs 18 10010 5-bit rt 19 10011 5-bit rd 17 10001 5-bit shamt 0 00000 6-bit funct 32 100000
sub $17, $18, $19 # $17=$18$19 6-bit op 0 000000 5-bit rs 18 10010 5-bit rt 19 10011 5-bit rd 17 10001 5-bit shamt 0 00000 6-bit funct 34 100010

and $17, $18, $19 # $17=$18 AND $19 6-bit op 0 000000 5-bit rs 18 10010 5-bit rt 19 10011 5-bit rd 17 10001 5-bit shamt 0 00000 6-bit funct 36 100100
or $17, $18, $19 # $17=$18 OR $19 6-bit op 0 000000 5-bit rs 18 10010 5-bit rt 19 10011 5-bit rd 17 10001 5-bit shamt 0 00000 6-bit funct 37 100101

lw $17, 100($18) # $17=Memory[$18+100] 6-bit op 35 100011 5-bit rs 18 10010 5-bit rt 17 10001 16-bit Address 100 0000 0000 0110 0100
sw $17, 100($18) # $Memory[$18+100]=$17 6-bit op 43 101011 5-bit rs 18 10010 5-bit rt 17 10001 16-bit Address 100 0000 0000 0110 0100

beq $17, $18, 25 # if $17=$18, goto PC+4+25*4 6-bit op 4 000100 5-bit rs 17 10001 5-bit rt 18 10010 16-bit Address 25 0000 0000 0001 1001
j 10000 # jump to 10000 6-bit op 2 000010 26-bit Target address 2500 00 0000 0000 0000 1001 1100 0100

slt $17, $18, $19 # if $18<$19, $17=1; else $17=0 6-bit op 0 000000 5-bit rs 18 10010 5-bit rt 19 10011 5-bit rd 17 10001 5-bit shamt 0 00000 6-bit funct 42 101010
ALU
A[3..0] B[31..0]
mux4x32 Zero
a0[31..0]
a1[31..0] as32 y[31..0] a[31..0] S[31..0] s[31..0] b[31..0] sub ALUC[2..0] ALUC[2] ALUC[1] ALUC[0] 32 0,0,...,0,0,S[31] s1 s0 a3[31..0] a2[31..0] Result[31..0]
ALUC[2..0] Func 000 001 010 110 111 and or add sub slt
Instructions and or add, lw, sw sub, beq slt
Multiplexer
Multiplexer: input A0, A1, S; output Y; if (S==0) Y=A0; else Y=A1; S 0 0 0 0 1 1 1 1 Truth table Input Output A0 A1 Y 0 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1
Karnaugh Map and Circuit of Multiplexer

A0 0 A1 0 0 1 1 1 1 1 1 1 0 1 S A0 Y = S A0 + S A1 S A1 mux2x1 A0 Y A1 S A0 Y A1 S Symbol
S 0 1
N1[4..0]
mux32x32 a00[31..0] a01[31..0] ... y[31..0] Q1[31..0]
Single-Cycle MIPS=CPU $0 0 REGISTER

FILE 32 X 32 bits
dec5e ce NI[4..0] a[4..0] d0 d1 ... WE e d31 d[31..0] ce q[31..0] ... dffe32 $1 ck dffe32
gnd
a31[31..0] d[31..0] q[31..0] s[4..0]
Read port 1
mux32x32 a00[31..0] a01[31..0] ...
Write port
DI[31..0]
ck
d[31..0] q[31..0] $31 ck dffe32 ce s[4..0]
y[31..0]
Q2[31..0]
a31[31..0]
CK N2[4..0]
Read port 2
2-4 Decoder
Input Output e a1 a0 d3 d2 d1 d0 1 1 1 1 0 0 0 0 0 X 0 0 0 0 X 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0
2-4 Decoder
a0 a1 d0 dec2e a0 d0 a1 d1 d2 e d2 Symbol
d1
d2
d3
Circuit for R-Format Instructions

R-format op add/sub/and/or/slt rd, rs, rt # rd <= rs op rt rs rt rd func
op 4 PC[31..0]
ALUC[2-0] Cntl unit WriteReg
+
Inst. mem
func
RegFile rs rt N1 N2 Q1 A Zero rd ND DI CK Q2 B Result ALU WE
P C
Address Mem Data
Clock
Circuit for I-Format Instructions

I-format op lw rt, #immediate(rs) ; rt <= Memory[rs + immediate] rs rt immediate
op 4 PC[31..0]
ALUC[2-0] Cntl unit WriteReg
+
Inst. mem
RegFile rs N1 N2 Q1 rt A Zero ND DI CK Result Q2 B ALU Mem Data Address WE
P C
Address Mem Data
Data mem
Clock
immediate
Sign extend

I-format op sw rt, #immediate(rs) ; Memory[rs + immediate] <= rt rs rt immediate
op 4 PC[31..0]
WriteMem Cntl unit ALUC[2-0]
+
Inst. mem
RegFile rs rt N1 N2 Q1 A Zero ND DI CK Result Q2 B ALU Mem Data Write Data Address
P C
Address Mem Data
Data mem
WE
Clock
immediate
Sign extend

I-format op beq rs, rt, target ; if rs==rt, PC <= PC + 4 + immediate * 4 rs rt immediate
Zero op 4 PC[31..0] Cntl unit
Branch ALUC[2-0] WriteReg NPC[31..0] RegFile Shift left 2 WE N1 N2 Q1 A Zero Result ALU Q2 B 0
+
Inst. mem
rs rt
P C
Address Mem Data
ND DI CK
Clock
immediate
Sign extend
Circuit for J-Format Instructions

J-format op j target # PC <= address * 4 address
op
Cntl unit
Jump
address 4 PC[31..0] NPC[31..0]
Shift left 2
NPC[31..28],A[25..0],0,0 NPC[31..28]
1 0
+
Inst. mem
P C
Address Mem Data
Clock
Combine All Together

To combine all together, we add the following control signals: ALUSrcB 1: select immediate (for lw and sw instructions) 0: select register 1: select memory data (for lw instruction) 0: select ALU output
MemToReg
RegDes
1: select rt (for lw instruction) 0: select rd

R-format op
MIPS instruction format
Zero op
Jump
MemToReg WriteMem ALUC[2-0] ALUSrcB
rs
rt
rd
func
func Cntl unit
Branch
I-format op rs rt immediate
J-format op address
WriteReg RegDes address Shift left 2 1 NPC[31..28] 0 0
4 PC[31..0]
+
Inst. mem
NPC[31..0]
RegFile rs rt 1 rd ND 0 DI CK Q2 0 N1 N2 Q1 WE
Shift left 2
P C
Address Mem Data
Data mem
A Zero Result ALU B 1 Write data Mem Data Address 0 1 WE
Clock
immediate Sign extend
Single-cycle MIPS CPU


R-format op
Zero op
Jump
rs
rt
rd
func
func Cntl unit
Branch
J-format op address
4 PC[31..0]
+
Inst. mem
NPC[31..0]
Shift left 2
P C
Address Mem Data
Data mem
Clock
add, sub, and, or, slt


R-format op
Zero op
Jump
rs
rt
rd
func
func Cntl unit
Branch
J-format op address
4 PC[31..0]
+
Inst. mem
NPC[31..0]
Shift left 2
P C
Address Mem Data
Data mem
Clock
lw

R-format op
Zero op
Jump
rs
rt
rd
func
func Cntl unit
Branch
J-format op address
4 PC[31..0]
+
Inst. mem
NPC[31..0]
Shift left 2
P C
Address Mem Data
Data mem
Clock
sw

R-format op
Zero op
Jump
rs
rt
rd
func
func Cntl unit
Branch
J-format op address
4 PC[31..0]
+
Inst. mem
NPC[31..0]
Shift left 2
P C
Address Mem Data
Data mem
Clock
beq

R-format op
Zero op
Jump
rs
rt
rd
func
func Cntl unit
Branch
J-format op address
WriteReg RegDes address Shift left 2 NPC[31..28],A[25..0],0,0 NPC[31..28] 0 0 1
4 PC[31..0]
+
Inst. mem
NPC[31..0]
Shift left 2
P C
Address Mem Data
Data mem
Clock
j

R-format op
Zero op
Jump
rs
rt
rd
func
func Cntl unit
Branch
J-format op address
4 PC[31..0]
+
Inst. mem
NPC[31..0]
Shift left 2
P C
Address Mem Data
Data mem
Clock

Control Unit Design

Control Signals Jump Branch ALUSrcB ALUC[2] ALUC[1] ALUC[0] MemToReg RegDes WriteReg WriteMem and 0 0 0 0 0 0 0 0 1 0 or 0 0 0 0 0 1 0 0 1 0 add 0 0 0 0 1 0 0 0 1 0 Instructions sub 0 0 0 1 1 0 0 0 1 0 slt 0 0 0 1 1 1 0 0 1 0 lw 0 0 1 0 1 0 1 1 1 0 sw 0 0 1 0 1 0 X X 0 1 beq 0 Zero 0 1 1 0 X X 0 0 j 1 X X X X X X X 0 0
Control Unit Design

Jump Branch ALUSrcB ALUC[2] ALUC[1] ALUC[0] MemToReg RegDes WriteReg WriteMem = = = = = = = = = = j beq Zero lw + sw sub + slt + beq add + sub + slt + lw + sw + beq or + slt lw lw and + or + add + sub + slt + lw sw
Control Unit Design

Instructions add sub and or slt lw st beq j Rtype add ...
op[5-0] 000000 000000 000000 000000 000000 100011 101011 000100 000010
func[5-0] 100000 100010 100100 100101 101010 X X X X
= =
op[5] op[4] op[3] op[2] op[1] op[0] Rtype func[5] func[4] func[3] func[2] func[1] func[0]

R-format op
Zero op
Jump
rs
rt
rd
func
func Cntl unit
Branch
J-format op address
4 PC[31..0]
+
Inst. mem
NPC[31..0]
Shift left 2
P C
Address Mem Data
Data mem
Clock

Exercise
Design a single-cycle MIPS CPU that can execute the following 13 instructions: add, sub, and, or, slt, lw, sw, beq, j, bne, addi, andi, ori. addi $17, $18, 1 # $17=$181
6-bit op 8 001000 5-bit rs 18 10010 5-bit rt 17 10001 16-bit Immediate 1 1111 1111 1111 1111

Single Cycle Mi Ps

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Single Cycle Mi Ps

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MIPS Processor Design

Single-Cycle MIPS CPU p.1/31

Single-Cycle MIPS CPU

I-format instruction ( lw, sw, beq )

9 Instructions Implemented in CPU Design

Single-Cycle MIPS CPU p.3/31

9 Instructions Implemented in CPU Design

Single-Cycle MIPS CPU p.4/31

9 Instructions Implemented in CPU Design

Single-Cycle MIPS CPU p.5/31

9 Instructions Implemented in CPU Design

Single-Cycle MIPS CPU p.6/31

9 Instructions Implemented in CPU Design

Single-Cycle MIPS CPU p.7/31

Single-Cycle MIPS CPU

Instructions and or add, lw, sw sub, beq slt

Single-Cycle MIPS CPU p.8/31

Karnaugh Map and Circuit of Multiplexer

Single-Cycle MIPS CPU p.10/31

mux32x32 a00[31..0] a01[31..0] ... y[31..0] Q1[31..0]

Single-Cycle MIPS=CPU $0 0 REGISTER

a31[31..0] d[31..0] q[31..0] s[4..0]

mux32x32 a00[31..0] a01[31..0] ...

d[31..0] q[31..0] $31 ck dffe32 ce s[4..0]

Single-Cycle MIPS CPU p.12/31

Single-Cycle MIPS CPU p.13/31

Circuit for R-Format Instructions

ALUC[2-0] Cntl unit WriteReg

RegFile rs rt N1 N2 Q1 A Zero rd ND DI CK Q2 B Result ALU WE

Address Mem Data

Single-Cycle MIPS CPU p.14/31

Circuit for I-Format Instructions

ALUC[2-0] Cntl unit WriteReg

RegFile rs N1 N2 Q1 rt A Zero ND DI CK Result Q2 B ALU Mem Data Address WE

Address Mem Data

Single-Cycle MIPS CPU p.15/31

Circuit for I-Format Instructions

WriteMem Cntl unit ALUC[2-0]

RegFile rs rt N1 N2 Q1 A Zero ND DI CK Result Q2 B ALU Mem Data Write Data Address

Address Mem Data

Single-Cycle MIPS CPU p.16/31

Circuit for I-Format Instructions

Zero op 4 PC[31..0] Cntl unit

Address Mem Data

Single-Cycle MIPS CPU p.17/31

Circuit for J-Format Instructions

address 4 PC[31..0] NPC[31..0]

Address Mem Data

Single-Cycle MIPS CPU p.18/31

Combine All Together

1: select rt (for lw instruction) 0: select rd

Single-Cycle MIPS CPU p.19/31

Single-Cycle MIPS CPU

MIPS instruction format

MemToReg WriteMem ALUC[2-0] ALUSrcB

func Cntl unit

WriteReg RegDes address Shift left 2 1 NPC[31..28] 0 0

Address Mem Data

Single-cycle MIPS CPU

Single-Cycle MIPS CPU

MIPS instruction format

MemToReg WriteMem ALUC[2-0] ALUSrcB

func Cntl unit

WriteReg RegDes address Shift left 2 1 NPC[31..28] 0 0