Development of CPLD based memory controller for MPC 603E PPC based single board computer

Guided byMrs. K Sridevi , M.Tech, Associate Professor, GITAM

Presented byPriyanka Dhanorkar Roll No. 1221208108

Need for high performance & low power CPLD

Today one of the most critical factors in designing portable electronics is reducing overall system power consumption. Portable devices require longer battery life and higher performance. Even power reductions on the order of 10mW are important. One of the most important power saving techniques is the ability to manage the operating mode of devices in the system. Manufacturers offer devices with power saving modes that temporarily suspend the device from its normal operation & power down to a non-functioning state if the device is not active for a specific amount of time.

How to reduce power consumption?

By managing the operating mode of large power consumers on a PCB, such as the processor, the overall power consumption of the system can be reduced significantly. Reducing power consumption involves correct management of the operating mode of a device, and design a system that can operate device within. Off loading operations of the microprocessor allow it to stay in its low-power state for a longer amount of time thereby reducing system power consumption. One way to reduce system power is to allow a low-power programmable logic device, such as a CPLD, to manage these off loaded operations.

Microprocessor power consumption

In some portable applications, the CPU can consume 30 percent of the overall system power. Fig. shows the typical power consumption of system components in a Web Pad application. Microprocessor power consumption can range from 720W to 1W during normal operation. Microprocessor operating modes vary by part and includes modes such as normal, run, sleep, suspend, standby, stop, and idle operation.

Microprocessor Operating modes

Operating modes of the processor include normal, idle, and sleep. In normal operation, the CPU is full-on, with the device fully powered and receiving active clocks. In idle mode all clocks to CPU are stopped, with only clocks to the peripheral devices active. In sleep mode, power to the CPU and other peripheral components is disabled. Sleep mode disables all functions except the real-time clock, interrupt controller, power manager and general purpose I/O.

Microprocessor Operating modes

Operating modes are used when the microprocessor is idle for a specific amount of time. When a microprocessor receives an enabled interrupt, the processor will respond to the interrupt request and operate in its run or normal mode. Reducing the number of interrupts to the processor will increase the time the processor is in a power saving state. If the microprocessor does not have any instructions to execute, it will remain in a power saving mode forever. Inserting an external device to respond and handle system interrupts can reduce the operations required of the processor. By allowing the microprocessor to stay in its power down mode as long as possible, significant power savings can be realized.

Interfacing
Use of a low power programmable logic device to supplement the microprocessor will save system power and increase system battery life. The latest CPLD simultaneously deliver high performance and low power consumption. Fig. shows use of a reprogrammable CPLD to interface to incoming system interrupts. Using an external data acquisition device to off-load interrupt requests to the microprocessor will reduce overall system power.

System Interrupts
Variety of external devices may interrupt the processor which include both data acquisition and data processing requests. By separating data processing interrupts to the microprocessor, data acquisition interrupts can be serviced by the external CPLD. Using a CPLD to handle data acquisition interrupts will off-load interrupt requests to the microprocessor and save power. Peripheral devices or incoming data demanding a response to incoming data can be classified as data acquisition interrupt requests. Data acquisition interrupts include memory access interrupts; communication interfaces such as UART, general-purpose I/O interrupts, and LCD interface interrupts.

Operational flow
Once a valid external interrupt is recognized by the CPLD, it will determine if it contains the functionality to process the interrupt. Once the CPLD has processed the interrupt, it can assert an interrupt to the processor for any data processing requests needed. If the CPLD is unable to process the interrupt, the interrupt is passed to the processor. The CPLD also monitors the operating state of the processor.

Interrupt interface
Interrupt interface- The interrupt interface of the CPLD receives all external device interrupt requests previously recognized by the microprocessor. The interrupt interface determines if the CPLD is capable of processing the interrupt request. The CPLD handles data acquisition interrupts that request data receiving and storage capabilities. If the CPLD is unable to process the interrupt, the interrupt is passed to the microprocessor. Programmable logic provides flexibility to change the trigger mode, which includes a high or low level and falling or rising edge sensitivity. The CPLD interrupt control registers are similar to the registers in the microprocessor.

Interrupt controller
The CPLD interrupt controller emulates the functionality that exists in the system microprocessor. The interrupt controller interprets from which device the data acquisition interrupt was received and initiates the processing of the interrupt. The CPLD processes the data acquisition interrupt request that would have otherwise interrupted the microprocessor. The interrupt controller initiates the action to process the request. An example of this is an application where the CPLD is receiving data from a remote device. The device is requesting to write the data being sent into memory. The CPLD interrupt controller recognizes a valid interrupt and initiates the memory interface to interpret the data.

Microprocessor interrupt interface

Peripheral device interfaces- The CPLD provides the interface to system devices that are needed in processing interrupt requests. When an external device interrupts the CPLD to read or write data into a memory component, that particular memory interface is needed in the CPLD design. The types of interfaces needed can range from memories to LCD interfaces & communication interfaces. The CPLD, like any external device requesting services of the processor, has the capability to interrupt the microprocessor. The CPLD must be able to interrupt the microprocessor once a data acquisition operation is complete.

Microprocessor operating mode interface

Depending on the system microprocessor, the CPLD will be able to recognize the operation state of the processor. The CPLD can recognize the current operating state of the processor and determine whether to assert an interrupt to the processor to execute a waiting interrupt. For example, if a low priority interrupt is received by the CPLD and the processor does not need to transition from its low power state, the CPLD can create a register indicating pending interrupts. Then when the processor wakes, the interrupt pending register can be read by the microprocessor.

Power saving mode

The power requirements of the CPLD are minimal compared to the power savings realized by keeping the microprocessor in its low power modes for a longer amount of time. The latest CPLD in the market today offer a flexible combination of low power and high speed for any end application.

MPC603e Microprocessor
Low-power implementation of the family of reduced instruction set computing (RISC) microprocessors. It implements 32-bit portion of the PowerPC architecture. 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits. Instructions can execute out of program order for increased performance. It is a superscalar processor that can issue and retire as many as three instructions per clock cycle. Integrates five execution unitsan integer unit (IU), a floating-point unit(FPU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit(SRU). The MPC603e is fabricated using an advanced CMOS process technology and is fully compatible with TTL devices.

Signal Configuration

MPC603e Signals
Address arbitration Signals Bus request (BR) :Requests mastership of the bus Bus grant (BG): Indicates bus ownership if properly qualified Address bus busy (ABB): Indicates whether the address bus is busy Address Transfer Start Signals: Transfer start (TS) : Indicates that the master has begun a transaction to memory Extended transfer start (XATS) : Indicates that the master has begun a transaction to a direct-store address Address Transfer Signals Address bus (A[031]) : Indicates the real address of the bus transaction Address parity (AP[03]) : Gives odd parity for each address byte Address parity error (APE) : Indicates detection of address bus parity error

MPC603e Signals
Address Transfer Attribute Signals Transfer type (TT[04]) : Indicates the type of transfer in progress Transfer burst (TBST) : Indicates that a burst transfer is in progress Transfer size (TSIZ[02]) : Indicates the size in bytes of transfer in progress Transfer code (TCn) : Gives information about the transaction for external cache operations Cache inhibit (CI) : Indicates whether a transfer can be cached Write-through (WT) : Indicates whether a transaction is write-through Global (GBL) : Indicates that a transaction is global and that data coherence is required

Address Transfer Termination Signals Address acknowledgment(AACK): Indicates that the address portion of a transaction is complete Address retry (ARTRY) : Asserted when the address tenure must be retried.

Byte Lane Redirection

Memory System Design

One of the complicated portion of a minimal system is the interface to the processor data bus. RISC processors do not typically perform data (re)alignment, so the data from each external device must be placed on the proper data lane. In an attempt to use an 8-bit memory device to supply instructions or data to a 64-bit data bus, 8-bidirectional latching transceivers must be used to move the byte to the correct byte lane on the 64-bit bus. Thus the processor expects from one to eight bytes on each transfer. The memory controller must generate from one to eight memory cycles to the 8-bit memory by generating the addresses, latching the resulting data, & presenting it to the processor with the TA signal.

Memory System Design

For this minimal system, we will instead take the approach that all memory is 64-bits wide. By using 32-bit pipelined-burst SRAM for the main memory and 16-bit Flash EPROM for start-up code, only 6 components will be needed. The controlling logic will be simple and inexpensive, and SRAM will allow very fast memory access speeds. The use of SRAM for main memory has become more attractive as speed and size increases and price falls. The first step in designing the memory controller is to determine the types of controls that will be needed among the proposed memory devices Flash EPROMs, SRAM and general I/O.

Minimal System Memory Architecture

SRAM controls
A(n-0) : Memory address, used for burst transfers ADSC : Latches address for single-beat or burst transfers ADV : Increments address for burst transfers BWE (a-d) : Active-low byte-write enables; if not asserted, the cycle is a burst read. G : Active-low output enable; asserted for all read operations. SE1 : Active-low chip enable; asserted for all operations. The BWE signals corresponding to the size of the transfer must be asserted if the cycle is a write cycle; otherwise, G must be asserted to read in data. The remaining signal is ADV, which must be asserted for three clock cycles if a burst transfer is selected; otherwise, it remains high.

Pipelined Burst SRAM Memory Connections

ADSC * ADSP * SGW * SE2 *

MPC 603E

ADV * SB(A-D) *

CY7C1347G

G* TS * SE1 * LBO SE3 * SW *

ADSC *

ADSC * BAA * BWE(0-7) * ADV *

ADSP * SGW * SE2 *

CY7C1347G

Memory Controller

SB(A-D) * SOE * SCS * G* SE1 * LBO SE 3 * SW *

Memory Controller Signal Handling

AACK : Asserted on final memory transfer TA : Asserted per-beat on each memory transfer TEA : Asserted on each unsupported memory transfer BWE(0-7) : Asserted on writes on individual byte lane SCS : Asserted on all SRAM accesses SOE : Asserted on all SRAM read accesses ADSC : Asserted on all burst SRAM accesses before the first cycle BAA : Asserted on all burst SRAM accesses during cycles 2-4 FCS : Asserted on all Flash accesses FOE : Asserted on all Flash read accesses XCS(0-1) : Asserted on all I/O accesses XOE : Asserted on all I/O read accesses

Memory Controller Architecture

Start Detection Module

Upon receiving a TS, the memory controller must examine the TT(0-4) signals to determine the type of cycle that will be performed. Of the 32 possible permutations, only those found below are of interest:

TT Encoding

Simulation result

Start() module

When any transfer begins, the start() module must either assert the claim_l or doerr_l signal to cause the appropriate actions to conclude the transfer cycle. The start() module provides the global CLAIM_L signal, used by other modules to detect whether a cycle is inprogress, or the DOERR_L signal, used to terminate unclaimed cycles, and a write signal (WE_L) to determine that the cycle is a write cycle.

Simulation result

Byte Write Enable

The next group of signals to generate are the byte lane write enables BWE(0-7). These signals are generated by using the transfer size signals TSIZ(0-2) along with the lower address bus signals A(29-31) to determine which byte lanes should be active.

Bytedec
The bytedec() module examines the decoded write status (WE_L) but not CLAIM, so the byte lane enables are asserted for all write cycles regardless of the activity of the CLAIM signal. Burst transfers enable all byte lanes, while all other transfers enable only the byte lanes based upon the address and transfer size.

Simulation result

Chip Select Module

The chip-select module, generates the four chipselect signals and selects the proper time delay for accesses to memory .

Chip select
Following are the chip-select actions based upon the address. The timer values in Table below have a constant overhead of three subtracted from the expected timer values. This constant overhead is due to the start delay, the final TA assertion, and one clock needed to detect a zero count on the timer. So for best performance, the actual timer values are offset by (-3). Chip Select Encodings

Simulation result

Cycler State Machine

The cycler() state machine module controls the remainder of any transaction claimed by the memory controller. For optimal performance, one of four flows are selected. The flows are as follows: SRAM single beat transfer SRAM burst transfer Programmed-length transfer (I/O and Flash) Error transactions

Memory Controller Module

The final module is the memory controller itself, which simply interconnects the previous modules. The PowerPC processor has one standard interrupt signal (INT) that can be connected to an external interrupt source if needed. If extra interrupts are needed, the simplest manner is to merge all level-sensitive interrupts with a logic gate. A PowerPC design can be implemented with a small amount of hardware by following this example. The resulting system will exhibit fast memory access times.