PIC18 Architecture

Program Memory Modes

Four Modes:
Extended Microcontroller Microcontroller Mode Mode 0 Internal 0 Internal Internal Internal Boot Block 512 Boot Block 512 Boot Block Boot Block Internal Internal Internal Internal Program Program Program Program Program Space Flash Flash Flash Flash External External Program Program Memory Memory 2M Data Space 0 4K 2M 0 Internal Internal 4K Internal Internal 4K Microprocessor Mode 0 Microprocessor With Boot Block Mode Internal 0 Internal Boot Block 512 Boot Block

External External Program Program Memory Memory

Read as 0 Read as 0

External External Program Program Memory Memory 2M 0 Internal Internal 4K 2M 0

Internal Internal

Note: Check your device datasheet

2002 Microchip Technology Incorporated. All Rights Reserved. 618 ICD PIC18FXXX DFT Hands On Workshop 40

PIC18 Architecture
Accessing Program Memory
G

21-bit Divided into PCU:PCH:PCL

G G

PCL is readable/writeable PCU:PCH is readable/writeable via shadow registers only

PCLU PCLH

PCLATU PCLATH PCL Program Counter

PCL<0> is forced to 0
Program Memory

0 2 M

16-bit Wide
2002 Microchip Technology Incorporated. All Rights Reserved. 618 ICD PIC18FXXX DFT Hands On Workshop 41

PIC18 Architecture
Reading Program Memory

TBLRD Operation
TBLPTRU TBLPTRH TBLPTRL<7:1> <0> TBLPTRL<0>=0 => LSB TBLPTRL<0>=1 => MSB

TABLAT

tblrd*+

MSB

LSB

Program Memory
2002 Microchip Technology Incorporated. All Rights Reserved. 618 ICD PIC18FXXX DFT Hands On Workshop 42

PIC18 Architecture
Writing to Program Memory
Table Pointer movff movff tblwt*
See Appendix C for more information

TBLPTRU TBLPTRH TBLPTRL

LOW(DATA),TABLAT HIGH(DATA),TABLAT

tblwt*+

TABLAT
Holding Latch

LOW(DATA) HIGH(DATA) LOW(DATA)

HIGH BYTE (ODD ADDR)

LOW BYTE (EVEN ADDR)

Internal Program Memory

2002 Microchip Technology Incorporated. All Rights Reserved. 618 ICD PIC18FXXX DFT Hands On Workshop 43

Accessing Program Memory ( Cont.) (Cont.)

G

PIC18 Architecture

TBLPTR is used to address program memory

G

Divided in TBLPTRU:TRBLPTRH:TBLPTRL

G G

TBLRD is used to read a byte TBLWT is used to load write buffer

G G

EECON1 register controls actual write cycle Protected against run-away code

G G

Erase block size 32 or 64 bytes* 8 bytes written at a time

* Note: Check your device datasheet
618 ICD PIC18FXXX DFT Hands On Workshop 44

2002 Microchip Technology Incorporated. All Rights Reserved.

Table Pointer Operations

G

To enhance flexibility of table operations, the TBLPTR automatically increment and decrement during read/write operations PIC18 devices have 4 modify modes for TBLPTR
tblwt* tblwt*+ tblwt*tblwt+* tblrd* tblrd*+ tblrd*tblrd+* no change auto post increment auto post decrement auto pre increment

2002 Microchip Technology Incorporated. All Rights Reserved.

618 ICD

PIC18FXXX DFT Hands On Workshop

45