A Seminar Report On

3D ICs
Submitted in partial fulfillment Of requirement for Degree of Bachelor of Technology in Electronics and Communication Engineering

ACADEMIC SESSION 2011-12

Department Of Electronics and Communication Engineering Suresh Gyan Vihar University Jagatpura, Jaipur

Submitted to: Mr. Rashid Hussain Head of Department Elec. & Comm. Engg.

Submitted by: Anurag Sharma Section: D

CERTIFICATE
Certified that this is a bonafide record of the seminar report entitled 3D

INTEGRATED CIRCUITS is done by ANURAG SHARMA of the 8th semester, Electronics & Communication Engineering in the year 2012 in partial fulfillment of the requirements to the award of degree of Bachelor of Technology in Electronics & Communication Engineering of SURESH GYAN VIHAR UNIVERSITY,JAIPUR under my supervision and guidance, is hereby approved for submission.

Sandhya Sharma
Associate Professor (ECE)

ACKNOWLEDGEMENT
At the outset, we thank God almighty for making our endeavor a success. We also express our gratitude to Mr. Rashid Hussain, Head of the Department for providing us with adequate facilities, ways and means by which we were able to complete this seminar. It is my pleasure and privilege to acknowledge and express my deep sense of gratitude to my teacher and guide, Mrs. SANDHYA SHARMA (Associate Professor), Department of Electronics & Communication Engineering, Faculty of Engineering, Suresh Gyan vihar University, Jaipur, who inspired and initiated me to prepare this seminar despite his busy academic schedule. She has always been kind enough to spare his valuable time and thought in giving necessary guidance. Her reach and varied experience as an academician immensely helped me in understanding this topic clearly. I express my immense pleasure and thanks to all the teachers and staff of the Department Electronics & Communication Engineering, SGVU for their cooperation and support. Last but not the least, I thank all others, and especially our classmates and our family members who in one way or another helped me in the successful completion of this work.

Date: Place: Jaipur

Anurag Sharma M.Tech.(DD) 8th Sem. (E&C)

PREFACE
An Engineers education is not complete until he has obtained both theoretical as well as practical knowledge. This combination of knowledge makes him a complete and full-fledged engineer who can work for his as well as the whole mankinds development and prosperity. Theoretical knowledge is provided in university. In the classroom and can be obtained from books and other similar materials. It is the first and most important part of education without which there can be no practical knowledge. With all these group discussion and seminars also causes the value to make his personality more powerful.

Seminars are the important part of engineering curriculum. They help a student in getting acquainted part with the manner in which the knowledge is presented at the professional level. When a student switches from process of learning to practical implementation such as projects and seminars etc. are of great help to handle the abrupt changes. Seminars extend your learning process to a step beyond your classroom performance.

ABSTRACT
Despite generation upon generation of technology scaling, computer chips have remained essentially two-dimensional (2D). Improvements in the on-chip wire delay, and in the maximum number of inputs and outputs per chip have not been able to keep up with transistor performance growth, and it has become progressively harder to hide the discrepancy. In addition, the complexities of lithography beyond the 32 nm node threaten the traditional performance and cost scaling paradigms. In contrast with these conventional 2D circuits, 3D integrated circuits offer a new paradigm that builds multiple tiers of active devices stacked above each other. Recent advances in process technology have brought 3D technology to the point where it is feasible and practical, and it has raised widespread interest in the chip industry. The move to 3D allows numerous benefits over 2D, such as reduced interconnect lengths, improved computation per unit volume, and the possibility of integrating heterogeneous systems. However, the paradigm requires a significant change from contemporary design methodologies, since an optimal 3D chip design has very different characteristics from an optimal 2D chip design. The goal of this tutorial is to provide an overview of the technology, the corresponding design challenges, and existing solutions to overcome these challenges. 3D chip technologies come in a number of flavors that are expected to enable the extension of CMOS performance. Designing in 3D forces the industry to look at formerly-two-dimensional integration issues quite differently, and requires the re-fitting of multiple existing EDA capabilities. We begin with an overview of the motivation for 3D, process steps, and delve into the design issues in detail.

TABLE OF CONTENTS
Certificate Acknowledgement Contents
CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 1.2 2D Integrated Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3D Integrated Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

CHAPTER 2 MANUFACTURING TECHNOLOGIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 2.2 2.3 2.4 2.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Fabrication of first level circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Creating the crystalline template for the second layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3D compatibility of laser annealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Transistor fabrication on the second layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

CHAPTER 3 3D INTEGRATION. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.3 3.5 3.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3D Integration Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3D-SIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3D-WLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3D-SIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 True 3D IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Thin Wafer Handling/Bonding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Tecnology Comparison and Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3D Integration Perspectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

CHAPTER 4 ADVANTAGES, DISADVANTAGES AND CHALLENGES. . . . . . . . . . . . . 29 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 Advantages of 3D IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Cost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Heterogeneous Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Shorter Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1.6 4.1.7 4.1.8 4.2 4.2.1 4.2.2 4.2.3 4.3 4.3.1 4.3.2 4.3.3 4.4.4 4.4.5 4.4.6

Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Circuit Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Disadvantages of 3D IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Thermal Issues in 3D IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power Delivery in 3D IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Challenges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 System level exploration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3D floorplanning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Extraction and Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Design for test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 IC/package Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

CHAPTER 5 SUMMARY. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 42 REFERENCES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

LIST OF FIGURES
Figure1 The schematic of the first level of a 2D IC ...5 Figure2 The schematic of the bonding process to obtain the second active device layer...6 Figure3 The schematic of the lateral seeded crystallization process showing two patterned islands and their seeding holes.7 Figure 4. Structure of an exemplary 3D IC structure along with the 1D cross-section used for the numerical simulation8 Figure 5. Thermal profile for the 3D IC..9 Figure 6. Evolution of temperature at the upper and lower interface of the separating LTO layer for a 250 mJ/cm2 laser pulse.10 Figure 7. C-V Measurements (at 1 MHz) for circular capacitors below the spots that were laser annealed.12 Figure 8. TEM image of the 3D stack comprising the deposited LTO and a-Si layers a) before and b) after laser annealing at a dose of upto200 mJ/cm2.....13 Figure 9. Optical absorption contours for a 100 nm gate length transistor using a wide area laser beam with photon wavelength of 308 nm..16

Figure 10. Fully processed 3D IC showing the crystalline island for the second circuit level and the interconnects connecting the transistors at the two levels to each other..17 Figure 11. Id vs (Vgs-Vt) of a 100m4m p channel MOSFET18 Figure 12. Id vs (Vgs-Vt) of a 100m4m n channel MOSFET..19 Figure 13 3D IC...22