Introduction

The tremendous growth has been observed in the electronic device industry. The devices are becoming faster with much smaller sizing. The famous Moores Law, which states that the transistor count of integrated circuits doubles approximately every 18 months continues to explain these trends. The law is declared expired several times but still it is a valid argument. The one thing which keeps Moores law alive is technology scaling; smaller structures consume less power and operate faster. Furthermore, as more transistors are available, there is more opportunity to parallelize computations, thereby leading to another performance improvement. This report discusses about the structure of NANGATE library, its different parameters and their theoretical interpretation. This document also discusses library exchange format (lef). NANGATE Library is an open library which is very extensively used throughout the academia and research. This library is a statistical library and works on the method of look-up tables for various parameters which come into play during the simulations. These methods are most commonly used but lack certain amount of precision. This report tries to relate the different parameters and factors with each other and more importantly the timing closure phase of simulation. In this report, we try to bring together the theory of working of MOSMOSs with the theoretical concepts to the design and structure of library. NANGATE Library in its latest version contains more than 100 cells in various drive strengths. We shall first look into the basic structure and operation of MOS so as to understand various parameters upon which the cells are characterised. MOS Basics Metal Oxide Semiconductor Field Effect Transistor is one of the most common and most revolutionary semiconductor devices which have contributed greatly to the development of Digital Electronics. We shall the example of NMOS for the explanation for its basic operations.

When Vgs< Vt, there is no conduction whatsoever between the drain and source, the MOS is in switched off state.

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Source to Body potential is zero.

When Gate to source potential difference crosses the threshold voltage Vt, due to presence of a transversal electric field a channel of n type charge carriers is formed in the p substrate of the device. Since the channel formed is of opposite polarity to that of the substrate, this channel is called inversion layer. Upon formation of this inversion layer or conducting channel current I is observed which varies linearly with the applied voltage Vgs. The MOS operates like a voltage controlled resistor in this phase. The current through the channel is given by

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where is the charge carrier mobility, Cox is the oxidation layer capacitance, W and L is the width and length of the channel respectively.

Upon application of another voltage source between Drain and source due to formation of a lateral electric field the conduction channel near the drain starts to shrink and after a certain voltage the depletion layer is fully pinched off leading to only Isat

The pinch off current or Isat can be is now not dependent on Vds but only on Vgs MOS operation in different phases can be summarized in the following graph.

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What is Cell Library?

A cell library is a collection of different combinational and sequential elements, called cells that are used to realize larger chip designs. For example the NANGATE library has AND gates as a combinational element and D-flip-flops as sequential element. A cell library is typically used by compilers that take as input a higher-level description of a chip design and create a netlist description containing numerous instances of the available cells.

Process Corners
In semiconductor manufacturing, a process corner is an example of a design-ofexperiments (DoE) technique that refers to a variation of fabrication parameters used in applying an integrated circuit design to a semiconductor wafer. One naming convention for process corners is to use two-letter designators, where the first letter refers to the N-channel MOSMOS (NMOS) corner, and the second letter refers to the P channel (PMOS) corner. In this naming convention, three corners exist: typical, fast and slow. Fast and slow corners exhibit carrier mobility which is higher and lower than normal, respectively. For example, a corner designated as FS denotes fast NMOS and slow PMOSs. There are therefore five possible corners: typical-typical (TT), fast-fast (FF), slow-slow (SS), fast-slow (FS), and slow-fast (SF). The first three corners (TT, FF, and SS) are called even corners; because both types of devices are affected evenly, and generally do not adversely affect the logical correctness of the circuit. The resulting devices can function at slower or faster clock frequency. The last two corners (FS, SF) are called "skewed" corners, and are cause for concern. This is because one type of MOS will switch much faster than the other, and this form of imbalanced switching can cause one edge of the output to have much less slew than the other edge.

Library Name NangateOpenCellLibrary_fast NangateOpenCellLibrary_low_ temp NangateOpenCellLibrary_slow NangateOpenCellLibrary_typi cal NangateOpenCellLibrary_wor st_low

Corner Fast Fast Fast Fast Slow Slow Typical Typical Slow Slow

Supply Voltage 1.25 1.25 0.95 1.10 0.95

Temperature (deg. C.) 0 -40 125 25 -40

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For Fast corner since the VDD is maximum the speed of the cell increases also the low temperature leads to higher saturation current because velocity saturation occurs at a higher value. For Slow corner the VDD is small and also the current saturation occurs at relatively lower value thus it takes longer to (dis)charge the output load capacitance. Similarly other corners can also be explained based on the concept of velocity, current saturation their dependence on temperature and Supply voltage with the below few relations As the temperature goes up the mobility of the electrons in the channel starts to increase but after a particular temperature this velocity saturates to a particular value, higher the temperature faster the velocity saturates thus limiting the saturation current as a result. Thus if the temperature is higher the velocity and hence current saturation is achieved earlier leading to slower operating MOS.

If the supply voltage is more the time taken to (dis)charge the capacitance at the end of the network varies proportionately and thus greatly contributes to the speed of the MOS. Higher the VDD higher is the speed of the MOS.

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One more factor which contributes to the overall switching speed of the MOS is the Threshold Voltage. For faster operations Vt is kept low and for slower operations Vt is kept high. But here while describing the dependence of the parameters over each other and some external factors it is assumed that Vt is kept constant across various process corners. The cell characteristics namely timing and power varies across the process corners but still follow the same relations. Process corners specify the operating conditions for the cells in a bigger design.

Cell characterization
Cell characterization is the foundation on which the entire high-level RTL-toGDSII flow has been built. Without accurately modelled ASIC cells IC design would take longer, require more people and software licenses. High quality, accurate and robust ASIC cell libraries enable implementation and verification flows for designers of ASIC, without these libraries this is not possible. Characterization starts when the cell's physical layout has been completed, extraction performed and an extracted SPICE netlist is available. The characterization process starts with the global parameters definition under which the library will be used we can say it as the 'Safe Operating Area' of the library as a whole. One method of defining this is to determine the maximum transition time that the cell may drive too long a transition time creates higher dynamic currents. Defining maximum transition times in turn defines, for each timing arc, the maximum capacitance that the cell output port can drive. The next decision is whether to use active or passive loads, and active or passive sources. With active sources and active loads the cell characterization is much more realistic, and results in superior quality results. Cell characterized with correctly configured source and load circuits and the correct voltage, process and temperature values will act as an agent to get the functionality details of the device or an IC. We can get pin capacitances; state-dependent pin-to-pin timing arcs and their values (intrinsic, input-slew dependent, and output load dependent); inertial and transport delays for combinational cells; timing constraints for sequential cells; timing sensitivity with VDD voltage variation, etc. Each acquisition of data requires a separate vector set, and a separate set of simulations (one for each process, voltage, temperature (PVT) corner of interest). Each cell in the library is characterized by the following features. i. ii. Propagation delay Output transition

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iii. iv.

Power Consumption Capacitance (Input to Output)

These characteristics in themselves differ among various, process corners.

Timing and Delays

a. Effect of Slew Rate: The slew rate of an electronic circuit is defined as the maximum rate of change of the output voltage. Slew rate is usually expressed in units of V/s [3].

The slew rate can be measured using a function generator usually by applying square wave and using oscilloscope to measure slope at the output as shown in fig.

Effect of slew rate. Red is desired output and green is actual output

Smaller the slew at the input larger is the input transition time and larger is the delay. Whenever a slew is applied to a cell's input pin, there is corresponding output slew at its output pin. This output slew directly depends upon the load connected to its output. Larger is the load capacitance larger would be the slew degradation. So the slew rate at output is caused by the load capacitance. b. Propagation Delay and Output Transition Propagation delay is the time gap between change at the input and acceptable change at output.

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Output transition is the time taken by the signal to change from one level to another. For NANGATE library these levels are the 30% and 70% of the VDD Propagation delay depends upon input transition and output capacitance. If the input transition rate or slew is more than the time taken for this information to travel through the cell takes longer. Thus if a source takes longer to transition from low to high the change at the output will take longer to change. Also Propagation delay and Output transition indeed depend upon the output load capacitance. Larger the load capacitance, longer it takes to charge or discharge thus effecting the time in which the signal change at the input is felt at the output. The dependence of propagation delay over load capacitance can be modelled in the following way. The propagation delay of a CMOS inverter is simply proportional to the time constant of the RC equivalent circuit thus formed taking into consideration the output load capacitance and pull-down resistor in case of High to low transition and pull-up resistor in case of Low to High transition.

where Reqp and Reqn are the pull-up and pull-down resistors respectively. Thus propagation delay becomes

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where K and k are the constants. Thus it can be clearly seen that propagation delay depends directly upon the load capacitance and similarly the output transition also depends upon the load capacitance. If the supply voltage is increased the propagation delay is reduced because of the more Isat because of the increased mobility and thus rapid (dis)charging of the capacitances. Increase in the temperature has adverse effect on the Propagation Delay, as explained earlier increase in the temperature leads to rapid velocity saturation of charge carriers thus limiting the Isat to a lower value. Full Cycle Delay is simply the sum of the propagation delay in transition from High to Low and Low to High transitions. Thus the dependence of propagation delay on various parameters including VDD, temperature is directly reflected into the Full Cycle Delay.

Power Dissipation
a. Dynamic Power Dissipation

Dynamic Power is dissipated by the switching activity of the cell. The energy dissipated during one transition can be written as

This expression can be derived by observing that during low to high transition Cl is loaded with a charge of value . For providing this charge requires the following energy

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Thus if the gate switches at the rate of f times per second the total power consumed dynamically is

Since gate is not switched in every cycle dynamic power becomes

where

is the switching factor.

Thus it can be clearly seen that the dynamic power dissipation depends directly on the Output load capacitance. Also if the VDD is kept higher the energy consumption increases, but keeping it low effects the switching speed of the MOS due to lower channel current. Thus effectively it is a trade-off between power consumption and speed of the cell in consideration.

b. Total Power Consumption Total power consumption is the sum of the power dissipated as Dynamic power and Static power. Static Power can be modelled as

Thus total power can be written as

Dynamic power plays a very dominant role in the total power consumption and it usually contributes to the 90% of the power dissipation in a cell. Also for both Dynamic and Total Power Consumption, if the input transition time is more, more power is consumed since it takes longer for the input to change

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the state from one accepted level to another thus taking up more power. If the transition occurs more rapidly, power consumed drops because transition takes less time.

Capacitance Table
Capacitance tables are the statistical LUTs containing the values of capacitance such as diffusion capacitance, gate capacitance etc. NANGATE library for every cell contains capacitance tables based on NLD modelling, depicting gate capacitance Cg for every input for fall and rise conditions separately. The format of the capacitance table is shown below

OR3_X1 Gate Capacitance Table

As shown, for each pin they have defined its direction and capacitance. Looking to the values, question may arise that

Why the capacitances are different at two inputs?

As shown in the table the capacitance for the input A1 is lower than that at pin A2. This is because if we draw equivalent capacitance at the pin A1 or A2 then we will have to write miller capacitance of capacitance from gate to drain of both the transistors and it is equal to C=Cgd(1+A), where A is gain from gate to drain. Now transistor M_i_2 (to which pin A1 is connected) acts as NMOS with the source degeneration (due to transistor M_i_3 connected to its source). Whereas transistor M_i_3 (to which pin A2 is connected) acts as NMOS with common source. So gain of M_i_3 will be higher than gain of M_i_2. So miller capacitance to the pin A2 will be higher than the capacitance at pin A1. Also other capacitances will be same because transistor sizes to which these pins are connected are same. That is why total capacitance at pin A2 is higher than that of A1.

Library Exchange Format (LEF)

A LEF file is an ASCII data format, which contains library information for a class of designs. Library data includes layer, via, placement site type, and macro cell

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definitions [4]. All of library information can be specified in a single LEF file; however this creates a large file that can be complex and hard to manage. Instead, we can divide the information into two files, a technology LEF file and a cell library LEF file. A technology LEF file contains all of the LEF technology information for a design, such as placement and routing design rules, and process information for layers. A technology LEF file can include any of the following LEF statements:
[VERSION statement], [BUSBITCHARS statement], [DIVIDERCHAR statement], [UNITS statement], [MANUFACTURINGGRID statement], [USEMINSPACING statement], [CLEARANCEMEASURE statement ], [PROPERTYDEFINITIONS statement], [LAYER (Nonrouting) statement| LAYER (Routing) statement], [MAXVIASTACK statement], [VIA statement], [VIARULE statement], [VIARULE GENERATE statement], [NONDEFAULTRULE statement], [SITE statement], [BEGINEXT statement], [END LIBRARY].

Whereas a cell library LEF file contains the macro and standard cell information for a design. It contains cell descriptions, cell dimensions, layout of pins and blockages, capacitances. A library LEF file can include any of the following statements:
[VERSION statement], [BUSBITCHARS statement], [DIVIDERCHAR statement], [VIA statement], [SITE statement], [MACRO statement], [PIN statement], [OBS statement ], [BEGINEXT statement], [END LIBRARY].

We have separate as well as combined LEF file available in NANGATE library.

View of LEF File

As described it contains metal layer and via information. Given below is an example how metal layer information is provided in the file:
LAYER metal1 TYPE ROUTING ; SPACING 0.065 ; WIDTH 0.07 ; PITCH 0.14 ; DIRECTION HORIZONTAL ; OFFSET 0.095 0.07 ; RESISTANCE RPERSQ 0.38 ; THICKNESS 0.13 ; HEIGHT 0.37 ; CAPACITANCE CPERSQDIST 7.7161e-05 ; EDGECAPACITANCE 2.7365e-05 ; END metal1 LAYER via1 TYPE CUT ; SPACING 0.08 ; WIDTH 0.07 ;

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RESISTANCE 5 ; END via1

So, it contains dimension information required during back end. Information for all the cells available in library is also provided in .LEF file. I am giving an example of how AND2_X1 cell is defined in the lef file. I have shown only two pin (A1 and A2) info for example. In reality It has information for ZN, VDD and VSS pins also.
MACRO AND2_X1 CLASS core ; FOREIGN AND2_X1 0.0 0.0 ; ORIGIN 0 0 ; SYMMETRY X Y ; SITE FreePDK45_38x28_10R_NP_162NW_34O ; SIZE 0.76 BY 1.4 ; PIN A1 DIRECTION INPUT ; ANTENNAPARTIALMETALAREA 0.021875 LAYER metal1 ; ANTENNAPARTIALMETALSIDEAREA 0.078 LAYER metal1 ; ANTENNAGATEAREA 0.02625 ; PORT LAYER metal1 ; POLYGON 0.06 0.525 0.185 0.525 0.185 0.7 0.06 0.7 ; END END A1 PIN A2 DIRECTION INPUT ; ANTENNAPARTIALMETALAREA 0.02275 LAYER metal1 ; ANTENNAPARTIALMETALSIDEAREA 0.0793 LAYER metal1 ; ANTENNAGATEAREA 0.02625 ; PORT LAYER metal1 ; POLYGON 0.25 0.525 0.38 0.525 0.38 0.7 0.25 0.7; END END A2

...

Frontend Subdirectory
Front end subdirectory of the library contains various timing delay model files which are used to model the delays in the simulations. There are two broad classifications of the delay models based on the driver source. a. b. Voltage source Current Source

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Voltage Source Based Model 1. Non Linear Delay Model This model is relatively old and was introduced for technology larger than 90nm. It does not take into account to large extent the contribution of interconnect delays. It also does not account for phenomenon like IR drop which has become quite important in the current technology of 90nm and smaller. It differs by more than 7% from the SPICE delay models. Since this is statistical model, delay values at intermittent slew and load capacitance values cannot be determined.

Thus these shortcomings gave way for Current Source Based timing models. Current Source Based Model 1. Composite Current Source This model was introduced by Synopsis and its support was provided by Si2. This model is current source based model. In this model the input and output waveforms are modelled so that delay values at intermittent values of slew and load capacitance can also be found out by interpolation. This model was developed for technology 90nm and below and it comprehensively takes into account the delay and parasitic elements introduced by interconnect which play very important role in todays technology. It also accounts for IR drop along the power rails. Its accuracy lies well within range of 97% of the SPICE delay models.

2. Equivalent Current Source Model This is an equivalent current source based model developed by Cadence and endorsed by Magma.