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[Label]

<Opcode>

<operand spec>

[,<operand spec>..]

[..] optional part <operand spec> <symbolic name> [+<displacement>][(<index register>)]

Examples :
AREA AREA+5 AREA(4) AREA+5(4)

First operand is register and AREG,BREG,CREG , DREG Second operand is memory word (symbolic name and optional displacement)

Instruction opcode Assembly mnemonic 00 01 02 03 04 05 06 07 08 09 10 STOP ADD SUB MULT MOVER MOVEM COMP BC DIV READ PRINT

Remarks Stop execution

Reg mem move Mem Reg move Sets condition code Branch on condition First operand not used

BC Instruction Format
BC <Cond. Code Spec. > <Mem Add>

Codes 1 2 3 4 5 6

Number LT LE EQ GT GE ANY

zxcz xczx zxcz zxcz zxcz zxcz xc c xc xc xc xc opcode Reg Opnd Mem.Opnd

AGAIN

N RESULT ONE TERM

START READ MOVER MOVEM MULT MOVER ADD MOVEM COMP BC MOVEM PRINT STOP DS DS DC DS END

101 N BREG, ONE BREG,TERM BREG,TERM CREG, TERM CREG,ONE CREG,TERM CREG,N LE, AGAIN BREG, RESULT RESULT
1 1 1 1

101) 102) 103) 104) 105) 106) 107) 108) 109) 110) 111) 112) 113) 114) 115) 116)

09 04 05 03 04 01 05 06 07 05 10 00

0 113 2 115 2 116 2 116 3 116 3 115 3 116 3 113 2 104 2 114 0 114 0 000

00 0 001

Imperative Statements Declaration Statements Assembler Directives

ADDAREG,FIVE FIVEDC 5 OR ADD AREG, = 5

MNEMONI OPCODE C ADD SUB 01

LENGTH 1

02 1 Mnemonic table Synthesis phase


TARGET PROGRAM

SOURCE PROGRAM

Analysis phase

Symbol AGAIN

Address 104

113
Symbol table

1. Isolate the label, mnemonic opcode and operand fields of a statement 2. If a label is present, enter the pair (symbol,<LC contents>) in a new entry of symbol table. 3. Check validity of the mnemonic opcode through a look-up in the Mnemonics table. 4. Perform LC processing

1. Obtain the machine opcode corresponding to the mnemoic from the mnemonic table 2. Obtain the address of a memory oprand from the symbol table 3. Synthesis a machine instruction or machine form of a constant, as the case may be

1. Two Pass Instruction 2. Single Pass Instruction

Pass I 1. Separate symbol, mnemonic opcode and operand fields, 2. Build the symbol table 3. Perform LC processing 4. Construct intermediate representation Pass II Synthesis the target program

START STOP END ORIGIN EQU LTORG

Mnemonic field (statement class, code) STATEMENT CLASS IS, DL and AD Declaration Statements Assembler Directives DC 01 START 01 DS 02 END 02 ORIGIN 03 EQU 04 LTORG 05

Operand class (operand class, code) START 200 READ A LOOP MOVER AREG,A . . SUB AREG, =1 BC GT,LOOP STOP A DS 1 LTORG

Variant I

(AD,01) (IS, 09) (IS,04) (1) (S,01)

(C,200) (S,01)

(IS,02) (1) (L,01) (IS,07) (4) (S,02) (IS,00) (DL,02) (C,1) (DL,05) .

Operand class (operand class, code) START 200 READ A LOOP MOVER AREG,A . . SUB AREG, =1 BC GT,LOOP STOP A DS 1 LTORG

Variant II

(AD,01) (C,200) (IS, 09) A (IS,04) (1) AREG,A

(IS,02) AREG, (L,01) (IS,07) GT,LOOP (IS,00) (DL,02) (C,1) (DL,05) .

Comparison of two variants


Variant I Work in PASS I is more as operand field is completely processed IC In PASS I takes more memory Variant II Processing in PASS I is simple Reduces the work of PASS I Memory requirement is balanced

ORIGIN <address spec>


ORIGIN LOOP+2

<symbol> EQU <address spec> BACK EQU LOOP LTORG

1 2 3 4 5 6 7 12 13

LOOP

BC

14 15 16 17 18 19 20 21 22 23 24 25

NEXT LAST

A BACK B

START 200 MOVER AREG,=5 200) MOVEM AREG, A 201) MOVER AREG, A 202) MOVER CREG, B 203) ADD CREG,=1 .. ANY,NEXT 210) LTORG = 5 211) = 1 212) .. SUB AREG,=1 214) BC LT,BACK 215) STOP 216) ORIGIN LOOP+2 MULT CREG, B 204) ORIGIN LAST+1 DS 1 217) EQU LOOP DS 1 218) END =1 219)

04 1 211 05 1 217 04 1 217 05 3 218 204) 07 6 214 00 0 005 00 0 001 02 1 219 07 1 202 00 0 000 03 3 218

01 3 212

00 0 001

Data Structure of Pass I


OPTAB Mnemonic opcode MOVER Class IS Mnemonic info (04,1) Symbol LOOP NEXT LAST A BACK LITTAB Sl No 1 2 3 Literal =5 =1 =1 Address B SYMTAB Address Length 202 214 216 217 202 218 1 1 1 1 1 1

DS
START

DL
AD

R#7
R#11

Literal #1 #3 -------

POOLTAB

1. loc_cntr := 0; (default vale) pooltab_ptr := 1 ; POOLTAB[1] := 1; littab_ptr := 1;

2. While next statement is not an END statement (a) If label is present then this_label := symbol in the label field; Enter (this_label,loc_cntr) in SYMTAB

(b) If an LTORG statement then (i) Process literal LITTAB [POOLTAB[pooltab_ptr]] LITTAB[littab_ptr-1] to allocate memory and put the address in the address field. Update loc_cntr accordingly. (ii) pooltab_ptr := pooltab_ptr + 1; (iii) POOLTAB[pooltab_ptr] := littab_ptr; ( c) if a START or ORIGIN statement then loc_cntr := value specified in the operand field; ( d) if an EQU statement then (i) this_addr := value of <address spec> (ii) Correct the symbol entry for this label to (this_label, this_addr)

(e) If a declaration statement then (i) code := code of the declaration statement (ii) size:=size of memory area required by DC/DS (iii) loc_cntr:= loc_cntr + size; (iv) Generate IC (DL,code)..

(f) If an imperative statement then (i) code := machine code from OPTAB; (ii) loc_cntr : loc_cntr + instruction length from OPTAB (iii) If Operand is a literal then this_literal := literal in operand field; LITTAB[littab_ptr]:=this_literal; littab_ptr := littab_ptr + 1; else (ie operand is symbol) this_entry := SYMTAB entry number of operand; Generate IC (IS.code) (S,this_entry);

3. Processing of END statement (a) Perform step 2(b). (b) Generate IC (AD,02). (C) Go to Pass II.

DC 5, 3, -7 By series of (DL,01) units can be put in the LC.


Processing of LTORG: two methods 1. Tables are created in Pass I and code is created in Pass II 2. Code is created in Pass I only

Method II
START 200 MOVER AREG,=5 MOVEM AREG,A MOVER AREG,A . BC ANY, NEXT LTORG (AD,01) (C,200) (IS,04) (1) (L,01) (IS,05) (1) (S,01) (IS,04) (1) (S,01) (IS,07) (6) (DL,01) (C,5)

LOOP (S,04)

Pass II (Algorithm)
1.code_area_addressm := address of code area; pooltab_ptr := 1; loc_cntr := 0; 2. While next statement is not END statement (a) Clear machine_code_buffer; (b) if an LTORG statement (i) Process literals in LITTAB[POOLTAB[pooltab_ptr]]LITTAB[ POOLTAB[pooltab_ptr+1]-1] assemble the literal in machine_codebuffer.

Pass II (Algorithm)
(ii) size:=size of memory area required for literals; (iii) pooltab_ptr := pooltab_prt + 1; (c) If a START or ORIGIN statement then (i)loc_cntr:= value specified in operand field (ii) size := 0; (d) If a declaration statement (i) if a DC statement then Assemble the constant in machine_code_buffer. (ii) size:= size of memory area required by DC/DS

Pass II (Algorithm)
(e) If an imperative statement (i) get operand address from SYMTAB or LITTAB (ii) Assemble instruction in machine_code_buffer. (iii) size := size of insruction. (f) If size 0 then (i) move contents of machine_code_buffer to the address code_area_address+loc_cntr; (ii) loc_cntr:=loc_cntr+size;

Pass II (Algorithm)
3. (Processing of END statement) (a) Perform steps 2(b) and 2(f) (b) Write code_area into output file.

Error reporting
In Pass I In Pass II 1.Source Program need not be 1. Source program need to be preserved till PASS II preserved 2.Conserves memory and avoids some amount of duplicate processing 3.Can report only certain errors such as syntax errors 2. All errors against the erroneous statement can be reported 3.Error report as well as target code can be printed

4. Difficult to locate the target 4. Debugging is easy code corresponding to source program 5. Debugging Difficult

Organizational Issues
SYMTAB

OPTAB

LITTAB
Target Program

Source program

Pass I Source program

Pass II Program Listing

SYMTAB always in memory LITTAB partially in memory OPTAB in memory during pass I

Intermediate code

Loaders and Linkers


Schematic of program execution:
Translator Linker Loader Data Binary Program

Results Source Program Object modules Binary programs

Data Flow
Control Flow

Various address
1. Translation time address 2. Linked address 3. Load time address

Relocation
rf = lorg torg 1 tsym = torg + dsym 2 lsym = lorg + dsym 3 lsym = torg + rf+dsym = tsym + rf

EXTRN and ENTRY statements


START 500 ENRTY TOTAL EXTRN MAX,ALPHA READ A LOOP 501) 500) 09 0 540

. . MOVER AREG, ALPHA BC ANY,MAX . BC LT,LOOP STOP A DS 1 TOTAL DS 1 END

518) 04 1 000 519) 06 6 000 538) 06 1 501 539) 00 0 000 540) 541)

START 200 ENTRY ALPHA ----------ALPHA DS 25 231) 00 0 025 END

Object module
1. Header translated origin, size,exec start address 2. Program m/c lan program 3. Relocation table: translated address of an address sensitive instruction. 4. Linking table: symbol symbolic name Type PD/EXT public def./ext. ref Translated address memory word , first word allocated to symbol / required to contain the address of a symbole

START 500 ENRTY TOTAL EXTRN MAX,ALPHA READ A LOOP

Example
500) 09 0 540 501)

. . MOVER AREG, ALPHA BC ANY,MAX . BC LT,LOOP STOP A DS 1 TOTAL DS 1 END

518) 04 1 000 519) 06 6 000 538) 06 1 501 539) 00 0 000 540) 541)

Example
1. 2. 3. 4. Header torg 500, size = 42, esa = 500 Program as shown in the fig. Relocation table 500 538 Linking table
ALPHA MAX TOTAL EXT EXT PD 518 519 540

RELOCATION ALGORITHM
1. program_linked_origin := <link origin> from linker command; 2. For each object module
a) t_origin := tran. Org. of the object module OM_size := size of the object module; b) relocation_factor := program_linked_origin t_origin c) Read the m/c program in work area d) Read RELOCTAB of the object module

(e) For each entry in RELOCTAB (i) translated_addr := address in the RELOCTAB entry; (ii) address_in_work_area := address of work_area + translated_address t_origin; (iii) Add relocation_factor to the operand address in the word with the address address_in_work_area. (f) program_linked_origin := program_linked_origin + OM_size.

Example
Let l_org = 900 t_org = 500 rf = 400 address of work area = 300 For the first entry in IRR address_in_work_area = 300+500-500=300 (address of READ A) address of operand is 400+540 = 940 For the second entry address_in_work_area = 300+538-500= 338 ( operand is relocated by adding 400)