Professional Documents
Culture Documents
of Large-Scale Dithered
Analog-to-Digital Conversion
in the HP 89400 Series VSAs
The analog-to-digital conversion (ADC) subsystem of The HP 89400 Series analyzers’ ADC is the first known
the HP 89400 Series vector signal analyzers (VSAs) is practical application of large-scale dithering as an
a key enabling technology in the development of a external enhancement to an embedded ADC
wide information bandwidth, wide dynamic range component. The effect of this dither implementation is
vector signal analyzer. As the critical block which to achieve superior low-order linearity at high
bridges the analog and digital worlds, the ADC conversion rates.
dominates several important instrument
specifications such as the widest information
Bits Versus Dynamic Range
bandwidth and the achievable noise and distortion
dynamic range.
The number of bits of an ADC is often considered an
Although commercial ADC converters are increasingly accurate indication of its dynamic range. In fact, this
used in signal processing at RF information bandwidths, measure can be quite misleading. As ADCs trend toward
the linearity of these converters has not been sufficient a combination of more bits and higher speeds, static
for precision electronic test instrumentation. In measures of converter performance such as integral
contrast, the large-scale dithered ADC subsystem of the and differential nonlinearity and number of bits are
HP 89400 Series VSAs provides unprecedented linearity giving way to dynamic measures such as signal-to-noise
performance in high-speed converters with sample rates ratio (SNR) and distortion dynamic range. These
to 25.6 MSPS, and achieves the necessary dynamic dynamic measures often are far more useful in
range suitable for wideband VSA instrumentation evaluating converter performance, particularly in
applications. applications where converters in conjunction with
digital signal processing are replacing traditional analog
Previous HP analyzers have used small-scale dithering implementations. To help users better interpret the
as an integral part of their ADC architectures. dynamic performance requirements for their
Small-scale dithering reduces the high-order spurious applications the specifications of the HP 89400 Series
mechanisms associated with analog-to-digital VSAs are written in terms of dynamic measures such as
converters. Moreover, dithering a converter in SNR and distortion dynamic range instead of bits.
conjunction with subsequent digital filtering makes it
possible to reliably extract signals far below the least The 6 dB per bit rule-of-thumb is often invoked in
significant bit (LSB) step size of the converter. estimating the dynamic range potential of an ADC. But
for many converter architectures this may be an
Large-scale dithering enjoys the same benefits of oversimplification. An obvious case in point are
small-scale dithering. In addition, large-scale dithering sigma-delta converters, which may only use a single bit
not only reduces high-order distortion products but also and, by oversampling techniques, achieve up to 18
seeks to achieve a significant improvement in the effective bits of signal-to-noise dynamic range.
low-order distortion performance as well. This comes at Moreover, converters with large number of bits at the
the cost of some signal overhead associated with the output may, in fact, suffer from inherent noise
level of dither signal applied. limitations which constrain their performance to fewer
effective bits.
2
This can be illustrated as follows: Consider an ideal The general equation for computing the expected value
ADC with staircase transfer function whose quantized for a transfer function with one random variable is
ideal error transfer function is shown in Figure 4. given by:
∞
∫
Output
error G(z) = p(z) e (z) dz
–∞
∞
G(x) = ∫ p(z) e (x + z) dz
–∞
Input
Probability
+q/2
-q/2
1/d
Input
-d/2 d/2
Amplitude Figure 6 — Condition integration yields zero
Figure 5 — PDF of LSB dither
For a dither amplitude of 1 LSB the integration result is
zero, yielding an ADC transfer function that is
completely linear. The high-order distortion terms
associated with the polynomial expansion of the
5
Operation of the HP 89400 Series The digital path of the PRN generator is routed to a
VSAs’ ADC high-speed, 13-bit digital subtractor immediately
following the analog-to-digital conversion. The
subtractor is composed of pipelined adders with
Figure 8 depicts the block diagram of the large-scale look-ahead carry to subtract corresponding values of
dithered ADC converter. The dither signal itself consists dither on a per-sample basis from the converted digital
of random noise which must be uncorrelated to the representation of the input signal plus dither. The
input signal. A random 12-bit sequence is generated by a appropriate number of delays in the digital path of the
pseudo-random number generator with a period of converter assures that correctly corresponding values
2^39-1 samples. At a sample rate of 25.6 MSPS this of dither are subtracted, thereby removing the dither
yields a period of about six hours, assuring that the and leaving only the digital representation of the
periodicity of the dither is well below any measurement original input signal.
frequency of interest. Adjacent dither samples are
designed to be highly uncorrelated to assure the power Small-scale dithered converters can often perform the
spectral density of the random noise is flat with subtraction step with a minimal noise penalty because
frequency. the dither signal levels are on the order of a few LSBs.
In fact, some small-scale dithered converters ignore the
The sampled random noise sequence follows two signal subtraction step entirely because any residual noise left
paths in the block diagram. On the analog input side of by the subtraction errors are often negligible. For
the block diagram the sequence is converted to an large-scale dither, because the large signal levels
analog random noise representation of the employed may exceed the magnitude of the input signal
pseudo-random number sequence by the high-speed itself, the precision of the subtraction step becomes
dither DAC which runs at the sample rate of the critical.
converter. The analog representation of the dither
signal is then combined with the analog input signal at a Accurate subtraction is achieved by using a digital
wideband summing junction comprised of very correlator as part of a low-frequency feedback loop to
wideband, low-distortion operational amplifers. The generate a feedback error signal. The feedback error
combined signal consisting of the input signal plus signal generated from the correlator/accumulator is
added random noise dither is applied to the converted into an analog error signal by the automatic
track-and-hold input of the analog-to-digital conversion gain control DAC. The analog error signal servos the
block. amplitude of the dither signal at the output of the dither
DAC to assure exact subtraction. This summarizes the
operation of the large-scale dithered ADC.