The Dynamic Range Benefits
of Large-Scale Dithered
Analog-to-Digital Conversion
in the HP 89400 Series VSAs
Product Note 89400-7
The analog-to-digital conversion (ADC) subsystem of
the HP 89400 Series vector signal analyzers (VSAs) is
a key enabling technology in the development of a
wide information bandwidth, wide dynamic range
vector signal analyzer. As the critical block which
bridges the analog and digital worlds, the ADC
dominates several important instrument
specifications such as the widest information
bandwidth and the achievable noise and distortion
dynamic range.
Although commercial ADC converters are increasingly
used in signal processing at RF information bandwidths,
the linearity of these converters has not been sufficient
for precision electronic test instrumentation. In
contrast, the large-scale dithered ADC subsystem of the
HP 89400 Series VSAs provides unprecedented linearity
performance in high-speed converters with sample rates
to 25.6 MSPS, and achieves the necessary dynamic
range suitable for wideband VSA instrumentation
applications.
Previous HP analyzers have used small-scale dithering
as an integral part of their ADC architectures.
Small-scale dithering reduces the high-order spurious
mechanisms associated with analog-to-digital
converters. Moreover, dithering a converter in
conjunction with subsequent digital filtering makes it
possible to reliably extract signals far below the least
significant bit (LSB) step size of the converter.
Large-scale dithering enjoys the same benefits of
small-scale dithering. In addition, large-scale dithering
not only reduces high-order distortion products but also
seeks to achieve a significant improvement in the
low-order distortion performance as well. This comes at
the cost of some signal overhead associated with the
level of dither signal applied.
The HP 89400 Series analyzers’ ADC is the first known
practical application of large-scale dithering as an
external enhancement to an embedded ADC
component. The effect of this dither implementation is
to achieve superior low-order linearity at high
conversion rates.
Bits Versus Dynamic Range
The number of bits of an ADC is often considered an
accurate indication of its dynamic range. In fact, this
measure can be quite misleading. As ADCs trend toward
a combination of more bits and higher speeds, static
measures of converter performance such as integral
and differential nonlinearity and number of bits are
giving way to dynamic measures such as signal-to-noise
ratio (SNR) and distortion dynamic range. These
dynamic measures often are far more useful in
evaluating converter performance, particularly in
applications where converters in conjunction with
digital signal processing are replacing traditional analog
implementations. To help users better interpret the
dynamic performance requirements for their
applications the specifications of the HP 89400 Series
VSAs are written in terms of dynamic measures such as
SNR and distortion dynamic range instead of bits.
The 6 dB per bit rule-of-thumb is often invoked in
estimating the dynamic range potential of an ADC. But
for many converter architectures this may be an
oversimplification. An obvious case in point are
sigma-delta converters, which may only use a single bit
and, by oversampling techniques, achieve up to 18
effective bits of signal-to-noise dynamic range.
Moreover, converters with large number of bits at the
output may, in fact, suffer from inherent noise
limitations which constrain their performance to fewer
effective bits.
 2

A related misconception is that a converter’s ability to

extract signals is limited by its resolution or LSB step
size. For ADCs with dithered architectures followed by
digital filtering, the resolution is usually much better
than the converter step size. The dithering which
randomizes the quantization of the converter works in
conjunction with the inherent time averaging of digital
filters to allow for the extraction of signals far below
the step size of the converter. For the smaller effective
resolution bandwidths of the digital filters, the resulting
greater processing gains provide higher resolution,
limited only by the accuracy of the digital filters.

This phenomenon is analogous to the reduction in noise

power which occurs for narrower resolution
bandwidths of analog IF filters. The HP 89400 Series
VSAs’ digital filters provide up to 23 bits of resolution,
corresponding to the narrowest resolution bandwidth of
1 millihertz. This means the dithered ADC and digital
filters can resolve signals to –140 dBc. On the lowest
input range setting of –30 dBm this corresponds to
–170 dBm sensitivity.

Similar arguments can be made for evaluating the

distortion dynamic range of a converter merely on the
basis of the number of bits at the converter output. In
many cases the actual linearity is far worse than the
6 dB per bit rule would imply. By contrast, in dithered
architectures the linearity typically exceeds the figure
suggested by the number of bits.
High- and Low-Order Distortion
Another distinction must be made between high-order
and low-order distortion mechanisms, whose
characterizations can be a source of confusion in
dithered converters. Most ADCs suffer from a hardfloor
distortion limitation associated with the high-order
distortion products generated by the staircase transfer
function. A characteristic of this hardfloor is that as the
fundamental input signal amplitude is lowered, the
amplitudes of the distortion products remain relatively
fixed. Most ADC distortion specifications are written in
terms of dB spurious because their distortion
performance is dominated by higher order spurious
mechanisms. These spurious products remain fixed in
amplitude as the fundamental amplitude is lowered,
thereby reducing the dynamic range relative to the
fundamental amplitude measured in dBc.
This is in sharp contrast to both analog components and
dithered converters, whose distortion is usually
Figure 1 — Behavior of various orders of low order distortion
dominated by low-order mechanisms. Dithered con-
verters exhibit low-order or “soft” distortion behavior,
because the reduction of high-order mechanisms
significantly lowers the hardfloor and allows the low
distortion mechanisms to dominate. As the signal
amplitude is lowered (to lower the distortion) the
product amplitudes also decrease relative to full-
scale. The amplitude at which the products no longer
continue to drop, and the dynamic range plateaus, is
called the hard-distortion floor. This floor is often
measured in terms of dBFS relative to the full-scale of
the converter, and may often be referred to as the
linearity of the converter. This is depicted in Figure 1.
Undithered, the HP 89410A hardfloor would be circa
–68 dBFS. Dithering reduces the actual hardfloor to
approximately –90 to –100 dBFS.
Low-order distortion products are usually measured in
terms of dBc below the fundamental signal amplitude.
Because the distortion performance of the HP 89410A
converter is dominated by low-order mechanisms, the
distortion is specified in terms of dBc, at nominal
full-scale. Distortion order originally derives from the
order of the term in the polynomial expansion of the

transfer function. It also dictates the amplitude and
frequency behavior of a particular distortion product. A
dBc specification indicates distortion performance
relative to the carrier for a given amplitude. The order
of amplitude behavior relates to the traditional rule of
determining the distortion amplitude relative to the
fundamental. This is described in terms of 2 dB of
distortion amplitude reduction per dB of fundamental
amplitude reduction for 2nd order, 3 dB/dB for 3rd
order, etc. First order distortion changes by 1 dB per dB
of reduction and therefore the dBc specification
remains constant with changing fundamental
amplitude. Because the dBc specification is dependent
on the absolute level of the fundamental, many
amplifiers and mixers are specified in terms of intercept
point. This is the theoretical signal amplitude at which
the fundamental and particular distortion term are
equal.
Figure 1 illustrates the difference between hard and soft
distortion in terms of dBc, and shows the behavior of
several orders of soft (low-order) distortion.
This summarizes the two main dynamic range benefits
of dithering. Dithering can substantially lower the
hard-distortion floor exhibited by undithered con-
verters. Secondly, dithered converters in conjunction
with digital filtering make possible the extraction of
signals far below the converter LSB step size. In
addition, large-scale dithering is employed in the
HP 89400 Series VSAs’ ADC to significantly improve the
low-order distortion as well. The following sections
explain how dithering works and describe the
performance and operation of the large-scale dithered
converter.
What is Dithering?
Dithering is a method for randomizing the quantization
errors of an ADC by adding a stimulus which is
uncorrelated to the desired signal at the analog input of
the converter. Figure 2 is a basic block diagram of an
externally dithered converter in which the dither signal
is subtracted following the ADC conversion.
3
Analog
Summing
Junction Subtractor
Analog Digital
Input Σ ADC - Output
Dither Generator
DAC PRN
Figure 2 — Block diagram of externally dithered converter
There are various types of dithering which, among other
aspects, can be differentiated by the characteristics of
the dither signal. Dither signals can be characterized on
the basis of signal type, e.g. noise, amplitude (small-
scale or large-scale), or in terms of frequency
(narrowband or broadband). Figure 3 depicts various
types of dither signals in the frequency domain. Note
that for narrowband signals which are outside the
information bandwidth of interest, the dither signal can
be removed by digital filtering following the conversion.
Dither signals are also often characterized on the basis
of the probability distribution of the dither amplitude,
which may be uniform or Gaussian (for random noise).
Amplitude
(LSBs)
b
c
a
1 LSB Frequency
Information Bandwidth fs /2
a. Small-scale broadband dither
b. Large-scale broadband dither
c. Narrowband dither
Figure 3 — Types of dither
Dithering can provide significant improvements in the
ability of a converter to extract signals below its LSB
resolution, and in linearizing a converter’s performance.
The improvements vary with the degree and type of
dither employed. Combined with the inherent
time-averaging property of subsequent digital filtering, a
dithered ADC/digital filter system effectively removes
or smoothes the quantization of the typical “staircase”
transfer function of an ADC converter.
 4

This can be illustrated as follows: Consider an ideal The general equation for computing the expected value
ADC with staircase transfer function whose quantized for a transfer function with one random variable is
ideal error transfer function is shown in Figure 4. given by:

∞
∫
Output
error G(z) = p(z) e (z) dz
–∞

Where e(z) represents the transfer function and p(z)

represents the probability distribution function of the
random variable z. The expected value computes the
+q/2 average of the transfer function weighted by the relative
likelihood of z. For the case of dithering in which the
random variable z is added to the input signal of
amplitude x, the resulting expected value of the transfer
function appears as follows:
- q/2

∞
G(x) = ∫ p(z) e (x + z) dz
–∞
Input

The function x(x+z) corresponds to the transfer

Figure 4 — Error transfer function of ideal ADC
The expected error transfer function resulting from
dithering with a random noise signal can be computed
by evaluating the expected transfer function with the
weighted probability distribution of the dither.
Figure 5 depicts a uniformly distributed PDF of random
dither with exactly 1 LSB of dither amplitude.
function in the variable x added to the random variable
z representing the dither.
Note that this resembles a convolution, and hence we
can illustrate the process graphically as the integration
of the dither PDF as it is slid past the ADC error
transfer function shown in Figure 6.
Output
error

Probability

+q/2

-q/2

1/d

Input
-d/2 d/2
Amplitude Figure 6 — Condition integration yields zero
Figure 5 — PDF of LSB dither
For a dither amplitude of 1 LSB the integration result is
zero, yielding an ADC transfer function that is
completely linear. The high-order distortion terms
associated with the polynomial expansion of the
 5

quantized transfer function are effectively removed by

3rd Harmonic Distortion
the dithering. This result is true for dither amplitudes
0
which are integral multiples of the ADC LSB.
Large-Scale Dithered
Low-order distortion performance improvements can Undithered
also be obtained by the application of large-scale dither.
In practice, the large-scale dither effectively smoothes dBc
the inflections caused by integral nonlinearities of the
ADC transfer function.

Although mathematically it can be shown that dithering

a transfer characteristic with a single 2nd or 3rd order -100
0 Hz 1.0 E+7
distortion term does not improve that term, it does
improve the low-order distortion of transfer functions
Figure 7 — Large-scale dithered vs. undithered performance
whose polynomial expansion also contains higher order
of the same converter
terms as well. This is true of ADC transfer functions in
practice. The convolution generates lower order terms
from the higher order terms by the mathematical
integration which combine with the original low-order
terms of the transfer function to make them smaller.
This results in an overall improvement in low-order
distortion. The degree of improvement is directly
related to the magnitude of the dither signal employed.
A larger amplitude dither signal yields greater reduction
of low-order distortion for a given signal amplitude.

Figure 7 demonstrates this phenomenon with a

measurement that compares the third harmonic
distortion performance of the HP 89410A converter
both for 1/2-scale dithered and undithered modes of
operation. As the plot illustrates, the third-order
distortion is significantly improved by the large-scale
dithering.

Operation of the HP 89400 Series
VSAs’ ADC
Figure 8 depicts the block diagram of the large-scale
dithered ADC converter. The dither signal itself consists
of random noise which must be uncorrelated to the
input signal. A random 12-bit sequence is generated by a
pseudo-random number generator with a period of
2^39-1 samples. At a sample rate of 25.6 MSPS this
yields a period of about six hours, assuring that the
periodicity of the dither is well below any measurement
frequency of interest. Adjacent dither samples are
designed to be highly uncorrelated to assure the power
spectral density of the random noise is flat with
frequency.
The sampled random noise sequence follows two signal
paths in the block diagram. On the analog input side of
the block diagram the sequence is converted to an
analog random noise representation of the
pseudo-random number sequence by the high-speed
dither DAC which runs at the sample rate of the
converter. The analog representation of the dither
signal is then combined with the analog input signal at a
wideband summing junction comprised of very
wideband, low-distortion operational amplifers. The
combined signal consisting of the input signal plus
added random noise dither is applied to the
track-and-hold input of the analog-to-digital conversion
block.
Figure 8 — Block diagram of large-scale dithered converter
6
The digital path of the PRN generator is routed to a
high-speed, 13-bit digital subtractor immediately
following the analog-to-digital conversion. The
subtractor is composed of pipelined adders with
look-ahead carry to subtract corresponding values of
dither on a per-sample basis from the converted digital
representation of the input signal plus dither. The
appropriate number of delays in the digital path of the
converter assures that correctly corresponding values
of dither are subtracted, thereby removing the dither
and leaving only the digital representation of the
original input signal.
Small-scale dithered converters can often perform the
subtraction step with a minimal noise penalty because
the dither signal levels are on the order of a few LSBs.
In fact, some small-scale dithered converters ignore the
subtraction step entirely because any residual noise left
by the subtraction errors are often negligible. For
large-scale dither, because the large signal levels
employed may exceed the magnitude of the input signal
itself, the precision of the subtraction step becomes
critical.
Accurate subtraction is achieved by using a digital
correlator as part of a low-frequency feedback loop to
generate a feedback error signal. The feedback error
signal generated from the correlator/accumulator is
converted into an analog error signal by the automatic
gain control DAC. The analog error signal servos the
amplitude of the dither signal at the output of the dither
DAC to assure exact subtraction. This summarizes the
operation of the large-scale dithered ADC.
 7

Performance of the HP 89400 Series

VSAs’ ADC

The converter has 2 modes of operation: 1/4-scale and

1/2-scale dither levels relative to the converter
full-scale, each optimized for the HP 89410A and 89440A
respectively. Figure 9 depicts the resultant low- and
high-order distortion performance for the HP 89410A
ADC at 1/2-scale dithered operation.

At nominal full-scale the HP 89410A ADC typically

provides 80dBc 2nd-order, and 85dBc 3rd-order
distortion dynamic range with 5 dB of overhead. The
high-order distortion associated with the hardfloor
(which is fixed for undithered converters) is Figure 10 — HP 89410 ADC low order amplitude distortion
behavior
significantly lowered allowing for “soft” distortion
behavior at input signal levels other than nominal
full-scale. Because of the soft distortion characteristic The HP 89440A which utilizes the converter in 1/4-scale
of the dithered converter, the performance measured in dithered mode exhibits similar characteristics.
dBc remains nearly constant over 10 dB of input level However, due to different overhead requirements
range. This flexibility in the nominal operating point associated with the front-end, the overhead in the
allows better optimization of the converter dynamic HP 89440A is 2dB. Readers are encouraged to consult
range to the overall instrument distortion performance. the current HP 89400 Series VSAs data sheet for a full
The unused overhead in the HP 89410A is available to description of each instrument’s dynamic range
users for measurements with higher SNR specifications.
measurements. Figure 10 depicts the typical low-order
distortion performance for the HP 89410A in terms of
dBc indicating relatively constant distortion dynamic
range over +/–5 dB of signal range.

Figure 9 — HP 89410 ADC distortion dynamic range at 1/2-scale dithered operation

For more information, call your In Europe, Africa and Middle East,
local HP sales office listed in your please call your local HP sales office
telephone directory or an HP regional or representative:
office listed below for the location of
your nearest sales office. Austria/East Central Europe:
(0222) 2500-0
United States of America: Belgium and Luxembourg:
Rockville, MD (02) 778 31 11
(301) 258 2000
Denmark:
Rolling Meadows, IL 45 99 10 00
(708) 255 9800
Finland:
Fullerton, CA (90) 88 721
(714) 999-6700
France:
Atlanta, GA (1) 69.82.65.00
(404) 955 1500
Germany:
Canada: (06172) 16 0
(416) 678 9430
Greece:
Japan: (01) 68 96 411
(813) 3335 8192
Ireland:
Latin America: (01) 284 4633
Miami, Florida
(305) 267 4245/4220 Israel:
(03) 5380 333
Australia/New Zealand:
(008) 13 1347 Italy:
Melbourne Caller (02) 92 122 241
272 2555 Netherlands:
Far East: (020) 547 6669
Hong Kong Norway:
(852) 848 7070 (67) 159 700
Korea Portugal:
(2) 769 0800 (11) 301 73 30
Taiwan South Africa:
(2) 717 9524 (011) 806 1000
Singapore Spain:
(65) 291 8554 900 123 123
India Sweden:
(11) 690 355 (08) 750 20 00
PRC Switzerland:
(1) 505-3888 (057) 31 21 11
Turkey:
(04) 125 83 13
United Kingdom:
(0344) 362 867
For countries not listed, contact
Hewlett-Packard International Sales
Branch, Geneva, Switzerland.
Tel: +41-22-780-4111
Fax: +41-22-780-4770

Data subject to change

© 1994 Hewlett-Packard Co
Printed in U.S.A. 8/94
5091-7668E