You are on page 1of 2

EC2101 DIGITAL SYSTEMS

C Slot (Mon 10-10.50, Tue 9-9.50, Wed 8-8.50, Fri 1-1.50 tutorial ) 4 Credits Instructors: Dr. C. Mathiazhagan (ESB106) and Dr. T. G. Venkatesh (ESB127) _____________________________________________________________________________________ Course Outline 1. Introduction to Digital Systems and Boolean Algebra (1 week) Basic logic operation and logic gates; Truth table. Basic postulates and fundamental theorems of Boolean algebra; Canonical (SOP and POS) forms; Multiplying out and factoring expressions; Binary, octal and hexadecimal number systems. 2. Logic Minimization and Implementation (2 weeks) Min-term and Max-term expansions; Karnaugh-maps, essential prime implicants, four and five variable maps; incompletely specified functions, NAND and NOR implementation, Quine-McCluskey method; Map entered variable method; Switch level representation and realisation using transistors; Logic families TTL, CMOS 3. Combinational Logic (2 weeks) Multi level gate circuits, Decoders, encoders, multiplexers, demultiplexers and their applications; Parity circuits and comparators; Arithmetic Circuits: Representation of signed numbers; Adders, Ripple carry, carry look ahead, BCD adders. 4. Sequential Logic (2 weeks) Latches and flip-flops: SR-latch, D-latch, D flip-flop, JK flip-flop, T flip-flop; Setup and Hold parameters, timing analysis; Registers and counters; Shift register; Synchronous counter design using D, SR, JK flip flops. 5. State Machine Design (2 -3 weeks) Definition of state machines, state machine as a sequential controller; Moore and Mealy state machines; Derivation of state graph and tables; Sequence detector; Code converter; state table reduction using Implication table; state assignment, logic realisation; Designing state machine using ASM charts; 6. Memory and Programmable Logic Devices (2 weeks) Read-only memory, read/write memory - SRAM and DRAM ; PLAs, Reduced PLA table; PALs and their applications; Sequential PLDs and their applications; State- machine design with sequential PLDs; 7. Advanced Topics (2 - 3 weeks) Asynchronous Sequential Machines, Static and Dynamic hazards; race free design; testing digital circuits;

8. Mini Project (1 week) Hardware description language; modelling combinational and sequential circuits; state machine realisation. Text books: 1. Morris. M. Mano, Michael D. Ciletti, Digital Design, 4th Ed. Prentice-Hall India. 2008. 2. Charles. H. Roth, Jr., Fundamentals of Logic Design, 5th Ed., Thomson Brooks /Cole, 2005.

Reference Books: 1. Charles. H. Roth, Jr., Digital System Design using VHDL, Indian Ed., Thomson Brooks /Cole, 2006. 2. Brown and Vranesic, Fundamentals of Digital Logic with VHDL, McGraw Hill. 3. J. F. Wakerly, Digital Design Principles and Practices, Prentice Hall.

Evaluation Procedure: Quiz I Quiz II Assignment Tests Mini Project End Semester 20 marks 20 marks 10 marks 10 marks 40 marks

Notes: All quizzes and exams are open book/notes. Assignment tests are open book only. Every alternate week, there will be a tutorial class with a short assignment test in the beginning. An assignment sheet will be given a week earlier before the tutorial class and you will have to work out and submit one of the problem given in the assignment sheet. Mini Project will involve simulating larger digital circuits using HDL simulators.