Code No: V0222/R07

Set No. 1

II B.Tech II Semester Supplementary Examinations, December 2009 LINEAR AND DIGITAL IC APPLICATIONS ( Common to Electrical & Electronic Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Dene parameters of Op-amp. i. ii. iii. iv. CMRR Slew rate O-set voltage Large signal voltage gain. [8+8]

(b) Explain the frequency response of Op-Amp. 2. (a) Explain about any two linear and nonlinear applications of Op-amp.

(b) Draw the circuit of an inverting adder using Op-amp and explain its operation. Derive the input / output relationship. [8+8] 3. (a) A fourth order Butterworth polynomial is given as (S2 +0.765S+1) (S2 + 1.848S+1). Design the fourth order Butterworth lter having upper cuto frequency 2 KHz. Assume suitable data. Draw the circuit diagram with suitable values. (b) What are the gain constraints imposed on higher order lters? Explain.[10+6] 4. (a) Design a few multi-vibrator using 555 timer to give a 25% duty cycle waveform at10 KHz and 5 V amplitude. Draw the diagram with waveforms. (b) Explain the use of 555 timer as free running ramp generator and draw the output waveforms. [8+8] 5. (a) Explain the operation of the successive approximation A/D converter, with a block diagram and timing diagram. Give it?s advantages. (b) With help of a block diagram and timing diagram explain the operation of ramp type A/D converter. [8+8] 6. (a) Draw the circuit diagram of basic TTL NAND gate and explain the three parts with the help of functional operation? (b) List out TTL families and compare them with reference to propagation delay, power consumption, speed-power product and low level input current? [8+8] 7. (a) Design a 3 input 5-bit multiplexer? Write the truth table and draw the logic diagram. (b) Write short notes on full subtractor. 1 of 2 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. [8+8]

Code No: V0222/R07

Set No. 1
[8+8]

8. (a) Design a conversion circuit to convert a D ip-op to J-K ip-op? (b) Design a 4-bit binary synchronous counter using 7474?

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Code No: V0222/R07

Set No. 2

II B.Tech II Semester Supplementary Examinations, December 2009 LINEAR AND DIGITAL IC APPLICATIONS ( Common to Electrical & Electronic Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Draw the pin diagram and schematic symbol of a typical Op-amp IC741 and explain the function of each pin. [6+6+4] (b) Discuss the three basic types of linear IC packages and briey explain the characteristics of each. (c) State the two types of integrated circuits classied according to their mode of operation and briey explain the signicance of each. 2. (a) Discuss important characteristics of a comparator and the limitations of Opamps as comparators. (b) Explain the operation of Schmitt trigger circuit. [8+8]

3. (a) List the conditions for oscillation in all the three types of oscillators, namely, RC phase shift, wien- bridge and quadrature oscillators. (b) Explain the dierence between a signal generator and a function generator. (c) Justify the name for quadrature oscillator. [8+4+4]

4. (a) Explain the operation of Monostable multivibrator using 555 timer. Derive the expression of time delay of a Monostable multivibrator using 555 timer. (b) Design a Monostable multivibrator using 555 timer to produce a pulse width of 100 ms. [10+6] 5. (a) Explain the operation of an 8-bit tracking type Analog to Digital converter. (b) Compare the conversion times and eciencies of 8-bit tracking type and successive approximation type Analog to Digital converters. [8+8] 6. (a) Explain in detail all the parameters of logic families. (b) Explain the operation of basic NAND and NOR latches. (c) Explain how a CMOS device is destroyed? [7+5+4]

7. (a) Design the 32 input to 5 output priority encoder using four 74LS148 and gates? (b) Design a CMOS transistor circuit with the functional behavior F(X) = (A + B)(B + D)(A + D). 8. (a) Distinguish between combinational and sequential circuit. (b) Dene the following terms as applied to ip ops. 1 of 2 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. [8+8]

Code No: V0222/R07 i. ii. iii. iv. v. Set up time. Hold time. Propagation delay. Maximum clock frequency. Power dissipation.

Set No. 2

[8+8]

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Code No: V0222/R07

Set No. 3

II B.Tech II Semester Supplementary Examinations, December 2009 LINEAR AND DIGITAL IC APPLICATIONS ( Common to Electrical & Electronic Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Give the design procedure of a compensating network for an Op-amp which uses 10V supply voltages. Assume necessary data. (b) In the circuit of gure 1, R1 =100 , RF = 4.7K , CMRR=90 db. If the amplitude of the induced 60-Hz noise at the output is 5mV (rms). Calculate [8+8] the amplitude of the common-mode input voltage Vcm .

Figure 1 2. (a) Write short notes on non inverting comparator. (b) For the given (gure 2b) inverting Schmitt trigger, calculate its higher and lower trigger levels. [8+8]

Figure 2b 3. (a) Calculate the frequency of oscillation of a 566 VCO IC for the external component values RT = 6.8K and CT = 470PF. Assume other component values if necessary. Shown in gure 3b. (b) Derive the expression for frequency of VCO and list important specications of 566 VCO IC. [8+8]

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Code No: V0222/R07

Set No. 3

Figure 3b 4. Discuss the signicance of phase detector, Low pass lter, amplier and a VCO in PLL. [4 4=16] 5. Write short notes on: (a) Dual-slope A/D converter. (b) Charge balancing type Analog to Digital converter. [8+8]

6. (a) Draw the circuit diagram of basic TTL NAND gate and explain the three parts with the help of functional operation? (b) List out TTL families and compare them with reference to propagation delay, power consumption, speed-power product and low level input current? [8+8] 7. (a) Give the logic diagram of 74139 and explain its truth table? (b) What is an encoder? Write short notes on decimal to binary encoder? [8+8] 8. (a) Design a conversion circuit to convert a D ip-op to J-K ip-op? (b) Design a 4-bit binary synchronous counter using 7474? [8+8]

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Code No: V0222/R07

Set No. 4

II B.Tech II Semester Supplementary Examinations, December 2009 LINEAR AND DIGITAL IC APPLICATIONS ( Common to Electrical & Electronic Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Give the design procedure of a compensating network for an Op-amp which uses 10V supply voltages. Assume necessary data. (b) In the circuit of gure 1, R1 =100 , RF = 4.7K , CMRR=90 db. If the amplitude of the induced 60-Hz noise at the output is 5mV (rms). Calculate [8+8] the amplitude of the common-mode input voltage Vcm .

Figure 1 2. (a) Find Vo for the following circuit given (gure2). (b) Design a subtractor circuit whose output is equal to the dierence between the two inputs. Use a dierential Op-amp conguration. [8+8]

Figure 2 3. Derive the transfer function, gain and phase angle for rst order and second order low pass active lter. [16] 4. Explain the functional block diagram of PLL emphasizing the importance of capture range and Lock range. [16] 1 of 2 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark.

Code No: V0222/R07 5. (a) List out dierent types of A/D converters.

Set No. 4

(b) Draw the schematic circuit diagram of dual-slope A/D converter and explain its operation. Derive expression for output voltage. (c) Compare dual-slope A/D converter with successive approximation A/D converter. [4+8+4] 6. (a) What are the draw backs of TTL gate? Explain how they are overcome using Schottky clamp? (b) Compare the various parameters of all TTL series NAND gates. 7. (a) Write short notes on parity generator and checker? (b) Design a 8:1 multiplexer using two 4:1 multiplexers? Write the truth table and draw the logic diagram? [8+8] 8. (a) Write short notes on parallel in parallel out shift register. (b) Design a conversion circuit to convert a JK ip-op to D ip-op? [8+8] [8+8]

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