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Synchronous Sequential Logic L i

2010.10.13

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SR Latch
The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates.

RS Flip-Flops characteristic equation is Q(t+1) = S + RQ(t)

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SR Latch with Control Input p

Graphic Symbols

RS

RS

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D Latch
One way to eliminate the undesirable condition of the indeterminate state in the RS latch is to ensure that inputs R and S are never equal time. to 1 at the same time

Graphic Symbols

D Flip-Flops characteristic equation is Q(t+1) = D

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D Latch

Verilog Design: D Latch

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Edge-Triggered D Flip-Flop g gg p p
It is similar to the symbol used for the D latch except for the arrowhead-like symbol in front of the letter C designating a dynamic input. input

Positive-edge

Negative-edge

Verilog Design: edge-triggered D Flip-Flop edge triggered Flip Flop

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D Flip-Flop with Asynchronous Reset p p y

Flip Flop Verilog Design: D Flip-Flop with Asynchronous Reset

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JK Flip-Flop p p
There are three operations that can be performed with a flip-flop: set it to 1, reset it to 0, or complement its output. The JK flip-flop operations. performs all three operations

Graphic Symbols

JK Flip-Flops characteristic equation is Q(t+1) = J Q(t) + KQ(t)

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JK Flip-Flop p p

Flip Flop Flip Flop Verilog Design: JK Flip-Flop from D Flip-Flop and gates

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T Flip-Flop p p
The T flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when inputs J and K are tied together.

The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gate.

Graphic Symbols

T Flip-Flops characteristic equation is Q(t+1) = T Q(t)

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T Flip-Flop p p

Verilog Design: T Flip-Flop from D Flip-Flop and gates

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JK Flip-Flop p p

Verilog Design: JK Flip-Flop for Behavioral Modeling

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