NITTEMEENAKSHIINSTITUTEOFTECHNOLOGY

DEPARTMENTOFELECTRONICSANDCOMMUNICATIONENGINEERING MODELQUESTIONPAPER

VERILOG(EC55)
UNIT:1 1. WHAT IS VERILOG HDL? WHAT ARE THE MAJOR CAPABILITIES OF VERILOG HDL?(5) 2. WHAT ARE COMPILER DIRECTIVES? EXPLAIN THE TIMESCALE COMPILER DIRECTIVE. 3. FIND THE VALUE OF FOLLOWING EXPRESSIONS IF THE TWO UNSIGNED VARIABLES, A=4B1001 AND B=4 B1101: (I){A, B} (II)(A&&B) (III)~^(A) (IV) B<<3

(5)

(4)

4. WRITE THE VERILOG CODE FOR A FULL ADDER IN ALL THE THREE MODELING (9) STYLES. OR 5. WHAT IS THE IEEE STANDARD FOR VERILOG? WHAT IS THE BASIC UNIT OF DESCRIPTION IN VERILOG HDL ? GIVE THE SYNTAX FOR IT WITH AN EXAMPLE. (5) 6. USING THE DATAFLOW DESCRIPTION STYLE, WRITE A VERILOG HDL MODEL FOR THE FOLLOWING EXCLUSIVE -OR LOGIC. USE THE SPECIFIED DELAYS: (5)
A

Z B NOT GATE DELAY=1NS, AND GATE DELAY=5NS, OR GATE DELAY=4NS .

7. FIND THE VALUE OF FOLLOWING EXPRESSIONS: (4) (A)IF A=4B 10X1, B=4B 01111 THEN A+B=_ (B) -8%-3= _ (C)A_BUS= {2{6B011010}} = _ (D)SUM= (A>B)? POSITIVE:NEGATIVE; GIVEN A= 15 AND B=10.

8. WRITE A VERILOG CODE FOR 2X1 MUX USING ALL THREE MODELING STYLE .(9)
UNIT : 2 9. WHAT DO YOU UNDERSTAND BY GATE DELAYS? WHAT ARE THE DIFFERENT TYPES OF GATE DELAYS? G IVE EXAMPLE OF EACH. (5) 10. WHAT ARE THE TRISTATE GATES? EXPLAIN WITH SYNTAX AND TRUTH TABLE .(3) 11. WRITE A GATE LEVEL DESCRIPTION OF 2-TO-4 DECODER CIRCUIT WITH A NEAT REPRESENTATION SUCH THAT RISE DELAY =2, FALL DELAY=3 FOR NOT GATES AND RISE DELAY =4, FALL DELAY=5 FOR NAND GATES. (5)

11. WRITE A VERILOG CODE FOR 4X1 MUX USING 2X1 UDP. OR

(7)

12. (A) WHAT DO YOU UNDERSTAND BY GATE LEVEL MODELING? WHAT ARE THE VARIOUS MOS SWITCHES ? EXPLAIN BRIEFLY . (B) HOW IS A COMBINATIONAL UDP DIFFERENT FROM A SEQUENTIAL UDP ? (8) 13. WRITE A GATE LEVEL DESCRIPTION FOR 4X1 MUX WITH A NEAT REPRESENTATION. (5) 14. WRITE A UDP TO MODEL A D-TYPE FLIP FLOP WITH AN ASYNCHRONOUS CLEAR (7) MIXING EDGE TRIGGERED AND LEVEL-SENSITIVE BEHAVIOUR. UNIT: 3 15. WHAT IS AN INTERSTATEMENT DELAY AND INTRASTATEMENT DELAY? EXPLAIN WITH AN EXAMPLE. (5) 16. WRITE A VERILOG CODE TO IMPLEMENT AN 8X1 MUX USING 4X1 MUX USING (10) DATAFLOW MODELING . 17. WHAT ARE THE DIFFERENCES BETWEEN A SEQUENTIAL BLOCK AND A PARALLEL BLOCK? G IVE EXAMPLE FOR EACH. (5) OR 18. WHAT DOES THE FOLLOWING MEAN? (A)SUM=REPEAT 2 @ (POSEDGE CLK) SUM+1; (5) (B)REPEAT 2@ (NEGEDGE CLOCKZ); 19. WRITE THE BEHAVIORAL DESCRIPTION OF THE TWO INTERACTING PROCESSES SHOWN BELOW : (10)
SERIAL_IN CLK

PROCESS Rx

READY DATA ACK

PROCESS Micro processor

PARALLEL _OUT

20. DESCRIBE THE BEHAVIOUR OF A JK FLIP FLOP USING AN ALWAYS STATEMENT. (5)

UNIT:4 21. (A) WHAT IS THE DIFFERENCE BETWEEN A GATE INSTANTIATION AND A MODULE INSTANTIATION? (2) (3) (B ) WRITE A BRIEF NOTE ON PORTS. 22. USING THE MODULE MUX4X1, WRITE A STRUCTURAL MODEL FOR 16-TO-1 (10) MULTIPLEXER. (5) 23. WRITE A TASK THAT MODELS A FULL ADDER. OR 24. WHAT ARE THE DIFFERENCES BETWEEN TASKS AND FUNCTIONS? (5) 25. WRITE A STRUCTURAL MODEL FOR THREE BIT UP-DOWN COUNTER WITH A NEAT REPRESENTATION . (10) 26. EXPLAIN WITH EXAMPLE ABOUT THE UNCONNECTED PORTS. (5) UNIT:5 27. WRITE A MODEL FOR A 4 BIT SHIFT REGISTER WITH SERIAL-IN DATA, SERIALOUT DATA USING A FOR LOOP WITH AN ALWAYS STATEMENT. (5) 28. EXPLAIN A MOORE FSM WITH AN EXAMPLE. MENTION THE STATE TRANSITION DIAGRAM FOR IT. (10) 29. WHAT DO YOU UNDERSTAND BY TRANSPORT DELAY? EXPLAIN WITH AN EXAMPLE . (5) OR 30. MODEL A 4X1 MULTIPLEXER USING A CASE STATEMENT IN AN ALWAYS STATEMENT AND A CONTINUOUS ASSIGNMENT WITH A CONDITIONAL OPERATOR. (6) 31. EXPLAIN A MEALY FSM WITH AN EXAMPLE. MENTION THE STATE TRANSITION DIAGRAM FOR IT. (10) 32. WRITE A MODULE FOR A HALF ADDER AND MENTION THE DELAYS AT THE PORT BOUNDARIES USING A SPECIFY BLOCK. (4)