EEET2362 HDL and High Level Synthesis Project 1: ALTERA DE2-70 Synchronous Digital Hierarchy Terminator (35%) Due

date: 11:59 am Monday of Week 6 (23rd July 2012)

Project 1:
This is to be completed in pairs. Your task is to design and implement VHDL Code on the Altera DE2-70 board met the ITU g.707 standard. You will submit VHDL code and test benches and demonstrate the prototype. Implement the following sections of the ITU g.707 standard: 6.2 Basic frame structure (STM-1) 6.2.1 Section overhead 6.5 Scrambling 9.2.2 SOH bytes description 9.2.2.1 Framing: A1, A2 9.2.2.4 BIP-8: B1 9.2.2.8 BIP-N24: B2 Alarms
LOS Loss of Signal LOS is raised when the synchronous signal (STM-N) level drops below the threshold at which a BER of 1 in 103 is predicted. It could be due to a cut cable, excessive attenuation of the signal, or equipment fault. The LOS state will clear when two consecutive framing patterns are received and no new LOS condition is detected. OOF state occurs when several consecutive SDH frames are received with invalid (errored) framing patterns (A1 and A2 bytes). The maximum time to detect OOF is 625 microseconds. OOF state clears within 250 microseconds when two consecutive SDH frames are received with valid framing patterns. LOF state occurs when the OOF state exists for a specified time in microseconds. The LOF state clears when an in-frame condition exists continuously for a specified time in microseconds. The time for detection and clearance is normally 3 milliseconds.

OOF

Out of Frame Alignment

LOF

Loss of Frame

Fundamentally, you need to implement the above. It will have a component that creates an empty payload. The payload will then be framed into a STM-1 packet. B1, B2 will be calculated and inserted into the frame. The packet will be scramble and then deserialized and sent over the GPIO ports (two pins per a receiver and another two pins per a transceiver). The STM-1 clock rate is 155.520 MHz (Hint: use the Mega-function Phase lock loop, multiplier and dividers). Marks will be deducted for excess code (Dead code) You must abide by the coding standard (see blackboard examples) You are encourage to use all of the VHDL standard including but not limited to packages, procedures, functions, records, etc.

Plagiarism & Writing Help

All used sources must be properly acknowledged with references and citations, if you did not create it. Quotations and paraphrasing are allowed but the sources must be acknowledged. Failure to do so is regarded as plagiarism and the minimum penalty for plagiarism is failure for the assignment. Sharing of code is prohibited because it enables plagiarism. Copying sections of code is plagiarism. All assignments are checked electronically and plenties will apply.

EEET2362: HDL and High Level Synthesis

2011B

The report will be check with TurnItIn and the Code will be checked with an automatic checker.

Due Date & Submission

Project 1 is due at Due date: 11:59 am Monday of Week 6 (23rd July 2012) By the due date, you must submit: 1. Soft copy of your code, report and statement of authorship to Blackboard.
Before submitting, carefully read the Assignment Submission Standards document posted on Blackboard. The submission should be reasonable in size, e.g. it should not exceed 5 MB.

Your filename should be labeled according to RMIT naming convention: studentNumber1_ studentNumber2.zip Late submission of assignments will be penalised as follows: For assignments 1 to 5 days late, a penalty of 10% (of total available marks) per day. For assignments more than 5 days late, a penalty of 100% will apply. Your submission must be compatible with the software in RMIT, Computer Laboratories/Classrooms. Marking Guidelines: Description Marks Awarded Report Appropriate Explanation of Project 5 Appropriate Methodology and Test Strategy 5 Appropriate Results and Test Cases 5 Sub Total 15 Presentation/Demonstration Adhere to Specifications (test using two boards and loopback) 2.5 x 10 (for each of the sections above) Sub Total 25 Total 35 How to Upload your file to Blackboard Open Quatus II Open Your Project Project (menu) -> Archive Call it your student No. e.g. s1234567 Open your project folder. You should see a file called s1234567.qar Put the report and this file in a folder. Zip the folder (use 7zip or WinZip. Do not use .rar files) Upload this file to blackboard. Test: Move your s1234567.qar file to desktop. Open Quartus II Project (menu) -> Restore Archive Project (Your project should load) Compile the Design and download it.

RMIT International University Vietnam

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EEET2362: HDL and High Level Synthesis

2011B

EEET2362 HDL and High Level Synthesis Project 1: ALTERA DE2-70 Synchronous Digital Hierarchy Terminator (35%)

Student Name: Student Name:

Student Number: Student Number:

Marking Guidelines: Description Report Appropriate Explanation of Project Appropriate Methodology and Test Strategy Appropriate Results and Test Cases Sub Total Presentation/Demonstration Adhere to Specifications (test using two boards and loopback) 6.2 Basic frame structure (STM-1) 6.5 Scrambling 9.2.2.1 Framing: A1, A2 9.2.2.4 BIP-8: B1 9.2.2.8 BIP-N24: B2 Alarms LOS - Loss of Signal OOF - Out of Frame Alignment LOF - Loss of Frame Sub Total Total

Marks Awarded

Total 5 5 5 15

2.5 x 10 (for each of the sections above

25 35

RMIT International University Vietnam

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