Estimation of Delay, Power, and Bandwidth for On-Chip VLSI Global Interconnects

Vikas Maheshwari
M.Tech-Final Year (Microelectronics & VLSI) (08/ECE/455 ) Under the supervisions of

Dr. Ashis Kumar Mal

Asst. Professor, ECE Deptt N.I.T. Durgapur

Mr. Rajib Kar

Asst. Professor, ECE Deptt N.I.T. Durgapur

Content
Introduction Moment Matching and Model Order Reduction Interconnect Models Distributed RC Tree Model Distributed RLC Tree Model Distributed RLCG Tree Model Conclusion Future Prospects Publications References

Introduction
Interconnection is a medium through which signal propagates from point A to reach other points, such as B and C. In the nanotechnology age, as ultra deep sub-micron effects continue to wreak havoc on the integrity of the signal, so efficient and accurate computation of interconnect parameters has become critical. Due to the large number and complex nature of on-chip interconnects, the accurate estimation of the propagation delay in the interconnects is very important for the design of high speed VLSI systems. This work represents the analysis and parameters estimation of RC, RLC and RLCG interconnects. Topics covered in this work include on-chip interconnect delay , bandwidth, crosstalk and power modeling for different interconnect models.

Moment Matching
Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay expression, to moment matching methods which creates reduced order transimpedance and transfer function approximations. If more moments are required for an accurate approximation, moment matching or other order reduction schemes can be used to generate reduced-order dominant pole/zero approximations for the interconnect transfer, admittance, and impedance functions. Consider the simple RC ladder circuit shown in Figure 1 We can express the transfer function of this circuit as
.......... + ansn ...... Vout s) a0 + a1s + a2s2 + .......... ( H(s) = = Vin s) 1+ b1s + b2s2 + .......... ( .......... + bmsm ........

Figure 1 Simple RC ladder Circuit

where m>n

Expanding this equation about s = 0 we can rewrite the transfer function as a series in powers of s :

H(s) = m0 + m s + m2s2 + m3s3 +.......... .......... .. .......... .......... 1

(1)

where the coefficients, mj s are known as circuit moments and can be shown as

mq =

( 1)q
q!

t q h ( t ) dt

(2)

It is straightforward to show that the first few central moments can be expressed in terms of circuit moments as follows 0 = m0 = 1 (3) 1 = 0 is the area under the curve.

2

m 12 = 2m 2 m0 6 m 1m = 6m 3 + m0

m 12 2 1 m0

2 is variance of the distribution 3 is a measure of the skew ness

Model Order Reduction

The aim of MOR is to perform the simulation and analysis on the reduced system instead of the original one in order to increase computational efficiency. MOR is the technique that approximates the original large scale system with a smaller scale system without introducing much degradation of accuracy in both frequency and time domains. Fig.2 demonstrates the general mechanism of MOR in a single-input single-output where r<<n such that the transfer function of the reduced order system is approximated to that of the original one, i.e., G(s) G(s)
b0 + b1 s + b2 s 2 + ...........................bn 1 s n 1 G ( s) = 1 + a1 s + a 2 s 2 + .................... + br 1 s r 1 2 n 1 ( s ) = b0 + b1 s + b2 s + ...........................bn 1 s G 1 + a1 s + a 2 s 2 + .................... + br 1 s r 1 Transfer Function of the original system (order n)

Transfer Function of the reduced system (order r )

Figure 2: MOR approximates the large scale original system of order n with a smaller scale system of order r.

Interconnect Models
On-chip global interconnect lines are modeled in three types as discussed bellow Distributed RC Interconnect Model Distributed RLC Interconnect Model Distributed RLCG Transmission line Interconnect Model Distributed RC interconnect models are of three types L, T, as shown in figure 3.

L-Type

T-Type

-Type

Distributed RC Tree Model

On-chip VLSI interconnect is most often modelled by RC tree. The RC model is easy to compute, but relatively inaccurate. Figure 3 shows a typical RC tree.

Figure 4 An Interconnect and its electrical model

For a uniform structure with a rectangle cross-section the resistance is given by

l R = RS w

Where

RS = t

l, t, and w are the resistivity, length, thickness, and width of the wire

For capacitance extraction many different techniques can be employed. Depending on the desired accuracy, these methods can vary from using very simple 2-D analytical models to employing 3-D electrostatic field solvers. 0.222 t w (4) C = 1.15 + 2.8 (4) h h The simplest curve-fitting based model approximates the per-unit-length capacitance as (5) C = C0 + C1w One conservative estimate for the number of lumped segments (N) required to model a URC, based on the maximum signal frequency of interest, is obtained by solving
f max 2N 2 (2 N 1) 1 cos 2N RC
(6)

RC Delay Model Based on Gamma Distribution

Elmore assumed k = m1 and therefore approximated the median (the desired delay) by the mean of the impulse response. The main idea behind our Delay metrics is to match the mean and variance of the impulse response to those of Gamma distribution. The Gamma distribution is a two parameter continuous distribution. It is well suited to match the impulse response of the generalized RC network since both are unimodel and have non-negative skewness. The PDF of Burrs distribution is shown in the following figure-5.

Figure 5 The Gamma Distribution Function

Venue: N.I.T. Durgapur, W.B.

The probability density function of gamma distribution g , n (t), is a function of one variable t and two parameters and n

g , n (t ) =

nt n 1e t
(n)

,t > 0

Where

( x) = y x 1e y dy, x > 0
0

Gammas cumulative distribution function [CDF] as a function of t is given by t h(t ) = 1 e , t > 0 (7) CDF must satisfy the following conditions

0 F (t ) 1

and

Lim F (t ) = 1 , Lim F (t ) = 0
t t 0

Calculation of Parameters of the Gamma Distribution Function

Mean and Variance of the Gamma function is given by

= m1

(8)

= m12 2m2

(9)

From (8) and (9),

m1 = 2 and m1 2m2 m12 n= 2 m1 2m2

(10)

Calculation of Median (50 % Delay) of the Gamma Distribution Function Median of Gamma function is given by Mode=3*Median-2* Mean
Median = Mode + 2Mean (n 1) n = + 2 / 3 3 n 1 n 1 = 3 / 3 = 3

(11)

From (3.27) and (3.28),

m12 2m2 Median = m1 3m 1 4 2 m2 or, Delay (50 %) = - m1 + 3 3 m1

(12)

Experimental Set-Up We have implemented the proposed delay estimation method using Gamma Distribution and applied it to widely used actual interconnect RC networks as shown in Figure6. For each RC network source we put a driver, where the driver is a voltage source followed by a resister.
60 ohm 60 ohm (7) (6) 1pF 1.2pF

80 ohm + -

60 ohm (1) (2)

60 ohm

60 ohm 60 ohm (5) (4) (3) 1pF 1pF 1.2pF

Vin 0.5pF 1pF

Figure 6 An RC Tree Example

We compare the delays obtained from SPICE with those found using our proposed model. The results for the 50% delay are summarized in Table 1.

Experimental Result Node 1 2 3 4 5 6 7 SPICE (ns) 0.196 0.477 0.700 0.845 0.919 0.375 0.452 Proposed Model (ns) 0.234 0.493 0.697 0.828 0.923 0.373 0.451

Table 1 Comparison of the 50% delays between SPICE and the Proposed Delay Metric (time in ns).

Distributed RLC Tree Model

Importance of On-Chip Inductance With these technology trends, on-chip inductance effects, such as delay increase, overshoot, and inductive crosstalk, can no longer be ignored. Inductance effects have become increasingly significant because: As the clock frequency increases and the rise time decreases, electrical signals comprise more and more high frequency components, making the inductance effect more significant. With the increase of chip size, it is fairly typical that many wires are long and run in parallel, which increases the inductive crosstalk. Due to the lack of highly conductive ground planes on the chips, the mutual coupling between the wires cover very long ranges and decrease very slowly with the increase of spacing.

Effect of Inductance
A key aspect of RLC delay estimation is first controlling the damping, then approximating the delay. Excessive settling time increases delay in some sense, both under-damping and over-damping adversely impact delay. This is evidenced by the responses in Figure 7(b) for the series terminated RLC line in Figure 7(a).

Figure 7 (a) A source terminated RLC Transmission Line. (b) Response of the RLC system as RS4>RS3>RS2>RS1.

Power-Estimation using Model Order Reduction Technique

We consider a distributed RLC line as shown in Figure 8

Fig 8 A distributed RLC Interconnect

Suppose that it is excited by a step input. Then, the Laplace transform of v(x, t) for a distributed RLC line of infinite length is given by

Vout(x, s) =Vin(x, s).A.B

Where

B=e

r x lc s ( s + ) l

r Z 0 (s + ) / s l A= r (s + ) l +R Z0 tr s

For the step input the output equation is (by taking Rtr=r)
r (s + ) / s x c l e V out ( x , s ) = r (s + ) l + r s l c s domain is given by The current equation in the time l
lc r s(s+ ) l

I ( x, t ) =
1 I( x , s) = r s

1 v( x, t ) r x
r r - x lc s ( s + l ) lc (s + ) e r l (s (s + )) = l (s + r ) l + r 2s rs lc s

By applying Laplace transform on both side of

r (s + ) / s x l e r (s + ) l + r l c s l c

lc

r s(s + ) l

lc

By equating the denominator term to zero, we get the pole of I(x, s) as

P1 = 0 and P2 = r l cr 2

The pole P2 is in the left half of the s-plane, so we can write

I ( x, p 2 ) = c ( 2l cr )
2 x r c ( 2 l cr 2 ) l cr 2

( r 2 + c ( 2l cr 2 ) )

The residue of I(x, s) at pole P2 is given by

r2 = lim ( s p 2 ) I ( x , s ) = rc 2 e
s p2 x r rc l cr 2

Thus the energy dissipation at the arbitrary position is given by

E ( x ) = r residue I ( x , p 2 ) = r rc 2 .e
x r rc l cr 2

c ( 2 l cr 2 ) ( l cr 2 )( r 2 +
2

c ( 2 l cr 2 ) )
c ( 2 l cr 2 ) + rc l cr 2

r c ( 2 l cr 2 ) l cr 2

= r 2c3

c ( 2 l cr ) (r +
2

c ( 2 l cr ) )
2

r x

The obtained expression for the distribution of energy dissipation can be plotted as an exponential form as shown in the Figure-9.

Fig 9 The Distribution of Energy Dissipation for a distributed RLC Interconnect

We have implemented the proposed power estimation method using Model Order Reduction technique and applied it to widely used actual interconnect RLC networks as shown in Figure-10.

Table-2 gives the comparative result of the energy dissipation computed using SPICE and our method.
No of Nodes=1000 SPICE Model (J) 0.2 1 8 19 100 6X102 8X102 103 104 105 106 Our Model (J) 0.2 1 8 10 75 575 700 8X102 8.6X103 8.5X104 8.8X105 No of Nodes=1500 SPICE Model (J) 0.2 1 8 10 102 6X102 8X102 103 104 105 106 Our Model (J) 0.2 1 8 10 85 590 795 9.2X102 9.25X103 9.35X104 9.57X105

Table-2 Comparison of the energy distribution for randomly generated RLC circuit

Figure-11 & Figure-12 show the graphical representation of the result for the circuit with 1000 and 1500 nodes respectively.

Fig-11. Comparison of the energy distribution for randomly generated RLC circuit with 1000 nodes

Fig-12. Comparison of the energy distribution for randomly generated RLC circuit with 1500 nodes

Distributed RLCG Tree Model

In case of very high frequency as in Giga scale (GHz), no longer can interconnects be treated as mere delays or lumped RC networks. The most common simulation model for interconnects is the distributed RLC model. In this case, the commonly and generally well-accepted Elmore delay calculation becomes inapplicable to RLC and RLCG interconnect networks due to their non-monotonic characteristics induced by inductances. Interconnect lines may be coupled to study the effects of mutual inductive and capacitive coupling. Our model considers both lossless components (i.e. L, C) and lossy components (i.e. R, G). The SPICE simulation justifies the accuracy of our proposed approach.

Transmission Line Model An infinitesimal unit length of the transmission line looks like the circuit as shown in Figure 13. The parameters are defined as R, L, C and G is Series resistance, Series inductance, Shunt capacitance and Shunt conductance per unit length.
Fig 13. RLCG parameters for a segment of a transmission line.

The following is a simple rule of thumb which can be used to determine when to use transmission line models.
rise ( fall ) < 2.5
l l 2.5 < rise ( fall ) < 5 v v l rise ( fall ) > 5 v l v {transmission line mod elling } {either transmission line or lumped mod elling } {lumped mod elling }

Crosstalk Crosstalk is undesired energy imparted to a transmission line due to signals in adjacent lines. The crosstalk noise between two shielded interconnects can produce a peak noise of 15% of VDD in a 0.18 um CMOS technology. In the complicated multilayered interconnect system, signal coupling and delay strongly affect circuit performances . Major impacts of cross talk are: (I) Crosstalk induces delays, which change the signal propagation time, and thus may lead to setup or hold time failures. (II) Crosstalk induces glitches, which may cause voltage spikes on wire, resulting in false logic behaviour. Crosstalk affects mutual inductance as well as inter-wire capacitance (III) crosstalk will induce noise onto other lines, which may further degrade the signal integrity and reduce noise margins (IV) crosstalk will change the performance of the transmission lines in a bus by modifying the effective characteristic impedance and propagation velocity .

Difference Model Approximation The time-domain difference approximation procedure should be employed only if transient characteristics are available . It can directly handle lines with arbitrary frequency-dependent parameters or lines characterized by data measured in frequency-domain For a single RLCG line, the analytical expressions are obtained for the transient characteristics and limiting values for all the modules of the system and device models. The difference approximation procedure involves an approximation of the dynamic part of the system transfer function, with the complex rational part of the transient characteristic with the real exponential series.

Modeling of Bandwidth Using Difference Model Approximation

We first consider the interconnect system consisting of single uniform line and ground as shown in Figure 5, and assume the length of the line is d.

The electrical parameters of each section are RX, LX, CX and GX, respectively, where R, L, C and G are per-unit length resistance, inductance, capacitance and conductance of the line.

Fig. 14 Equivalent circuit of each uniform section

Using Kirchoffs Law, we can write di ( x, t ) v ( x, t ) = i ( x, t ) Rx + Lx + v ( x + x, t ) dt

i ( x, t ) = Gx v( x + x, t ) + c x dv( x + x, t ) + i ( x + x, t ) dt

(1) (2)

Simplifying the above transformation, we get

two

equations

and

applying

Laplace
(3) (4)

V ( x) = ( R + sL) I ( x) x
I ( x) = (G + sC )V ( x) x

Differentiating equations (3) and (4) with respect to simplifying we get, 2

V ( x) = 2V ( x) 2 x
2 I ( x) = 2 I ( x) x 2

x, and after
(5)

(6)

The general solution of equation (5) is given by

(7) V ( x) = A1e x + A2 e x Where A1 and A2 are the constants determined by the boundary conditions. From equations (5) and (7 ) A1e x + A2 e x = ( R + sL) I ( x) x

I ( x) =

Assuming at x=d, the termination voltage and current are V (d) =V2 and I (d) =I2, respectively, then we get,

1 A1e x A2 e x Z0

(8)

V2 = A1e d + A2 e d
I2 =

(9) (10)

From equation (9) and (10) we get

A1 = 1 [V2 + I 2 Z 0 ]e d 2

1 [ A1e d A2 e d ] Z0

A2 =

1 [V2 I 2 Z 0 ]e d 2

Substituting these values of A1 and A2 in equation (7)

[V + I 2 Z 0 ] ( d x ) [V2 I 2 Z 0 ] ( x d ) + V ( x) = 2 e e 2 2

(11)

Similarly we calculate for I (x) as

I ( x) =

Let at x=0, V(x) =V1 and I(x) =I1 then from equation (9) and (11), we can write V1 = cosh( d )V2 + Z 0 sinh( d ) I 2 (13)
I1 = 1 sinh(d )V2 + cosh(d ) I 2 Z0
(14)

1 [V2 + I 2 Z 0 ] ( d x ) [V2 I 2 Z 0 ] ( x d ) e e Z0 2 2

(12)

So we can write ABCD matrix from equation (13) and (14)

Z 0 sinh(d ) cosh(d ) V1 V2 I = 1 sinh(d ) cosh(d ) I 1 Z 2 0
(15)

From equation (15), we can write the equation for the transfer function of the system
H ( s) = V2 ( s ) 1 = V1 ( s) cosh(d )
V2 ( s ) = V1 ( s)

(16)

After simplification, we get from equation (16)

H (s) = 1 (s + R G )( s + ) L C

(17)

Substitute s=j in equation (17) and after simplification

H ( j ) = 1 RG R G 2 + j + CL L C

(18)

Apply modulus on both side and equate to , we get

1 2 = 1 RG 2 2 R G + + CL L C
2 2

(19)

After simplification, we get 3-dB bandwidth in Hz and is given as,

f3 db = 1 2
2 2 R 2 G 2 + 8 R + G L C L C 2 2

(20)

The above equation (20) is our proposed closed form bandwidth expression taking crosstalk noise voltage into consideration for distributed RLCG interconnects line. In Table 3, results are summarized for the 10mm length of interconnect at different operating frequencies when the values of source resistant RS and load capacitance CL are kept constant .
Frequency (GHz) 10 15 20 R (K) 1.2 1.2 1.2 L (nH) 2.7 2.7 2.7 C (pF) 2.4 2.4 2.4 G (mS) 1.5 2.25 3 BW (GHz) 3.27 3.64 3.97

Table-3 Bandwidth for different values Operating Frequencies

Conclusion
The first part of the proposed work discussed about an efficient and accurate interconnect delay metric based on Gamma function for high speed VLSI RC global interconnects. In the second part of the proposed work, a brief analytical model is presented for calculating the delay and power for the RLC interconnects. The last part of the work proposed a distributed RLCG transmission line model of interconnects using difference model approach.

Future Prospects
Future integrated circuits design will be driven by interconnect performance, not transistors performance. New interconnect technologies, such as copper and lowtemperature interconnect, may introduce new problems. Alternative solutions such as on-chip optical interconnects have been proposed in order to avoid the problems associated with global on-chip wires altogether.

Publications
Rajib Kar, Vikas Maheshwari, A.K. Mal, A.K. Bhattacharjee, Delay Analysis for On-Chip VLSI Interconnect using Gamma Distribution Function, International Journal of Computer Application (IJCA). Vol. 1, No. 3, Article 11, pp. 77-80, 2010, Foundation of Computer Science (FCA) Press Rajib Kar, Vikas Maheshwari, A.K. Mal, A.K. Bhattacharjee, A Model for Slew Evaluation for On-Chip RC Interconnects using Gamma Distribution Function, International Journal of Computer Application (IJCA).Vol. 1, No. 10, Article 13, pp. 88-93. 2010, Foundation of Computer Science (FCA) Press. Rajib Kar, Vikas Maheshwari, Md. Maqbool, A.K.Mal, A.K.Bhattacharjee , An Explicit Model of Delay and Slew Metric for On-Chip VLSI RC Interconnects for Ramp Inputs using Gamma Distribution Function, International Journal of Recent Trends in Engineering, Academy Publisher, Finland. Vol. Issue. pp Rajib Kar, Md. Maqbool, Vikas Maheshwari, A.K. Mal, A.K. Bhattacharjee, PowerEstimation for On-Chip VLSI Distributed RLC Global Interconnect Using Model Order Reduction Technique, International Journal of Computer Application (IJCA). Vol. 1, No.14. pp. 96-101, 2010. Foundation of Computer Science (FCA) Press

Rajib Kar, Vikas Maheshwari, Md. Maqbool, A.K.Mal, A.K.Bhattacharjee, A Closed Form Modelling of cross-talk for Distributed RLCG On-Chip Interconnects Using Difference Model Approach, International Journal on Communication Technology (IJCT), India Rajib Kar, V. Maheshwari, Md. Maqbool, A.K.Mal, A.K.Bhattacharjee, An Explicit Coupling Aware Delay Model for Distributed On-Chip RLCG Interconnects Using Difference Model Approach, International Journal of Embedded Systems and Computer Engineering, Vol. 2 Issue.1.pp.39-42, Serial Publications, India Rajib Kar, Vikas Maheshwari, Md. Maqbool, Sangeeta Mandal , A.K.Mal, A.K.Bhattacharjee , Closed Form Bandwidth Expression for Distributed On-Chip RLCG Interconnects, IEEE International Conference on Advances in Computer Engineering (ACE 2010), pp. June 20-21, 2010 , Bangalore, INDIA Rajib Kar, V. Maheshwari, Aman Choudhary, Abhishek Singh, Ashis K. Mal, A. K. Bhattacharjee, Coupling Aware Power Estimation for Distributed On-Chip RLCG Interconnects Using Difference Model Approach, 2nd IEEE International Conference on Computing, Communication and Networking Technologies (ICCCN 2010), 29th 31st July, 2010 Karur, India.

References
Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis and Design, TMH Publication,2008 Intel website, http://www.intel/research/silicon/mooreslaw.htm, Sept. 2010 C. Bermond, B. Flechet, A. Fracy, V. Arnal, J. Torres, G LeCarval, G. Angenieux, and R. Salik. Impact of Dielectrics and Metals Properties on Electrical Performances of Advanced On-Chip Interconnect, Proceedings of the International Interconnect Technology Conference, 2002, p. 161163 T. Kikkawa, Current and Future Low-K Dielectrics for Cu Interconnects, Proceedings of International Electron Devices Meeting, 2000, p. 253-256. L. Peters, Pursuing the Perfect Low-K Dielectric, Semiconductor International, September 1998, p. 64-74. 98 Bibliography C. Cregut, G. Le Carval, J. Chilo. Low-K Dielectrics Influence on Crosstalk: Electromagnetic Analysis and Characterization, Proceedings of the International Interconnect Technology Conference, 1998, p. 59-61. R. Donaton, F. Iacopi, M Baklanov, D. Shamiryan, B. Coenegrachts, H. Struyf, M. Lepage, M Meuris, M. Van Hove, W. Gray, H. Meynen, D. DeRoest, S. Vanhaelemeersch, K. Maex, Physical and Electrical Characterization of Silsesquioxane-Based Ultra-Low k Dielectric Films, Proceedings of the International Interconnect Technology Conference, 2000, p. 93-95. S. Jang, Y. Chen, T. Chou, S. Lee, C. Chen, T. Tseng, B. Chen, S. Chang, C, Yu, and M. Liang. Advanced Cu/Low-k (k=2.2) Multilevel Interconnect for 0.10/0.07 mm Generation, Symposium on VLSI Technology Proceedings, 2002, p. 17-18. M. Anders, N. Rai, R. Krishnamurthy, S. Borkar. A Transition-Encoded Dynamic Bus Technique for High-Performance Interconnects, Symposium on VLSI Circuits Proceedings, 2002, p. 16-17.