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Code No: RR311903 Set No.

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III B.Tech I Semester Supplimentary Examinations, November 2007
MICROPROCESSORS AND INTERFACING
(Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. It is necessary to check the parity of the data byte in location 4000H:01FEH. If the
parity is even store 00H otherwise store 0FFH in location 5000H:1000H. Give the
instruction sequence for every addressing mode to achieve the above result. [16]

2. (a) Give the assembly language implementation of the following.


i. REPEAT - UNTIL
ii. FOR [4+4]
(b) Using DF flag and string instructions, write an assembly language program
to move a block of data of length ?N? from source to destination. Assume all
possible conditions. [8]

3. The I/O circuitry in an 8086 based system consists of five I/O devices with one
status signal for each device. Design the required hardware providing two address
locations to each device, one for status and other for data. In the range 0F00H to
0FOFH. Write an instruction sequence to test the status of each device and store
it. [16]

4. Explain why 8255 ports are divided into two groups? Discuss how these groups are
controlled in different modes of operation? Explain different control signals and
their associated pins for bi-directional I/O mode of operation? [4+6+6]

5. (a) What are the MODEM control lines? Explain the function of each line?
Discuss how MODEM is controlled using these lines with necessary sequence
of instructions?
(b) Discuss the Command instruction and Status register format of 8251? [8+8]

6. (a) What is the address map of interrupt address vector table? Explain how a
vector address is stored in this table? How many interrupts are serviced with
this table?
(b) What is the purpose of operational command words of 8259? Explain their
format and the use? [6+10]

7. In an SDK-86 kit 128KB SRAM and 64KB EPROM is provided on system and
provision for expansion of another 128KB SRAM is given. The on system SRAM
address starts from 00000H and that of EPROM ends with FFFFFH. The expansion
slot address map is from 80000H to 9FFFFH. The size of SRAM chip is 64KB.
EPROM chip size is 16KB. Give the complete memory interface and also the address
map for individual chips? [16]

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Code No: RR311903 Set No. 1
8. (a) Explain how 8051 is built around I/O ports? Discuss the function of each port
in detail?
(b) What are the addressing modes supported by 8051? Explain each addressing
mode with examples? [10+6]

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Code No: RR311903 Set No. 2
III B.Tech I Semester Supplimentary Examinations, November 2007
MICROPROCESSORS AND INTERFACING
(Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) What is the purpose of addressing mode? It is necessary to move a byte from
location 5000H:0102H to 5000H:0050H. Give all possible methods using 8086
addressing modes?
(b) Explain the use of Direction flag and Interrupt flag with examples? [10+6]
2. (a) Give the assembly language implementation of the following.
i. DO - WHILE
ii. FOR [4+4]
(b) What is a recursive procedure? Write a recursive procedure to calculate the
factorial of number N, where N is a two-digit Hex number? [8]
3. (a) What are the control signals useful for inter processor communication using
8086? What instruction set support is provided in 8086?
(b) Design an I/O port decoder that generate the following low-bank I/O strobes:
0010H, 0020H, 0030H, 0040H. [6+10]
4. Explain why 8255 ports are divided into two groups? Discuss how these groups are
controlled in different modes of operation? Explain different control signals and
their associated pins for bi-directional I/O mode of operation? [4+6+6]
5. (a) Draw the block diagram of 8251 and explain each block?
(b) Discuss the serial data transmission standards and their specifications?[10+6]
6. In an 8086 based system it is necessary to serve 64 IRQ’s from different initiators.
The allocated address space for 8259’s is from 0700h to 070FH. Give the complete
design by choosing the appropriate address locations in the above range? Give
the initialization sequence for all 8259’s with each IRQ activated in level triggered
mode and the starting interrupt is type 40H? [16]
7. In an SDK-86 kit 64KB SRAM and 32KB EPROM is provided on system and
provision for expansion of another 64KB SRAM is given. The on system SRAM
address map is from 00000H to 0FFFFH and that of EPROM is from F8000H to
FFFFFH. The expansion slot address map is from 80000H to 8FFFFH. The size
of SRAM chip is 32KB. EPROM chip size is 16KB. Give the complete memory
interface and also the address map for individual chips? [16]
8. (a) Explain the internal RAM organization of 8051? Discuss how switching be-
tween register banks is possible? Give a sequence of instructions to switch
from bank-0 to bank-2?

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Code No: RR311903 Set No. 2
(b) What is the use of SFR? List out the special function registers of 8051? [10+6]

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Code No: RR311903 Set No. 3
III B.Tech I Semester Supplimentary Examinations, November 2007
MICROPROCESSORS AND INTERFACING
(Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) What is the use of trap flag? Discuss how trap flag provides debugging feature?
(b) What is the difference between physical address, effective address and offset
address? Explain with example how physical address is generated? [7+9]

2. (a) What is a recursive procedure? Write a recursive procedure to calculate the


factorial of number N, where N is a two-digit Hex number?
(b) What are the loop instructions of 8086? Explain the use of DF flag in the
execution of string instructions. [9+7]

3. (a) Explain how an 8086 enters into Wait State? How many wait states can be
inserted in a machine cycle?
(b) What is the difference between system bus cycle and bus idle cycle? Draw the
timing diagram of bus idle cycle? [6+10]

4. Explain why 8255 ports are divided into two groups? Discuss how these groups are
controlled in different modes of operation? Explain different control signals and
their associated pins for bi-directional I/O mode of operation? [4+6+6]

5. (a) Distinguish between synchronous and asynchronous serial data transmission


techniques? Discuss the advantages and disadvantages? [8]
(b) Draw the block diagram of combination of FAX and Data Modem? Explain
each block? [4+4]

6. It is necessary to serve 18 interrupt requests using 8259’s. The address map for
the 8259’s is given from 0A00H to 0A0FH. Show the complete interface with 8086
system bus? These 18 interrupts are to be requested from interrupt type 040H on
words, with edge trigged mode and auto end of interrupt. Give the initialization
sequence for all 8259’s. [16]

7. (a) With a neat sketch explain the internal organization of SRAM chip? List out
the input and output pins? Discuss their function in a system? [8]
(b) Explain the following terms with reference to DRAM
i. Write cycle
ii. Access time
iii. Refresh
iv. Read cycle [4x2=8]

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Code No: RR311903 Set No. 3
8. (a) How does 8051 differentiate between the external and internal program mem-
ory?
(b) Explain how serial data communication is done with 8051 ports? [6+10]

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Code No: RR311903 Set No. 4
III B.Tech I Semester Supplimentary Examinations, November 2007
MICROPROCESSORS AND INTERFACING
(Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Draw the block diagram of 8086 and explain each block?
(b) Discuss the addressing modes provided by 8086 and explain with examples?
[8+8]

2. (a) Develop a far procedure declared as PUBLIC to convert a 4-digit BCD number
to its equivalent hex number?
(b) Develop a near procedure to find the GCD of two numbers of 2-digit Hex. Use
this procedure to find the GCD of three numbers? [8+8]

3. Describe the function of the following pins and their use in 8086 based system.

(a) DEN
(b) LOCK
(c) T EST
(d) READY [4 x 4 = 16]

4. It is necessary to initialize interrupt for mode 2 operation of port-A and mode


1 operation of port-B with the 8255 address map of 0800H to 0803H. Give the
complete hard ware design to interface 8255 to 8086 processor with this address
map? Write the instruction sequence for the initialization of 8255 in the above
modes? Give the instruction sequence to change the operation modes of port A
and Port B to mode 1? [16]

5. (a) A terminal is transmitting asynchronous serial data at 1200 bd. What is the
bit time? Assuming 8 data bits, a parity bit and 1 stop bit how long does it
take to transmit one character?
(b) Draw necessary circuit to interface 8251 to an 8086 based system with an
address 0C0H. Write the sequence of instructions to initialize 8251 for syn-
chronous transmission? (Assume the necessary data) [8+8]

6. (a) How many initialization command words are required for a single 8259 in an
8086 based system? Explain their format?
(b) Under what conditions type 0 interrupt is initiated? List out the instructions
that may cause type 0 interrupt? [10+6]

7. In an SDK-86 kit 64KB SRAM and 32KB EPROM is provided on system and
provision for expansion of another 64KB SRAM is given. The on system SRAM

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Code No: RR311903 Set No. 4
address map is from 00000H to 0FFFFH and that of EPROM is from F8000H to
FFFFFH. The expansion slot address map is from 80000H to 8FFFFH. The size
of SRAM chip is 32KB. EPROM chip size is 16KB. Give the complete memory
interface and also the address map for individual chips? [16]

8. Interface two 8255’s to 8051 with starting address of 0FFF0H? Show the hardware
design? Write the instruction sequence to initialize all ports of 8255?s as input
ports in mode 0. [16]

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