SAN JOSE STATE UNIVERSITY DEPARTMENT OF ELECTRICAL ENGINEERING EE 125: Analog CMOS Integrated Circuits Spring 2011 _____________________________________________________________________________________

Class Number: 44401 (Section 2) Class Days: TR Class Hours: 1800-1915 Room: IS 113 Instructor: Behzad Mohtashemi E-mail: behzadmohtashemi@yahoo.com Phone: Office: Part Time Office 3rd floor near EE office Office Hours: By appointment _____________________________________________________________________________________ Course Description: Analysis and design of analog CMOS integrated circuits. CMOS Transistor Analysis, Basic Building Blocks, Transconductance Amplifiers, Comparators, Operational Amplifiers, Voltage References and Bandgaps, Clocks and Oscillators, Linear Regulators, Low Dropout Regulators, and Switching Regulators( if time permits). Course Content: CMOS operation review Voltage and Current references Standard Analog building blocks /Design and Analysis Amplifiers / Design and Analysis Comparators Analog IC layout Regulators as time permits Course Objectives: This course introduces the principles of analog and mixed-signal IC design in CMOS technologies. Design and analysis of fundamental building blocks and basic analog circuits are covered to provide a foundation for more complicated and advanced designs, some of which we will touch on. Both practical design and layout issues will be emphasized. This will be a difficult and demanding course. One challenging project will be assigned to be worked on in groups.. Prerequisites: EE 124 (Electronic Design II) or consent of instructor. Required Text: CMOS Analog Circuit Design (2nd Edition), Phillip E. Allen & Douglas R. Holberg, Oxford University Press, February 2002. References (recommended, but not required): 1. The Art of Analog Layout, Alan Hastings & Roy Alan Hastings, December 15, 2000. 2. IC Mask Design: Essential Layout Techniques, Christopher Saint, Judy Saint, May 24, 2002. 3. CMOS Circuit Design Layout and Simulation, R. Jacob Baker, Harry W. Li, David E. Boyce, August 1997. 4. Design of Analog CMOS Integrated Circuits, Behzad Razavi, August 15, 2000. 5. Analog Integrated Circuit Design, David Johns & Ken Martin, November 15, 1996.

6. Grading & Evaluation: Homework: 10% Project(s) 30% Midterm 1: 15% Midterm II: 15% Final Exam: 30% Homework: There will be homework assignments that will be collected on a random basis. Homework will be returned when graded. Projects: There will be two projects for this class. The first project will be the design of building block such as a Voltage Reference or a Current Reference. The second project will be a system level design that will involve the basic building blocks. This can be the design of a Regulator, an Amplifier, a PLL, or anything that is of interest to the student. Exams: There will be two midterm exams that will cover appropriate material up to that point in time. The final exam will cover the remaining material and will be somewhat comprehensive, accounting for the extra weight of an additional 15%. All exams will be CLOSED BOOK, except for one sheet (both sides may be used) of notes and formulas, and a calculator. Rapidograph pens are allowed as well as programmable calculators, but I must be able to see how you derived your answers. Grading will be a meaningful combination of absolute Distribution in TABLE A: A 93 100% A- 90 93% B+ 87 90% B 83 87% B- 80 83% C+ 77 80% C 73 77% C- 70 73% D+ 67 70% D 63 67% D- 60 63% F 0 60% TABLE A

Usually, missing an in-class examination or assignment due date will result in a grade of zero (no credit). The only exceptions are a documented illness/injury or a significant personal event. When possible, arrangements must be made before the assigned date. . Final Exam: Date: Thursday, May 19, 2011. Time: 1715 1930. Location: IS 113. For detailed information, see course outline appended below. My intellectual property history is appended at the end of this document as an additional reference for specialized circuits discussed in the course.

University, College, or Department Policy Information: Academic Integrity Statement (from Office of Judicial Affairs): Your own commitment to learn, as evidenced by your enrollment at San Jose State University, and the Universitys Academic Integrity Policy requires you to be honest in all your academic course work. Faculty members are required to report all infractions to the Office of Judicial Affairs. The policy on academic integrity can be found at http://www2.sjsu.edu/senate/S04-12.pdf. Campus Policy in compliance with the Americans with Disabilities Act: If you need course adaptations or accommodations because of disability, of if you need special arrangements in case the building must be evacuated, please make an appointment with me as soon as possible, or see me during office hours. Presidential Directive 93-03 requires that students with disabilities requesting accommodations must register with DRC to establish a record of their disability.

EE 125: Analog CMOS Integrated Circuits Spring 2011 Syllabus Note: Reading assignments and dates of exams are subject to change with fair notice. WEEK 1 2 DATE R. 1/27 T. 2/1 R.2/3 T. 2/8 3 R. 2/10 Introduction Ch. 3: CH. 3: Ch. 4: Ch. 4: Basic MOSFET Device Characteristics Basic MOSFET Device Characteristics Analog CMOS Subcircuits Analog CMOS Subcircuits 4.1-4,5,6,7,8 4.3-1,2,3,4,5,6,7 4.4-1 4.5-2,4,5,6 HW will be assigned HW will be assigned TOPIC ASSIGNMENT

T. 2/15 4 R. 2/17

Ch. 5: Ch. 5: Ch.6:

CMOS Amplifiers CMOS Amplifiers CMOS Operational Amplifiers

T. 2/22 5 R. 2/24 T. 3/1 R. 3/3 T. 3/8 7 R. 3/10 Ch.6: CMOS Operational Amplifiers

HW will be assigned

HW will be assigned HW will be assigned HW will be assigned

Special Topic: Voltage and Current References Special Topic: Voltage and Current References

Midterm 1
Ch.7: High-Performance CMOS Op Amps HW will be assigned

WEEK

DATE T. 3/15 Ch.7:

TOPIC High-Performance CMOS Op Amps

ASSIGNMENT HW will be assigned

8 R. 3/17 Ch.7: High-Performance CMOS Op Amps Multistage Amplifier Design and Compensation HW will be assigned HW will be assigned

T. 3/22 9 R. 3/24 T. 3/29 10 R. 3/31 11 12 13 14 15 16 17 18 T. 4/5 R. 4/7 T. 4/12 R. 4/14 T. 4/19 R. 4/21 T. 4/26 R. 4/28 T. 5/3 R. 5/5 T. 5/10 R. 5/12 T. 5/17 T. 5/19

Special Topic:

Project 1Presentation.
Spring Break Spring Break Special Topic: Special Topic: Ch.8: Ch.8: Multistage Amplifier Design and Compensation Multistage Amplifier Design and Compensation HW will be assigned HW will be assigned HW will be assigned HW will be assigned

Comparators Comparators

Midterm 2
Special Topic: Special Topic: Special Topic: Special Topic: Special Topic: Special Topics: Special Topic: Clocks and Oscillators An Approach to System Design Linear Regulators Linear Regulators Power Amplifiers Switching Regulators Switching Regulators HW will be assigned HW will be assigned HW will be assigned HW will be assigned HW will be assigned HW will be assigned HW will be assigned

Project 2Presentation.
FINAL EXAMINATION: 5:15 - 7:30pm