NFC Institute of Engineering and Technological Training Multan Pakistan

Lab Manual VLSI Design EE-405

List of Experiments
S. No.
1 2 3 4 5 6 7 8 9 10 11 12 DC Analysis of CMOS inverter using SPICE Transient Analysis of CMOS inverter using SPICE Power Dissipation of CMOS inverter using SPICE DC Analysis of NAND and NOR using SPICE Simulating Pseudo-NMOS implementations using SPICE Simulating Symmetric CMOS implementations using SPICE Simulating BiCMOS Driver circuits using SPICE Investigating Interconnect delays for CMOS implementations using SPICE Using Verilog for switch, gate and Behavioral Modeling Simulating propagation delays using Switch Level modeling of Verilog HDL Combinational Logic Design using Gate Level Modeling of Verilog HDL and Xilinx Spartan-3 FPGA Combinational & Sequential Logic Design using Data Flow Modeling of Verilog HDL and Xilinx Spartan-3 FPGA 13 Combinational & Sequential Logic Design using Behavioral Modeling of Verilog HDL and Xilinx Spartan-3 FPGA 14 15 16 Driving on-board displays of Xilinx Spartan-3 FPGA using Behavioral Modeling of Verilog HDL Utilizing on-board 50 MHz clock source of Xilinx Spartan-3 FPGA using Behavioral modeling of Verilog HDL Utilizing on-board Serial and PS/2 ports of Xilinx Spartan-3 FPGA using Behavioral modeling of Verilog HDL

Experiment Name

Experiment 1
Objective: Apparatus: Circuit Diagram:
DC Analysis of CMOS inverter using SPICE Desktop PC, 5SPICE Software

Theory:
The CMOS inverter gives the basis for calculating the electrical characteristics of logic gates. The input voltage determines the conduction satiates of the two FETs. This produces the output voltage of the gate. A DC analysis determines output voltage for a given input voltage. In this type of calculation it is assumed that input is changed very slowly and the output is allowed to stabilize before a measurement is made. A DC analysis provides a direct mapping of the input to the output, which in turn tells us the voltage ranges that define Boolean logic 0 and logic 1 values. DC characteristics of inverter are portrayed in the voltage transfer characteristics (VTC), which is a plot of output voltage versus varying input voltage. A sample VTC is given as under:

VOH

VOL

NMH=VOH-VIH NML=VIL-VOL

VIH

VM

VIL

Procedure:
1. Draw the circuit in 5 SPICE using the drag and place menu available. 2. For the both nMOS and pMOS use the Level 3 electrical device models present in library with the name CMOSN and CMOSP. 3. Apply two test point at input and output respectively 4. Set the source to DC analysis by setting input to ramp up from 0 to 5V. 5. Start a new DC analysis in the Analyze menu. 6. Vary geometrical parameters Length and Width of both nMOS and pMOS to obtain a number of VTCs

Basic SPICE Listing:

Vdd Va Mn Mp .dc vdd a y1 y1 Va gnd gnd a a 0 gnd vdd 5 NMOS PMOS 0.1 W=5 W=30 L=0.5 L=0.5

.MODEL CMOSP PMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U +TPG=-1 VTO=-0.9056 DELTA=1.5200E+00 LD=2.2000E-08 KP=2.9352E-05 +UO=180.2 THETA=1.2480E-01 RSH=1.0470E+02 GAMMA=0.4863 +NSUB=1.8900E+16 NFS=3.46E+12 VMAX=3.7320E+05 ETA=1.6410E-01 +KAPPA=9.6940E+00 CGDO=5.3752E-11 CGSO=5.3752E-11 +CGBO=3.3650E-10 CJ=4.8447E-04 MJ=0.5027 CJSW=1.6457E-10 +MJSW=0.217168 PB=0.850000 .MODEL CMOSN NMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U +TPG=1 VTO=0.7860 DELTA=6.9670E-01 LD=1.6470E-07 KP=9.6379E-05 +UO=591.7 THETA=8.1220E-02 RSH=8.5450E+01 GAMMA=0.5863 +NSUB=2.7470E+16 NFS=1.98E+12 VMAX=1.7330E+05 ETA=4.3680E-02 +KAPPA=1.3960E-01 CGDO=4.0241E-10 CGSO=4.0241E-10 +CGBO=3.6144E-10 CJ=3.8541E-04 MJ=1.1854 CJSW=1.3940E-10 +MJSW=0.125195 PB=0.800000

Observations:
Sr. No. 1 2 3 4 5 Aspect Ratio 10 20 30 40 50 VIL VOL VIH VOH NML NMH VM VTC
Please attach Please attach Please attach Please attach Please attach

Comments/ Notes:
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Experiment 2
Objective: Apparatus: Circuit Diagram:
Transient Analysis of CMOS inverter using SPICE Desktop PC, 5SPICE Software

Theory:
High speed digital system design is based on the ability to perform calculations very quickly. This requires that logic gates introduce a minimum amount of time delay when the input changes. Designing fast logic circuits is one of the most challenging aspects of VLSI design. Rise and Fall Time: While performing transient analysis, a step like input voltage (abruptly changing between logic 0 and logic 1) is applied to the inverter. The output waveform reacts to the input but the output voltage cant change all of a sudden. The output 1-0 transition introduces a fall time delay tf, while the 0-1 delay is described by a rise time delay tr. Both delays are due to parasitic capacitances of the transistors.

90% 90%

10%

10%

tr

tf

Propagation Delay: The propagation delay time is often used to estimate the reaction delay time from input to output. When we use step like input voltage, the propagation delay is denoted by the simple average of the two time intervals tpr and tpf tp=

50% 50%

tpr

tpf

Procedure:
1. Draw the circuit in 5 SPICE using the drag and place menu available. 2. For both nMOS and pMOS FETs, use the Level 3 electrical device models present in library with the name CMOSN and CMOSP. 3. Apply two test point at input and output respectively 4. Set the source to Transient analysis by setting input with appropriate duty cycle and rise & fall time 5. Start a new Transient analysis in the Analyze menu. 6. Vary geometrical parameters of nMOS and pMOS to obtain a number of readings

Basic SPICE Listing:

Vdd Va Mn Mp vdd a y1 y1 gnd gnd a a gnd vdd NMOS PMOS W=5 W=30 L=0.5 L=0.5

.tran 20ps 800ps .plot v(in) v(out) .MODEL CMOSP PMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U +TPG=-1 VTO=-0.9056 DELTA=1.5200E+00 LD=2.2000E-08 KP=2.9352E-05 +UO=180.2 THETA=1.2480E-01 RSH=1.0470E+02 GAMMA=0.4863 +NSUB=1.8900E+16 NFS=3.46E+12 VMAX=3.7320E+05 ETA=1.6410E-01 +KAPPA=9.6940E+00 CGDO=5.3752E-11 CGSO=5.3752E-11 +CGBO=3.3650E-10 CJ=4.8447E-04 MJ=0.5027 CJSW=1.6457E-10 +MJSW=0.217168 PB=0.850000 .MODEL CMOSN NMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U +TPG=1 VTO=0.7860 DELTA=6.9670E-01 LD=1.6470E-07 KP=9.6379E-05 +UO=591.7 THETA=8.1220E-02 RSH=8.5450E+01 GAMMA=0.5863 +NSUB=2.7470E+16 NFS=1.98E+12 VMAX=1.7330E+05 ETA=4.3680E-02 +KAPPA=1.3960E-01 CGDO=4.0241E-10 CGSO=4.0241E-10 +CGBO=3.6144E-10 CJ=3.8541E-04 MJ=1.1854 CJSW=1.3940E-10 +MJSW=0.125195 PB=0.800000

Observations:
Sr. No. Aspect Ratio 1 2 3 4 5 10 20 30 40 50
Please attach Please attach Please attach Please attach Please attach

tr

tf

tpr

tpf

tp

Plot

Comments/ Notes:
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Experiment 3
Objective: Apparatus: Circuit Diagram:
Power Dissipation of a CMOS inverter using SPICE Desktop PC, 5SPICE Software

Theory:
An important characteristic of CMOS integrated circuits is the power dissipated by a particular design technique. Generally, the current flows from the power supply to ground; power dissipation (also called Static Power) is as under: P=VDDIDD Since the value of the voltage supply VDD is assumed to be a constant, we can find the value of P by studying the nature of the current flow. Static Power can be calculated by examining the voltage transfer curve reproduced in Figure below. When the input voltage is stable at logic low, the nMOS is off and there is no direct current flow path between VDD and ground. Ideally, the DC current flow for this case would be IDD=0, but in a realistic circuit, small leakage currents exist. The value is denoted as IDDQ and is called quiescent leakage current. When Vin is switched, the current flow reaches a peak value Ipeak at VM. However, when the input reaches a logic1 voltage, then the pMOS turns off, once again preventing a direct current flow path. If we assume that the inputs are in stable 0 or 1 states as in the idle system, the DC power dissipation is given by PDC=VDDIDDQ

The leakage current IDDQ is usually quite small, with a typical value of the order of a Pico ampere per gate. The value of PDC is quite small. This consideration was a major factor in the move to CMOS in the mid 1990s.

IDD

Ipeak

Mn Off IDDQ

Mp Off

VM

Vin

Procedure:
1. Draw the circuit in 5 SPICE using the drag and place menu available. 2. For both nMOS and pMOS FETs, use the Level 3 electrical device models present in library with the name CMOSN and CMOSP. 3. Apply a current test point between the two transistors 4. Set the source to DC analysis by setting input to vary from 0-VDD with appropriate step size 5. Start a new DC analysis in the Analyze menu. 6. Vary geometrical parameters of nMOS and pMOS to obtain a number of readings

Basic SPICE Listing:

Vdd Va Mn Mp vdd a y1 y1 gnd gnd a a gnd vdd NMOS PMOS W=5 W=30 L=0.5 L=0.5

.DC Vdd 0 5 0.1 .MODEL CMOSP PMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U +TPG=-1 VTO=-0.9056 DELTA=1.5200E+00 LD=2.2000E-08 KP=2.9352E-05 +UO=180.2 THETA=1.2480E-01 RSH=1.0470E+02 GAMMA=0.4863 +NSUB=1.8900E+16 NFS=3.46E+12 VMAX=3.7320E+05 ETA=1.6410E-01 +KAPPA=9.6940E+00 CGDO=5.3752E-11 CGSO=5.3752E-11 +CGBO=3.3650E-10 CJ=4.8447E-04 MJ=0.5027 CJSW=1.6457E-10 +MJSW=0.217168 PB=0.850000 .MODEL CMOSN NMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U

+TPG=1 VTO=0.7860 DELTA=6.9670E-01 LD=1.6470E-07 KP=9.6379E-05 +UO=591.7 THETA=8.1220E-02 RSH=8.5450E+01 GAMMA=0.5863 +NSUB=2.7470E+16 NFS=1.98E+12 VMAX=1.7330E+05 ETA=4.3680E-02 +KAPPA=1.3960E-01 CGDO=4.0241E-10 CGSO=4.0241E-10 +CGBO=3.6144E-10 CJ=3.8541E-04 MJ=1.1854 CJSW=1.3940E-10 +MJSW=0.125195 PB=0.800000

Observations:
Sr. No. Aspect Ratio 1 2 3 4 5 10 20 30 40 50
Please attach Please attach Please attach Please attach Please attach

VM

IDDQ

Ipeak

VDD

Power

Plot

Comments/ Notes:
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Experiment 4
Objective: Apparatus: Circuit Diagram:
DC Analysis of NAND2 and NOR2 using SPICE Desktop PC, 5SPICE Software

Theory:
The basic calculations introduced for the inverter circuit can be used to analyze NAND and NOR gates. The presence of two independent inputs implies that more than one VTC curve is needed to describe the circuit. Suppose that we look for the transitions where Vout is initially high and then falls to 0V when inputs are changed. Figure below summarizes three possible starting pints that can lead to this situation. In case (i), both VA and VB are at 0V and then switched to the bottom line condition where VA=VB=VDD such that Vout=0V. Since both inputs are increased at the same time, this describes the case for simultaneous input switching. The other two possibilities (ii) and (iii) describe cases where only a single input is changed. For example, in (ii) VA is changed from 0V to VDD while VB is held constant at VDD. These three possibilities lead to three distinct transitions shown in plots below. This shows that the simultaneous switching case is pushed to right compared to the single-switched input cases. DC characteristics of NAND are portrayed in the voltage transfer characteristics (VTC), which is a plot of output voltage versus varying input voltages of case (i), (ii) and (iii) given as under:

VA (i) (ii) (iii) 0 0 VDD VDD

VB 0 VDD 0 VDD

Vout VDD VDD VDD 0

Vout (iii) (ii) (i) Simultaneous Switching

Vin

Procedure:
1. Draw the circuit in 5 SPICE using the drag and place menu available. 2. For the both nMOS and pMOS use the Level 3 electrical device models present in library with the name CMOSN and CMOSP. 3. Apply two test point at input and output respectively 4. Set the source to DC analysis by setting input to ramp up from 0 to 5V. 5. Start a new DC analysis in the Analyze menu. 6. Vary geometrical parameters Length and Width of both nMOS and pMOS to obtain a number of VTCs for each case i.e. (i), (ii) and (iii)

Basic SPICE Listing:

Vdd Va Mp1 Mp2 Mn1 Mn2 vdd a y1 y1 y1 w1 gnd gnd a b a b vdd vdd w1 gnd PMOS PMOS NMOS NMOS W=30 W=30 W=5 W=5 L=0.5 L=0.5 L=0.5 L=0.5

.dc

Va

0.1

.MODEL CMOSP PMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U +TPG=-1 VTO=-0.9056 DELTA=1.5200E+00 LD=2.2000E-08 KP=2.9352E-05 +UO=180.2 THETA=1.2480E-01 RSH=1.0470E+02 GAMMA=0.4863 +NSUB=1.8900E+16 NFS=3.46E+12 VMAX=3.7320E+05 ETA=1.6410E-01 +KAPPA=9.6940E+00 CGDO=5.3752E-11 CGSO=5.3752E-11 +CGBO=3.3650E-10 CJ=4.8447E-04 MJ=0.5027 CJSW=1.6457E-10 +MJSW=0.217168 PB=0.850000 .MODEL CMOSN NMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U +TPG=1 VTO=0.7860 DELTA=6.9670E-01 LD=1.6470E-07 KP=9.6379E-05 +UO=591.7 THETA=8.1220E-02 RSH=8.5450E+01 GAMMA=0.5863 +NSUB=2.7470E+16 NFS=1.98E+12 VMAX=1.7330E+05 ETA=4.3680E-02 +KAPPA=1.3960E-01 CGDO=4.0241E-10 CGSO=4.0241E-10 +CGBO=3.6144E-10 CJ=3.8541E-04 MJ=1.1854 CJSW=1.3940E-10 +MJSW=0.125195 PB=0.800000

Observations:
Sr. No. Aspect Ratio VIL VOL VIH VOH NML NMH VM Case (i) 1 2 3 4 5 10 20 30 40 50
Please attach

VTC Case (ii) Case (iii)

Please attach

Please attach

Please attach

Please attach

Lab Assignment:
Please repeat the experiment for NOR2 (Schematic, Truth Table, SPICE Listing and Observations)

Comments/ Notes:
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Experiment 5
Objective: Apparatus: Circuit Diagram:
Pseudo-NMOS NOT Pseudo-NMOS NOR2 Pseudo-NMOS NAND2

Simulating Pseudo-NMOS implementations using SPICE Desktop PC, 5SPICE Software

Theory:
Prior to the widespread adoption of CMOS, single FET polarity logic circuits were dominant. Many microprocessors were designed using nFET-only circuits in an nMOS technology. Although nMOS was abandoned due to high DC power dissipation, yet some of the main ideas are used in CMOS technology today. Adding a single pMOS to otherwise nMOS-only circuit produces a logic family that is called pseudo-NMOS. Pseudo nMOS logic uses fewer transistors because only the nMOS logic block is needed to create the logic. For N inputs, a pseudo nMOS logic gate requires (N+1) FETs. In conventional CMOS, the pMOS group is added to reduce the DC power dissipation, but the logic is surplus. Standard N-input CMOS gates use 2N transistors on the other hand. As it can be observed in the diagram below, the gate of pMOS is always at logic low which puts VSGp=VDD and hence pMOS acts as a pull-up device that tries to pull the output to the power supply voltage VDD. Logic is implemented by nMOS array only which acts as a large switch between ground and the output. If the nMOS switch is closed, the array tries to pull the output down to ground. Since pMOS is always on, V OL can never reach to a value equal to 0V. It is tempting to use pseudo nMOS circuits to reduce the FET count and area. However, this logic family is more complicated because the relative sizes of the transistors set the numerical value of V OL and care must be taken to insure that VOL is small enough to be an electronic logic low voltage.

The value of VOL thus depends on the ratio (n/p)>1. Increasing the device size ratio decreases the output low voltage. Because of his characteristic, pseudo nMOS is a type of ratioed logic where the relative device sizes set VOL or VOH. The choice of aspect ratio is critical to this design style. It is important to note that when Vin=VDD, a current flow path is established from VDD to ground, leading to a large DC power dissipation. This is another factor that may limit the use of pseudo-nMOS circuits. The problems associated with pseudo nMOS limit its usage to situations where the layout problems are critical or some special switching situations where it yields simpler circuitry.
VDD VSGp + Pull-up Load Output

nMOS Logic Array

Pull-down

Procedure:
1. Draw all the three circuits (NOT, NOR2 & NAND2) one by one in 5 SPICE using the drag and place menu available. 2. For both nMOS and pMOS FETs, use the Level 3 electrical device models present in library with the name CMOSN and CMOSP. 3. Apply a voltage test point at the output to note VOL 4. Apply ground to the gate of pMOS and VDD to the gate of nMOS 5. Start a new DC Bias analysis in the Analyze menu. 6. Vary n/p by varying geometrical parameters (W/L)n and (W/L)p of nMOS and pMOS to obtain a number of readings and finally settling to an acceptable value of VOL

Basic SPICE Listing:

Vdd Va Mp Mn vdd a y1 y1 gnd gnd gnd vdd vdd gnd PMOS NMOS W=30 W=5 L=0.5 L=0.5

.DC Vdd 5 .MODEL CMOSP PMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U +TPG=-1 VTO=-0.9056 DELTA=1.5200E+00 LD=2.2000E-08 KP=2.9352E-05 +UO=180.2 THETA=1.2480E-01 RSH=1.0470E+02 GAMMA=0.4863

+NSUB=1.8900E+16 NFS=3.46E+12 VMAX=3.7320E+05 ETA=1.6410E-01 +KAPPA=9.6940E+00 CGDO=5.3752E-11 CGSO=5.3752E-11 +CGBO=3.3650E-10 CJ=4.8447E-04 MJ=0.5027 CJSW=1.6457E-10 +MJSW=0.217168 PB=0.850000 .MODEL CMOSN NMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U +TPG=1 VTO=0.7860 DELTA=6.9670E-01 LD=1.6470E-07 KP=9.6379E-05 +UO=591.7 THETA=8.1220E-02 RSH=8.5450E+01 GAMMA=0.5863 +NSUB=2.7470E+16 NFS=1.98E+12 VMAX=1.7330E+05 ETA=4.3680E-02 +KAPPA=1.3960E-01 CGDO=4.0241E-10 CGSO=4.0241E-10 +CGBO=3.6144E-10 CJ=3.8541E-04 MJ=1.1854 CJSW=1.3940E-10 +MJSW=0.125195 PB=0.800000

Observations:
Pseudo-NMOS NOT Sr. No. VDD (W/L)n (W/L)p VOL VOL (smallest)
( ) ( )

at VOL (smallest)

1 2 3 4 5

Pseudo-NMOS NOR2 Sr. No. VDD (W/L)n (W/L)p VOL VOL (smallest)
( ) ( )

at VOL (smallest)

1 2 3 4 5 Pseudo-NMOS NAND2 Sr. No. VDD (W/L)n (W/L)p VOL VOL (smallest)
( ) ( )

at VOL (smallest)

1 2 3 4 5

Comments/ Notes:
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Experiment 6
Objective: Apparatus: Circuit Diagram:
NOT NOR2 NAND2

Simulating Symmetric CMOS implementations using SPICE Desktop PC, 5SPICE Software

Theory:
As studied in elementary physics, we know that the mobility of electronics is greater than the mobility of holes, therefore resistance of a pMOS (majority carriers are holes) is greater than the resistance of an nMOS (majority carriers are electronics) for symmetric geometric drawings. Further, resistance of MOS can be adjusted by changing the channel width W. To design pMOS and nMOS with same electrical resistance, we use an aspect ratio of (W/L)p > (W/L)n that compensates for the differences in mobilities. This is accomplished by selecting the following: ( ) ( )

A symmetric inverter VTC is one that has equal 0 and 1 input voltage ranges. This can be achieved by choosing VM=0.5VDD. This allows us to compute the transistor sizes for this particular choice of VM. Aspect ratio plays the key role; its adjustment will help obtaining our desired value of VM. In general increasing the width of pMOS decreases VM; electrically symmetric design can be achieved by adjusting Width of pMOS will we achieve VM=0.5VDD. A similar approach can be used to calculate device size ratio for CMOS based NAND2 and NOR2 implementations, considering only the case of simultaneous switching. In each case, both nMOS will have the same aspect ratio which may be different from the aspect ratio of both pMOS. In case of NAND2 both pMOS (high resistance devices) are in parallel, therefore difference between the aspect ratio of all four transistors

should not be large. However, in case of NOR2, difference will be large enough as both pMOS (high resistance devices) are in series and both low resistance devices i.e. nMOS are in parallel.

Procedure:
1. Draw all the three circuits (NOT, NOR2 & NAND2) one by one in 5 SPICE using the drag and place menu available. 2. For both nMOS and pMOS FETs, use the Level 3 electrical device models present in library with the name CMOSN and CMOSP. 3. Apply a voltage test point at the output and one at input to obtain a VTC 4. Put the circuit to DC Analysis and for simultaneous switching in case of NAND2 and NOR2. 5. Start a new DC analysis in the Analyze menu. 6. Vary geometrical parameters (W/L)n and (W/L)p of nMOS and pMOS to obtain a number of readings and finally settling to desired value of VM.

Basic SPICE Listing:

Vdd Va Mp Mn vdd a y1 y1 gnd gnd Va va vdd gnd PMOS NMOS W=30 W=5 L=0.5 L=0.5

.DC Va 0 5 0.1 .MODEL CMOSP PMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U +TPG=-1 VTO=-0.9056 DELTA=1.5200E+00 LD=2.2000E-08 KP=2.9352E-05 +UO=180.2 THETA=1.2480E-01 RSH=1.0470E+02 GAMMA=0.4863 +NSUB=1.8900E+16 NFS=3.46E+12 VMAX=3.7320E+05 ETA=1.6410E-01 +KAPPA=9.6940E+00 CGDO=5.3752E-11 CGSO=5.3752E-11 +CGBO=3.3650E-10 CJ=4.8447E-04 MJ=0.5027 CJSW=1.6457E-10 +MJSW=0.217168 PB=0.850000 .MODEL CMOSN NMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U +TPG=1 VTO=0.7860 DELTA=6.9670E-01 LD=1.6470E-07 KP=9.6379E-05 +UO=591.7 THETA=8.1220E-02 RSH=8.5450E+01 GAMMA=0.5863 +NSUB=2.7470E+16 NFS=1.98E+12 VMAX=1.7330E+05 ETA=4.3680E-02 +KAPPA=1.3960E-01 CGDO=4.0241E-10 CGSO=4.0241E-10 +CGBO=3.6144E-10 CJ=3.8541E-04 MJ=1.1854 CJSW=1.3940E-10 +MJSW=0.125195 PB=0.800000

Observations:
NOT Sr. No. (W/L)n (W/L)p VM
( ) ( )

Plot at VM = 0.5VDD Please Attach Please Attach Please Attach Please Attach Please Attach

1 2 3 4 5

NOR2 Sr. No. (W/L)n (W/L)p VM

( ) ( )

Plot at VM = 0.5VDD Please Attach Please Attach Please Attach Please Attach Please Attach

1 2 3 4 5

NAND2 Sr. No. (W/L)n (W/L)p VM

( ) ( )

Plot at VM = 0.5VDD Please Attach Please Attach Please Attach Please Attach Please Attach

1 2 3 4 5

Comments/ Notes:
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Experiment 7
Objective: Apparatus: Circuit Diagram:
BiCMOS NOT BiCMOS NAND2 BiCMOS NOR2

Simulating BiCMOS Drivers using SPICE Desktop PC, 5SPICE Software

Theory:
BiCMOS is a modified CMOS technology that includes bipolar junction transistors as circuit elements. In digital design, BiCMOS stages are used to drive high-capacitance lines more efficiently than MOSFET-only circuits. BiCMOS processing is more expensive than standard CMOS, and bipolar transistors have an intrinsic voltage drop that can not be avoided making them undesirable for low voltage applications. BiCMOS circuits employ CMOS logic circuits that are connected to a bipolar output driver stage. The CMOS network is used to provide logic operations and drive the output bipolar transistors. Only one BJT is active at a time. Upper BJT provides the high output voltage lower BJT discharges the output capacitance and gives the low output state. The inverting circuit drawn below gives an example of the operational details. The NOT logic operation is performed by FETs Mp and Mn, even though they are separated from each other. The other two FETs M1 and M2 are used to provide paths to remove charge from the base terminals of Q1 and Q2, respectively. This speeds up the switching of the circuit, enhancing its use as an output driver.

VDD Mp Q1 M1 Vout Mn Cout Q2 Vin M2

Figure: A BiCMOS Inverter

In order to learn its operation, lets first consider the case where the input voltage is at a value of 0V. This turns Mp on, while M1 and Mn are off. Since Mp and M1 form an inverter, the base of Q1 is high at a voltage of VDD, and it goes active; the same voltage turns on M2, which grounds the base of Q2 and dries it into cutoff. The output high voltage VOH for this case can be calculated from the subcircuit shown below. Noting that Q1 will eventually enter saturation, we have VOH=VDD-VBE (sat) The subcircuit for the case where Vin=VDD is shown below. Now we see that Mp is off while M1and Mn are on. M1 connects the base of Q1 to ground, driving it into cutoff. This in turn shuts off M2 so that Q2 is biased by the output voltage feeding to the base. The output low voltage is seen to be: VOL=VBE(sat) The problem with this configuration is that the output logic swing is reduced from VDD by 2VBE(sat).
VDD Mp Q1 VBE
(sat)

Vout VDD Mn Cout Q2 VBE (sat)

Cout

Vout

Figure: VOH Circuit

Figure: VOL Circuit

Further, the same logic can be extended to implement BiCMOS NOR2 and NAND2. As it is obvious from the discussions above that a BiCMOS implementation is more complex compared to a CMOS implementation in general, therefore it will have a higher parasitic capacitance (due to more no. of transistors). This leads to an important conclusion: BiCMOS is only effective for larger values of load capacitance. A plot between propagation delay and load capacitance for both CMOS and BiCMOS shown below reveals that the propagation delay is pretty much relaxed for BiCMOS. The plots cross each other at a value called Cx beyond which BiCMOS is preferred over CMOS.

tp

CMOS

BiCMOS

Cx

CL

Procedure:
1. Draw all the three circuits (BiCMOS NOT, BiCMOS NAND2 & BiCMOS NOR2) one by one in 5 SPICE using the drag and place menu available. 2. For both nMOS and pMOS FETs, use the Level 3 electrical device models present in library with the name CMOSN and CMOSP. 3. Apply a voltage test point at the output and one at input to obtain a plots of Vin and Vout simultaneously 4. Put the circuit to Transient Analysis and for simultaneous switching in case of NAND2 and NOR2. 5. Start a new Transient analysis in the Analyze menu. 6. Vary Load Capacitance CL to obtain a number of readings for propagation delay and finally plot tp vs CL for each implementation in conjunction with its CMOS counterpart to determine Cx

Observations:
BiCMOS NOT S/ N 1 2 3 4 5
Cx BiCMOS NOT

CL

BiCMOS NOT

CMOS NOT

Cx

Plot

tpf

tpr

tp

tpf

tpr

tp
tp CMOS NOT

CL

BiCMOS NAND2 S/ N 1 2 3
BiCMOS NAND2

CL

BiCMOS NAND2

CMOS NAND2

Cx

Plot

tpf

tpr

tp

tpf

tpr

tp
tp CMOS NAND2

4 5
Cx CL

BiCMOS NOR2 S/ N 1 2 3 4 5
Cx BiCMOS NOR2

CL

BiCMOS NOR2

CMOS NOR2

Cx

Plot

tpf

tpr

tp

tpf

tpr

tp
tp CMOS NOR2

CL

Comments/ Notes:
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Experiment 8
Objective: Apparatus: Circuit Diagram:
L-Model Pi-Model T-Model Investigating Interconnect delays for CMOS implementations using SPICE Desktop PC, 5SPICE Software

Theory:
Logic gates communicate with each other by signal flow paths from one point to another. At the integrated circuit level, this is accomplished by using patterned metal lines as wires to conduct electrical current. These lines are generically referred to as interconnects. While this seems like a straightforward translation, the level of electric current flow is governed by the physical characteristics of the material and the dimensions of the line. This implies that the signal transfer speed is directly affected by the physical implementation of the wiring, making it a very important aspect of chip design. Resistance of an interconnect line can generally be represented as: ( )

A VLSI designer can not change the value of t or , as these are established by the manufacturing process. Because of this, it is useful to rewrite process related terms together and be given the name of sheet resistance Rs. Interconnect lines also exhibit the property of capacitance, which is the ability to store electric charge and energy. Capacitance exists between any two conducting bodies that are electrically separated. For the interconnect line, the conductor is isolated from the semiconductor substrate by an insulating layer of silicon dioxide glass. The capacitance depends upon the geometry of the line and can be written as: wl is the area of interconnect line. For now, it is sufficient to note that interconnect line exhibits both parasitic resistance (R line) and capacitance (Cline). Product of these two quantities give a value called time constant. In high-speed digital circuits, signals on an interconnect line are delayed by time constant, which places a limiting factor on the speed of the network. Long interconnect lines can either take form of a Pi or of a T. Both of these types can be modeled in SPICE using appropriate circuit elements. Pi and T models can also be simulated in cascade which is a lab exercise at the end of this experiment.

Vin
Voltage

Vout

Time
Figure: Delay exhibited by an Interconnect

Procedure:
1. 2. 3. 4. 5. 6. Draw all the three circuits (L-Model, Pi-Model and T-Model) one by one in 5 SPICE using the drag and place menu available. Set appropriate values for Cline and Rline. Apply one voltage test point at the output and one at input to obtain a plots of Vin and Vout simultaneously as shown in theory section above Set the source for Step at 0 under Transient Analysis Start a new Transient analysis in the Analyze menu. Vary Cline and Rline to model different scenarios in all three models and obtain various plots.

Basic SPICE Listing:

Vin R1 C1 in in out gnd out gnd pwl 2k 100f 0ps 0 100ps 0 150ps 1.8 800ps 1.8

.tran 20ps 800ps *transient analysis with a 20ps step size for 800 ps .plot v(in) v(out) .end

Observations:
L-Model S/ N R C tp Plots (Vin & Vout vs tp) 1 2 3 4 5 Please attach Please attach Please attach Please attach Please attach Plot (tp versus RC) Please attach

Pi-Model S/ N R C tp Plots (Vin versus Vout) 1 2 3 4 5 T-Model S/ N R C tp Plots (Vin versus Vout) 1 2 3 4 5 Please attach Please attach Please attach Please attach Please attach Plot (tp versus RC) Please attach Please attach Please attach Please attach Please attach Please attach Plot (tp versus RC) Please attach

Lab Assignment:
Please repeat the experiment for three stage cascades of all three models i.e. L, Pi and T.

Comments/ Notes:
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Experiment 9
Objective: Apparatus: Theory:
In the semiconductor and electronic design industry, Verilog is a hardware description language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction. It is also used in the verification of analog and mixed-signal circuits. Hardware description languages such as Verilog, differ from software programming languages because they include ways of describing the propagation of time and signal dependencies (sensitivity). The designers of Verilog wanted a language with syntax similar to the C programming language, which was already widely used in engineering software development. Verilog is case-sensitive, has a basic preprocessor (though less sophisticated than that of ANSI C/C++), and equivalent control flow keywords (if/else, for, while, case, etc.), and compatible operator precedence. Verilog provides the ability to design at a MOS-transistor level. Design at this level is becoming rare with the increasing complexity of circuits (millions of transistors) and with the availability of sophisticated CAD tools. Verilog HDL currently provides only digital design capability with logic values 0 1, x, z, and the drive strengths associated with them. There is no analog capability. Thus, in Verilog HDL, transistors are also known switches that either conduct or are open. Most digital design is now done at gate level or higher levels of abstraction. At gate level, the circuit is described in terms of gates (e.g., and, nand). Hardware design at this level is intuitive for a user with a basic knowledge of digital logic design because it is possible to see a one-to-one correspondence between the logic circuit diagram and the Verilog description. A logic circuit can be designed by use of logic gates. Verilog supports basic logic gates as predefined primitives. These primitives are instantiated like modules except that they are predefined in Verilog and do not need a module definition. All logic circuits can be designed by using basic gates. There are two classes of basic gates: and/or gates and buf/not gates. For small circuits, the gate-level modeling approach works very well because the number of gates is limited and the designer can instantiate and connect every gate individually. Also, gate- level modeling is very intuitive to a designer with a basic knowledge of digital logic design. However, in complex designs the number of gates is very large. Thus, designers can design more effectively if they concentrate on implementing the function at a level of abstraction higher than gate level. Dataflow modeling provides a powerful way to implement a design. Verilog allows a circuit to be designed in terms of the data flow between registers and how a design processes data rather than instantiation of individual gates. With gate densities on chips increasing rapidly, dataflow modeling has assumed great importance. No longer can companies devote engineering resources to handcrafting entire designs with gates. Currently, automated tools are used to create a gate-level circuit from a dataflow design description. This process is called logic synthesis. Dataflow modeling has become a popular design approach as logic synthesis tools have becomes sophisticated. This approach allows the designer to concentrate on optimizing the circuit in terms of data flow. For maximum flexibility in the design process, designers typically use a Verilog description style that combines the concepts of gate-level, data flow, and behavioral design. In the digital design community, the term RTL (Register Transfer Level) design is commonly used for a combination of dataflow modeling and behavioral modeling. With the increasing complexity of digital design, it has become vitally important to make wise design decisions early in a project. Designers need to be able to evaluate the tradeoffs of various architectures and algorithms before they decide on the optimum architecture and algorithm to implement in hardware. Thus, architectural evaluation takes place at an algorithmic level where the designers do not necessarily think in terms of logic gates or data flow but in terms of the algorithm they wish to implement in hardware. They are more concerned Using Verilog for Switch, Gate, Data Flow and Behavioral Modeling Desktop PC, Xilinx Software, Xilinx Spartan 3 kit

about the behavior of the algorithm and its performance. Only after the high-level architecture and algorithm are finalized, do designers start focusing on building the digital circuit to implement the algorithm. Verilog provides designers the ability to describe design functionality in an algorithmic manner. In other words, the designer describes the behavior of the circuit. Thus, behavioral modeling represents the circuit at a very high level of abstraction. Design at this level resembles C programming more than it resembles digital circuit design. Behavioral Verilog constructs are similar to C language constructs in many ways. Verilog is rich in behavioral constructs that provide the designer with a great amount of flexibility.

Procedure:
7. Make a new project in Xilinx software. 8. Apply all the modeling techniques one by one implementing AND, OR and NAND gates. 9. Connect the Spartan 3 kit to computer. 10. Burn the code on Spartan 3 ROM. 11. Reset the Spartan 3 kit. 12. Check the desired logic.

Comments/ Notes:
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Experiment 10
Objective: Apparatus: Theory:
Verilog provides various constructs to model switch-level circuits. Digital circuits at MOS-transistor level are described using these elements. Two types of MOS switches can be defined with the keywords nmos and pmos. MOS switch keywords nmos pmos Keyword nmos is used to model NMOS transistors; keyword pmos is used to model PMOS transistors. Simulating propagation delays using Switch Level modeling of Verilog HDL Desktop PC, Xilinx Software

nmos n1(out, data, control); //instantiate a nmos switch pmos p1(out, data, control); //instantiate a pmos switch Since switches are Verilog primitives, like logic gates, the name of the instance is optional. Therefore, it is acceptable to instantiate a switch without assigning an instance name. CMOS switches are declared with the keyword cmos.

The power (Vdd, logic 1) and Ground (Vss, logic 0) sources are needed when transistor level circuits are designed. Power and ground sources are defined with keywords supply1 and supply0. Sources of type supply1 are equivalent to Vdd in circuits and place a logical 1 on a net. Sources of the type supply0 are equivalent to ground or Vss and place a logical 0 on a net. Both supply1 and supply0 place logical 1 and 0 continuously on nets throughout the simulation. supply1 vdd; supply0 gnd;

Procedure:
1. Design a NOT gate and 2x1 Multiplexer. 2. Make a new project in Xilinx software.

3. Apply switch level modeling to implement the above designs. 4. Using ModelSim simulator note the propagation delays.

Comments/ Notes:
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Experiment 11
Objective: Apparatus: Theory:
And/or gates have one scalar output and multiple scalar inputs. The first terminal in the list of gate terminals is an output and the other terminals are inputs. The output of a gate is evaluated as soon as one of the inputs changes. The and/or gates available in Verilog are shown below. and nand or nor xor xnor Combinational Logic Design using Gate Level Modeling of Verilog HDL and Xilinx Spartan-3 FPGA Desktop PC, Xilinx Software, Xilinx Spartan 3 kit

The truth tables for these gates define how outputs for the gates are computed from the inputs.

Procedure:
1. 2. 3. 4. 5. 6. 7. Design a two and four bit full adder. Make a new project in Xilinx software. Apply gate level modeling to implement the above design. Connect the Spartan 3 kit to computer. Burn the code on Spartan 3 ROM. Reset the Spartan 3 kit. Check the desired logic.

Comments/ Notes:
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Experiment 12
Objective: Apparatus: Theory:
A continuous assignment is the most basic statement in dataflow modeling, used to drive a value onto a net. This assignment replaces gates in the description of the circuit and describes the circuit at a higher level of abstraction. The assignment statement starts with the keyword assign. The syntax of an assign statement is as follows. continuous_assign ::= assign [ drive_strength ] [ delay3 ] list_of_net_assignments ; list_of_net_assignments ::= net_assignment { , net_assignment } net_assignment ::= net_lvalue = expression We will not discuss drive strength specification in this chapter. The default value for drive strength is strong1 and strong0. The delay value is also optional and can be used to specify delay on the assign statement. This is like specifying delays for gates. Delay specification is discussed in this chapter. Continuous assignments have the following characteristics: 1. The left hand side of an assignment must always be a scalar or vector net or a concatenation of scalar and vector nets. It cannot be a scalar or vector register. 2. Continuous assignments are always active. The assignment expression is evaluated as soon as one of the right-hand-side operands changes and the value is assigned to the left-hand-side net. 3. The operands on the right-hand side can be registers or nets or function calls. Registers or nets can be scalars or vectors. 4. Delay values can be specified for assignments in terms of time units. Delay values are used to control the time when a net is assigned the evaluated value. This feature is similar to specifying delays for gates. It is very useful in modeling timing behavior in real circuits. Dataflow modeling describes the design in terms of expressions instead of primitive gates. Expressions, operators, and operands form the basis of dataflow modeling. Expressions are constructs that combine operators and operands to produce a result. Combines operands and operators a^b addr1[20:17] + addr2[20:17] in1 | in2 Some constructs will take only certain types of operands. Operands can be constants, integers, real numbers, nets, registers, times, bit-select (one bit of vector net or a vector register), part-select (selected bits of the vector net or register vector), and memories or function calls. integer count, final_count; final_count = count + 1;//count is an integer operand real a, b, c; c = a - b; //a and b are real operands Combinational & Sequential Logic Design using Data Flow Modeling of Verilog HDL and Xilinx Spartan-3 FPGA Desktop PC, Xilinx Software, Xilinx Spartan 3 kit

reg [15:0] reg1, reg2; reg [3:0] reg_out; Operators act on the operands to produce desired results. Verilog provides various types of operators. Verilog provides many different operator types. Operators can be arithmetic, logical, relational, equality, bitwise, reduction, shift, concatenation, or conditional. Some of these operators are similar to the operators used in the C programming language.

Procedure:
1. 2. 3. 4. 5. 6. 7. Design a four bit synchronous counter. Make a new project in Xilinx software. Apply data flow modeling to implement the above design. Connect the Spartan 3 kit to computer. Burn the code on Spartan 3 ROM. Reset the Spartan 3 kit. Check the desired logic.

Comments/ Notes:
------------------------------------------------------------------------------------------------------------ ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------

Experiment 13
Objective: Apparatus: Theory:
All statements inside an initial statement constitute an initial block. An initial block starts at time 0, executes exactly once during a simulation, and then does not execute again. If there are multiple initial blocks, each block starts to execute concurrently at time 0. Each block finishes execution independently of other blocks. Multiple behavioral statements must be grouped, typically using the keywords begin and end. If there is only one behavioral statement, grouping is not necessary. module stimulus; reg x,y, a,b, m; initial m = 1'b0; //single statement; does not need to be grouped initial begin #5 a = 1'b1; //multiple statements; need to be grouped #25 b = 1'b0; end initial begin #10 x = 1'b0; #25 y = 1'b1; end initial 128 #50 $finish; endmodule Variables can be initialized when they are declared. All behavioral statements inside an always statement constitute an always block. The always statement starts at time 0 and executes the statements in the always block continuously in a looping fashion. This statement is used to model a block of activity that is repeated continuously in a digital circuit. module clock_gen (output reg clock); //Initialize clock at time zero initial clock = 1'b0; //Toggle clock every half-cycle (time period = 20) always #10 clock = ~clock; 130 initial #1000 $finish; endmodule Combinational & Sequential Logic Design using Behavioral Modeling of Verilog HDL and Xilinx Spartan-3 FPGA Desktop PC, Xilinx Software, Xilinx Spartan 3 kit

Procedural assignments update values of reg, integer, real, or time variables. The value placed on a variable will remain unchanged until another procedural assignment updates the variable with a different value. Blocking assignment statements are executed in the order they are specified in a sequential block. A blocking assignment will not block execution of statements that follow in a parallel block. Nonblocking assignments allow scheduling of assignments without blocking execution of the statements that follow in a sequential block. A <= operator is used to specify nonblocking assignments. Note that this operator has the same symbol as a relational operator, less_than_equal_to. The operator <= is interpreted as a relational operator in an expression and as an assignment operator in the context of a nonblocking assignment. Conditional statements are used for making decisions based upon certain conditions. These conditions are used to decide whether or not a statement should be executed. Keywords if and else are used for conditional statements. There are three types of conditional statements. The keywords case, endcase, and default are used in the case statement.. case (expression) alternative1: statement1; alternative2: statement2; alternative3: statement3; ... ... default: default_statement; endcase Each of statement1, statement2 , default_statement can be a single statement or a block of multiple statements. A block of multiple statements must be grouped by keywords begin and end. The expression is compared to the alternatives in the order they are written. For the first alternative that matches, the corresponding statement or block is executed. If none of the alternatives matches, the default_statement is executed. The default_statement is optional. There are four types of looping statements in Verilog: while, for, repeat, and forever. The syntax of these loops is very similar to the syntax of loops in the C programming language. All looping statements can appear only inside an initial or always block. Loops may contain delay expressions. The keyword while is used to specify this loop. The while loop executes until the while expression is not true. If the loop is entered when the while-expression is not true, the loop is not executed at all. initial begin count = 0; while (count < 128) //Execute loop till count is 127. //exit at count 128 begin $display("Count = %d", count); count = count + 1; end end The keyword for is used to specify this loop. The for loop contains three parts: An initial condition A check to see if the terminating condition is true A procedural assignment to change value of the control variable integer count; initial for ( count=0; count < 128; count = count + 1) $display("Count = %d", count); The keyword repeat is used for this loop. The repeat construct executes the loop a fixed number of times. A repeat construct cannot be used to loop on a general logical expression. A while loop is used for that purpose. A repeat construct must contain a number, which can be a constant, a variable or a signal value. However, if the number is a variable or signal value, it is evaluated only when the loop starts and not during the loop execution. integer count;

initial begin count = 0; repeat(128) begin $display("Count = %d", count); count = count + 1; end end The keyword forever is used to express this loop. The loop does not contain any expression and executes forever until the $finish task is encountered. The loop is equivalent to a while loop with an expression that always evaluates to true, e.g., while (1). A forever loop can be exited by use of the disable statement. A forever loop is typically used in conjunction with timing control constructs. If timing control constructs are not used, the Verilog simulator would execute this statement infinitely without advancing simulation time and the rest of the design would never be executed. //Use forever loop instead of always block reg clock; initial begin clock = 1'b0; forever #10 clock = ~clock; //Clock with period of 20 units end Block statements are used to group multiple statements to act together as one. In previous examples, we used keywords begin and end to group multiple statements. Thus, we used sequential blocks where the statements in the block execute one after another.

Procedure:
1. 2. 3. 4. 5. 6. 7. Design four bit synchronous counter. Make a new project in Xilinx software. Apply behavioral modeling to implement the above design. Connect the Spartan 3 kit to computer. Burn the code on Spartan 3 ROM. Reset the Spartan 3 kit. Check the desired logic.

Comments/ Notes:
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Experiment 14
Objective: Apparatus: Theory:
The Spartan-3 Starter Kit board has a four-character, seven segment LED display controlled by FPGA user-I/O pins. Each digit shares eight common control signals to light individual LED segments. Each individual character has a separate anode control input. The pin number for each FPGA pin connected to the LED display appears in parentheses. To light an individual signal, drive the individual segment control signal Low along with the associated anode control signal for the individual character. The digital values driving the display in this example are shown in blue. The AN3 anode control signal is Low, enabling the control inputs for the leftmost character. The segment control inputs, A through G and DP, drive the individual segments that comprise the character. A Low value lights the individual segment, a High turns off the segment. A Low on the A input signal, lights segment a of the display. The anode controls for the remaining characters, AN[2:0] are all High, and these characters ignore the values presented on A through G and DP. Driving on-board displays of Xilinx Spartan-3 FPGA using Behavioral Modeling of Verilog HDL Desktop PC, Xilinx Software, Xilinx Spartan 3 kit

The Spartan-3 Starter Kit board has eight individual surface-mount LEDs located above the push button switches. The LEDs are labeled LED7 through LED0. LED7 is the left-most LED, LED0 the right-most LED.

Procedure:
1. 2. 3. 4. 5. 6. Make a new project in Xilinx software. Apply behavioral modeling to implement the basic gates. Connect the Spartan 3 kit to computer. Burn the code on Spartan 3 ROM. Reset the Spartan 3 kit. Check the desired logic.

Comments/ Notes:
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Experiment 15
Objective: Apparatus: Theory:
The Spartan-3 Starter Kit board has a dedicated 50 MHz Epson SG-8002JF series clock oscillator source and an optional socket for another clock oscillator source. The 50 MHz clock oscillator is mounted on the bottom side of the board. Utilizing on-board 50 MHz clock source of Xilinx Spartan-3 FPGA using Behavioral modeling of Verilog HDL Desktop PC, Xilinx Software, Xilinx Spartan 3 kit

Procedure:
1. 2. 3. 4. 5. 6. 7. Design a synchronous counter. Make a new project in Xilinx software. Apply behavioral modeling to implement the above design. Supply the clock source of counter from the on board clock source. Connect the Spartan 3 kit to computer. Burn the code on Spartan 3 ROM. Reset the Spartan 3 kit.

Comments/ Notes:
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Experiment 16
Objective: Apparatus: Theory:
The Spartan-3 Starter Kit board has an RS-232 serial port. The RS-232 transmit and receive signals appear on the female DB9 connector, labeled J2. The connector is a DCE-style port and connects to the DB9 DTE-style serial port connector available on most personal computers and workstations. Use a standard straight-through serial cable to connect the Spartan-3 Starter Kit board to the PCs serial port. Utilizing on-board Serial and PS/2 ports of Xilinx Spartan-3 FPGA using Behavioral modeling of Verilog HDL Desktop PC, Xilinx Software, Xilinx Spartan 3 kit

The Spartan-3 Starter Kit board includes a PS/2 mouse/keyboard port and the standard 6-pin mini-DIN connector, labeled J3.

Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a host device, the Spartan-3 FPGA in this case. The PS/2 bus includes both clock and data.

Procedure:
1. 2. 3. 4. 5. Make a new project in Xilinx software. Apply behavioral modeling to use PS2 port and serial port. Connect the Spartan 3 kit to computer. Burn the code on Spartan 3 ROM. Reset the Spartan 3 kit.

Comments/ Notes:
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