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  • ECE4680 Computer Organization and Architecture Designing Single Cycle Control

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    Narender Kumar
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    This document discusses the design of a controller for a single cycle datapath. It begins with a recap of the MIPS instruction formats and subset. It then reviews the design of a single cycle datapath. The remainder of the document goes through each instruction type - R, I, J - and shows the required control signals and datapath configuration for each. It introduces the concept of local decoding to generate the ALU control signals from the ALU operation field. In summary, it provides an in-depth look at the control logic needed to implement a single cycle MIPS processor.

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    Datapath-2-2

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    This document discusses the design of a controller for a single cycle datapath. It begins with a recap of the MIPS instruction formats and subset. It then reviews the design of a single cycle datapath. The remainder of the document goes through each instruction type - R, I, J - and shows the required control signals and datapath configuration for each. It introduces the concept of local decoding to generate the ALU control signals from the ALU operation field. In summary, it provides an in-depth look at the control logic needed to implement a single cycle MIPS processor.

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    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    41 views17 pages

    ECE4680 Computer Organization and Architecture Designing Single Cycle Control

    Uploaded by

    Narender Kumar
    This document discusses the design of a controller for a single cycle datapath. It begins with a recap of the MIPS instruction formats and subset. It then reviews the design of a single cycle datapath. The remainder of the document goes through each instruction type - R, I, J - and shows the required control signals and datapath configuration for each. It introduces the concept of local decoding to generate the ALU control signals from the ALU operation field. In summary, it provides an in-depth look at the control logic needed to implement a single cycle MIPS processor.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 17

    ECE4680 Computer Organization and Architecture Designing Single Cycle Control

    How to design a controller to produce signals to control the datapath

    ECE4680 Control.1

    2003-3-17

    Recap: The MIPS Instruction Formats


    All MIPS instructions are 32 bits long. The three instruction formats:
    31 26 op 6 bits 31 op 6 bits 31 op 6 bits 26 target address 26 bits 26 rs 5 bits rs 5 bits 21 rt 5 bits 21 rt 5 bits 16 immediate 16 bits 0 16 rd 5 bits 11 shamt 5 bits 6 funct 6 bits 0 0

    R-type I-type J-type

    The different fields are: op: operation of the instruction rs, rt, rd: the source and destination registers specifier shamt: shift amount funct: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of the jump instruction
    ECE4680 Control.2 2003-3-17

    Recap: The MIPS Subset


    ADD and subtract add rd, rs, rt sub rd, rs, rt
    31 31 26 op 6 bits 26 op 6 bits 21 rs 5 bits 21 rs 5 bits 16 rt 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits funct 6 bits 0 immediate 16 bits 0

    OR Imm: ori rt, rs, imm16 LOAD and STORE lw rt, rs, imm16 sw rt, rs, imm16 BRANCH: beq rs, rt, imm16 JUMP: j target
    31

    26 op 6 bits

    0 target address 26 bits


    2003-3-17

    ECE4680 Control.3

    Recap: A Single Cycle Datapath


    We have everything except control signals (underline) Todays lecture will show you how to generate the control signals
    Branch Rd RegDst Rt Rs 5 5 Rt Jump Clk Instruction Fetch Unit Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

    1 Mux 0 RegWr 5 ALUctr

    Rs Zero ALU

    Rt

    Rd

    Imm16 MemtoReg 0 Mux

    busW 32 Clk

    busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

    MemWr

    32 32 WrEn Adr Data Memory

    Mux

    Data In 32 Clk

    imm16

    16

    ALUSrc ExtOp
    ECE4680 Control.4 2003-3-17

    The Big Picture: Where are We Now?


    The Five Classic Components of a Computer
    Processor Input Control Memory Datapath

    Output

    Todays Topic: Designing the Control for the Single Cycle Datapath

    ECE4680 Control.5

    2003-3-17

    RTL: The ADD Instruction


    31 op 6 bits 26 rs 5 bits 21 rt 5 bits 16 rd 5 bits 11 shamt 5 bits 6 funct 6 bits 0

    add

    rd, rs, rt Fetch the instruction from memory The actual operation Calculate the next instructions address

    mem[PC] R[rd] <- R[rs] + R[rt] PC <- PC + 4

    A note: 2nd step and 3rd step can be done in parallel.

    ECE4680 Control.6

    2003-3-17

    Instruction Fetch Unit at the Beginning of Add / Subtract


    Fetch the instruction from Instruction memory: Instruction This is the same for all instructions
    30 PC<31:28> Target 4 Instruction<25:0> 26 PC Clk imm16 Instruction<15:0> 16
    ECE4680 Control.7

    mem[PC]

    30 00 30 1 Mux 0

    Addr<31:2> Addr<1:0> Instruction Memory 32

    Adder

    30 1

    0 30 Adder Mux 1 30

    Jump = previous Instruction<31:0>

    The Single Cycle Datapath during Add and Subtract


    31 op 26 rs 21 rt 16 rd 11 shamt 6 funct 0

    R[rd] <- R[rs] + / - R[rt]


    Branch = 0 Rd RegDst = 1 Rt Rs 5 5 Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Add or Subtract Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

    SignExt

    30

    Branch = previous

    Zero = previous
    2003-3-17

    1 Mux 0

    RegWr = 1 5 busW 32 Clk

    Rs Zero

    Rt

    Rd

    Imm16 MemtoReg = 0

    busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

    MemWr = 0 0 Mux 32

    ALU

    32 WrEn Adr

    Mux Data In 32 Clk

    imm16

    16

    Data Memory

    ALUSrc = 0 ExtOp = x
    ECE4680 Control.8 2003-3-17

    Instruction Fetch Unit at the End of Add and Subtract


    PC <- PC + 4 This is the same for all instructions except: Branch and Jump
    30 PC<31:28> Target 4 Instruction<25:0> 26 PC Clk imm16 Instruction<15:0> 16
    ECE4680 Control.9

    30 00 30 1 Mux 0

    Addr<31:2> Addr<1:0> Instruction Memory 32

    Adder

    30 1

    0 30 Adder Mux 1 30

    Jump = 0

    Instruction<31:0>

    The Single Cycle Datapath during Or Immediate


    31 op 26 rs 21 rt 16 immediate 0

    R[rt] <- R[rs] or ZeroExt[Imm16]


    Branch = 0 Rd RegDst = 0 Rt Rs 5 5 Jump = 0 Clk Rt Instruction Fetch Unit Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

    SignExt

    30

    Branch = 0

    Zero = x
    2003-3-17

    1 Mux 0 ALUctr = Or

    RegWr = 1 5 busW 32 Clk

    Rs Zero ALU

    Rt

    Rd

    Imm16 MemtoReg = 0

    busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

    MemWr = 0 0 Mux 32

    32 WrEn Adr

    Mux Data In 32 Clk

    imm16

    16

    Data Memory

    ALUSrc = 1 ExtOp = 0
    ECE4680 Control.10 2003-3-17

    The Single Cycle Datapath during Load


    31 op 26 rs 21 rt 16 immediate 0

    R[rt] <- Data Memory {R[rs] + SignExt[imm16]}


    Branch = 0 Rd RegDst = 0 Rt Rs 5 5 Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Add Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

    1 Mux 0

    RegWr = 1 5 busW 32 Clk

    Rs Zero ALU

    Rt

    Rd

    Imm16 MemtoReg = 1

    busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

    MemWr = 0 0 Mux

    32 WrEn Adr

    Mux Data In 32 Clk

    1 32

    imm16

    16

    Data Memory

    ALUSrc = 1 ExtOp = 1
    ECE4680 Control.11 2003-3-17

    The Single Cycle Datapath during Store


    31 op 26 rs 21 rt 16 immediate 0

    Data Memory {R[rs] + SignExt[imm16]} <- R[rt]


    Branch = 0 Rd RegDst = x Rt Rs 5 5 Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Add Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

    1 Mux 0

    RegWr = 0 5 busW 32 Clk

    Rs Zero ALU

    Rt

    Rd

    Imm16 MemtoReg = x

    busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

    MemWr = 1 0 Mux 32

    32 WrEn Adr

    Mux Data In 32 Clk

    imm16

    16

    Data Memory

    ALUSrc = 1 ExtOp = 1
    ECE4680 Control.12 2003-3-17

    The Single Cycle Datapath during Branch


    31 op 26 rs 21 rt 16 immediate 0

    if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0


    Branch = 1 Rd RegDst = x Rt Rs 5 5 5 Jump = 0 Clk Rt Instruction Fetch Unit ALUctr = Subtract Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

    1 Mux 0

    RegWr = 0

    Rs Zero

    Rt

    Rd

    Imm16 MemtoReg = x

    busW 32 Clk

    busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

    MemWr = 0 0 Mux 32

    ALU

    32 WrEn Adr

    Mux Data In 32 Clk

    imm16

    16

    Data Memory

    ALUSrc = 0 ExtOp = x
    ECE4680 Control.13 2003-3-17

    Instruction Fetch Unit at the End of Branch


    31 op 26 rs 21 rt 16 immediate 0

    if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4


    30 PC<31:28> Target 4 Instruction<25:0> 26 PC Clk imm16 Instruction<15:0> 16
    ECE4680 Control.14

    30 00 30 1 Mux 0

    Addr<31:2> Addr<1:0> Instruction Memory 32

    Adder

    30 1

    0 30 Adder Mux 1 30

    Jump = 0

    Instruction<31:0>

    SignExt

    30 Assume Zero = 1 to see the interesting case. Branch = 1 Zero = 1


    2003-3-17

    The Single Cycle Datapath during Jump


    31 op 26 target address 0

    Nothing to do! Make sure control signals are set correctly!


    Branch = 0 Rd RegDst = x Rt Rs 5 5 busA 32 0 Mux ALU Zero MemWr = 0 0 Mux 32 WrEn Adr Data In 32 Clk ALUSrc = x ExtOp = x
    ECE4680 Control.15 2003-3-17

    Instruction<31:0> <21:25> <16:20> <11:15> Instruction Fetch Unit ALUctr = x <0:15>

    Jump = 1 Clk Rt

    1 Mux 0

    RegWr = 0 5 busW 32 Clk

    Rs

    Rt

    Rd

    Imm16 MemtoReg = x

    Rw Ra Rb 32 32-bit Registers busB 32 Extender

    32

    1 32

    imm16

    16

    Data Memory

    Instruction Fetch Unit at the End of Jump


    31 op 26 target address 0

    PC <- PC<31:29> concat target<25:0> concat 00


    30 PC<31:28> Target 4 Instruction<25:0> 26 PC Clk imm16 Instruction<15:0> 16
    ECE4680 Control.16

    30 00 30 1 Mux 0

    Addr<31:2> Addr<1:0> Instruction Memory 32

    Adder

    30 1

    0 30 Adder Mux 1 30

    Jump = 1

    Instruction<31:0>

    SignExt

    30

    Branch = 0

    Zero = x
    2003-3-17

    A Summary of the Control Signals


    See Appendix A func 10 0000 10 0010 We Dont Care :-) op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 add sub ori lw sw beq jump x x x 0 0 1 RegDst 1 x 0 1 1 1 0 ALUSrc 0 x x x 1 0 0 MemtoReg 0 0 0 0 1 1 1 RegWrite 1 0 0 1 0 0 0 MemWrite 0 0 1 0 0 0 0 Branch 0 1 0 0 0 0 0 Jump 0 x x 1 1 0 x ExtOp x Add Subtract xxx Add ALUctr<2:0> Add Subtract Or 31 R-type I-type J-type
    ECE4680 Control.17

    26 op op op rs rs

    21 rt rt

    16 rd

    11 shamt

    6 funct

    0 add, sub ori, lw, sw, beq jump


    2003-3-17

    immediate target address

    The Concept of Local Decoding


    op RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop<N:0> 00 0000 R-type 1 0 0 1 0 0 0 x R-type 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump x x x 0 0 x 0 1 1 1 x x x 1 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 x x 1 1 0 Add Subtract xxx Add Or

    op 6

    Main Control

    func 6 ALUop N

    ALU Control (Local)

    ALUctr 3 ALU

    ECE4680 Control.18

    2003-3-17

    The Encoding of ALUop


    op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3

    How many bits?

    In this exercise, ALUop has to be 2 bits wide to represent: (1) R-type instructions I-type instructions that require the ALU to perform: - (2) Or, (3) Add, and (4) Subtract
    Why not consider J-type?

    To implement the full MIPS ISA, ALUop hat to be 3 bits to represent: (1) R-type instructions I-type instructions that require the ALU to perform: (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi)
    R-type R-type 1 00 ori Or 0 10 lw Add 0 00 sw Add 0 00 beq Subtract 0 01 jump xxx xxx
    2003-3-17

    ALUop (Symbolic) ALUop<2:0>


    ECE4680 Control.19

    The Decoding of the func Field


    op 6 Main Control func 6 ALUop N ori Or 0 10 16 rt rd ALU Control (Local) ALUctr 3

    ALUop (Symbolic) ALUop<2:0> 31 R-type op 26

    R-type R-type 1 00 21 rs

    lw Add 0 00 11

    sw Add 0 00 6 shamt

    beq Subtract 0 01

    jump xxx xxx 0

    funct

    Recall ALU Homework (also P. 286 text): funct<5:0> 10 0000 10 0010 10 0100 10 0101 10 1010
    ECE4680 Control.20

    Instruction Operation add subtract and or set-on-less-than

    ALUctr

    ALUctr<2:0> 000 001 010 110 111

    ALU Operation Add Subtract And Or Set-on-less-than


    2003-3-17

    ALU

    The Truth Table for ALUctr


    R-type ALUop (Symbolic) R-type ALUop<2:0> 1 00 ori Or 0 10 lw Add 0 00 sw Add 0 00 beq Subtract 0 01

    funct<3:0> 0000 0010 0100 0101 1010

    Instruction Op. add subtract and or set-on-less-than

    ALUop bit<2> bit<1> bit<0> 0 0 0 0 x 1 0 1 x 1 x x 1 x x 1 x x 1 x x 1 x x

    func bit<3> bit<2> bit<1> bit<0> x x x x x x x x x x x x 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 0 1 0

    ALU Operation Add Subtract Or Add Subtract And Or Set on <

    ALUctr bit<2> bit<1> bit<0> 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 0 1 1 0 1 1 1

    ECE4680 Control.21

    2003-3-17

    The Logic Equation for ALUctr<0>


    ALUop bit<2> bit<1> bit<0> 0 x 1 1 x x 1 x x func bit<3> bit<2> bit<1> bit<0> x x x x 0 0 1 0 1 0 1 0 ALUctr<0> 1 1 1

    This makes func<3> a dont care

    ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0>

    ECE4680 Control.22

    2003-3-17

    The Logic Equation for ALUctr<1>


    ALUop bit<2> bit<1> bit<0> 0 1 x 1 1 1 x x x x x x func bit<3> bit<2> bit<1> bit<0> ALUctr<1> x x x x 1 0 0 1 1 1 0 0 0 1 0 1 0 1 1 1

    ALUctr<1> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & !func<1> ALUop<2> & func<3> & !func<2> & func<1> & !func<1>

    ECE4680 Control.23

    2003-3-17

    The Logic Equation for ALUctr<2>


    ALUop bit<2> bit<1> bit<0> 0 1 x 1 x x 1 x x func bit<3> bit<2> bit<1> bit<0> ALUctr<2> x x x x 1 0 1 0 1 1 1 0 1 0 1

    ALUctr<2> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

    ECE4680 Control.24

    2003-3-17

    The ALU Control Block


    func 6 ALUop 3 ALU Control (Local) ALUctr 3

    ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0> ALUctr<1> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & !func<1> + ALUop<2> & func<3> & !func<2> & func<1> & !func<1> ALUctr<2> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

    ECE4680 Control.25

    2003-3-17

    The Truth Table for the Main Control


    op 6 RegDst ALUSrc Main Control

    :
    ALUop 3 00 0000 R-type 1 0 0 1 0 0 0 x R-type 1 0 0

    func 6

    ALU Control (Local)

    ALUctr 3

    op RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop (Symbolic) ALUop <2> ALUop <1> ALUop <0>
    ECE4680 Control.26

    00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump x x x 0 0 x 0 1 1 1 x x x 1 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 x x 1 1 0 Add Subtract xxx Add Or 0 0 0 x 0 1 0 0 x 0 0 0 0 x 1
    2003-3-17

    The Truth Table for RegWrite


    op RegWrite 00 0000 R-type 1 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 1 1 0 0 0

    RegWrite = R-type + ori + lw = !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0>
    op<5>

    (R-type) (ori) (lw)

    ..

    op<5>

    <0>

    ..

    op<5>

    <0>

    ..

    op<5>

    <0>

    ..

    op<5>

    <0>

    ..

    op<5>

    <0>

    ..

    op<0>

    R-type

    ori

    lw

    sw

    beq

    jump RegWrite

    ECE4680 Control.27

    2003-3-17

    PLA Implementation of the Main Control


    op<5>

    ..

    op<5>

    <0>

    ..

    op<5>

    <0>

    ..

    op<5>

    <0>

    ..

    op<5>

    <0>

    ..

    op<5>

    <0>

    ..

    op<0>

    R-type

    ori

    lw

    sw

    beq

    jump

    RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop<2> ALUop<1> ALUop<0>

    ECE4680 Control.28

    2003-3-17

    Putting it All Together: A Single Cycle Processor


    ALUop op 6 Instr<31:26> RegDst Main Control ALUSrc 3 func Instr<5:0> 6 ALU Control ALUctr 3

    :
    Rt Rs 5 5 Rt

    Branch Jump Clk Instruction Fetch Unit

    Instruction<31:0> <21:25> <16:20> <11:15> <0:15>

    Rd RegDst

    1 Mux 0 RegWr 5 ALUctr

    Rt Zero ALU

    Rs

    Rd

    Imm16 MemtoReg 0 Mux

    busW 32 Clk

    busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Extender 1 32

    MemWr

    32 32 WrEn Adr

    Mux Data In 32 Clk

    imm16 Instr<15:0>

    16

    Data Memory

    ALUSrc ExtOp
    ECE4680 Control.29 2003-3-17

    How is this Different from a Real MIPS Processor?


    The effect of load in a real MIPS Processor is delayed: - lw $1, 100 ($2) // Load Register R1 add $3, $1, $0 add $4, $1, $0 // Move old R1 into R3 // Move new R1 into R4

    The effect of load in our single cycle processor is NOT delayed - lw $1, 100 ($2) // Load Register R1 add $3, $1, $0 // Move new R1 into R3

    The effect of branch and jump in a real MIPS Processor is delayed: - Instruction Address: 0x00 j 1000 Instruction Address: 0x04 Instruction Address: 0x1000 add $1, $2, $3 sub $1, $2, $3

    Branch and jump in our single cycle processor is NOT delayed - Instruction Address: 0x00 j 1000 Instruction Address: 0x1000 sub $1, $2, $3

    ECE4680 Control.30

    2003-3-17

    Worst Case Timing


    Clk PC Old Value Clk-to-Q New Value Old Value Old Value Old Value Old Value Old Value Old Value Old Value Delay through Extender & Mux Old Value Old Value Data Memory Access Time busW
    ECE4680 Control.31

    Rs, Rt, Rd, Op, Func ALUctr ExtOp ALUSrc MemtoReg RegWr busA busB Address

    Instruction Memory Access Time New Value Delay through Control Logic New Value New Value New Value New Value New Value

    Register Write Occurs

    Register File Access Time New Value New Value ALU Delay New Value New
    2003-3-17

    Old Value

    Drawback of this Single Cycle Processor


    Long cycle time: Cycle time must be long enough for the load instruction: PCs Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew Cycle time is much longer than needed for all other instructions

    ECE4680 Control.32

    2003-3-17

    Where to get more information?


    Chapter 5.1 to 5.3 of your text book: Daid Patterson and John Hennessy, Computer Organization & Design: The Hardware / Software Interface, Morgan Kaufman Publishers, San Mateo, California, 1998. For a reference on the MIPS architecture: Gerry Kane, MIPS RISC Architecture, Prentice Hall.

    ECE4680 Control.33

    2003-3-17

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