ECE 4680 Computer Architecture and Organization

ECE 4680 Computer Architecture and Organization Lecture 1: A Short Journey to the World of Computer Architecture
Basic Ideas and Definition Major Components of Software/Hardware Computer Revolution
ece4680 Lect1 Intro.1
February 6, 2002
What is "Computer Architecture"

Co-ordination of
levels of abstraction
Application Operating System Instruction Set Architecture
Compiler
Instr. Set Proc. I/O system Digital Design Circuit Design Merits of Abstraction/Layers/Hierarchy
Under a set of rapidly changing Forces : technology, applications, Programming Languages, operating systems, history
February 6, 2002
Technology Trend: Clock rate

1,000
R10000 Pentium100 i80386
Clock rate (MHz)
100

10
i8086

i80286
i8080
i8008
i4004
0.1 1970
1975
1980
1985
1990
1995
2000
2005
30% per year ---> todays PC is yesterdays Supercomputer

ece4680 Lect1 Intro.3 February 6, 2002
Technology Trends: Transistor Count Growth

100,000,000 10,000,000 Transistors 1,000,000 100,000 10,000
i80286
R10000 Pentium R3000 R2000
i80386
i8086 i8080 i8008
1,000 1970
i4004
1975
1980
1985
1990
1995
2000
2005
- 40% per year, order of magnitude more contribution in 2 decades - More and more functions can be performed by a CPU - Similar story for storage: capacity increased by 1000x over ten years, speed only 2x
Technology => dramatic change

Processor logic capacity: about 30% per year clock rate: Memory DRAM capacity: about 60% per year (4x every 3 years) Memory speed: about 10% per year Cost per bit: improves about 25% per year Disk capacity: about 60% per year about 20% per year
February 6, 2002
Performance Trends
1000
Supercomputers Mainframes
100 Performance
10
Minicomputers
Microprocessors
0.1 1965 1970 1975 1980 1985 1990 1995 2000
Year
February 6, 2002
Processor Performance (SPEC)

performance now improves ~ 50% per year (2x every 1.5 years)
350 300 250 RIS C
P e rforma nce
200 150 100 50 0
RISC introduction
Inte l x86
35%/yr
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
Ye ar
Did RISC win the technology battle and lose the market war?
CPU and LAN Performance

Relative Performance CPU (spec) 1000 LAN 100 10 10 Mb 1 1980 1985 1990 1995 2000 Year MIPS M/120 100 Mb FDDI DEC Alpha 1 Gb ATM
1995
February 6, 2002
Moores Law
Moores Law (1965)

The number of transistors on a microchip doubles about every 18-24 months, The speed of a microprocessor doubles about every 18-24 months, The price of a microchip drops about 48% every 18-24 months,
assuming the performance metric (processor speed or memory capacity) of the chip stays the same. Official Definition of Moores Law : http://www.intel.com/intel/museum/25anniv/hof/moore.htm
February 6, 2002
H Notations and Conventions for Numbers P Appendix1: Notations and Conventions for Numbers Abbreviation Meaning Numeric Value CPrefix 10 3 m One thousandth Amill 10 6 micro One millionth 2 nano n 10 9 One billionth 0 p 10 12 One trillionth 0 pico 1 femto f One quadrillionth 10 15 atta kilo mega giga tera peta exa
a K (or k) M G T P E
One quintillionth Thousand Million Billion Trillion Quadrillion Quintillion
10 18 10 3 or 210
10 6 or 2 20 10 9 or 2 30 10 12 or 2 40 10 15 or 2 50 10 18 or 2 60
61
Even the measure unit is changing !!!

February 6, 2002
How they predict the future

Popular Science , 1949 "Computers in the future may weight no more than 1.5 tons" Thomas Watson, Chairman of IBM , 1943 "I think there is a world market for maybe five computers" Ken Olsen, founder and president of Digital Equipment Corp, 1957 "There is no reason anyone would want a computer in their home" Charles H. Duell, Commissioner, U.S. Office of patents "Everything that can be invented has been invented" Bill Gates, 1981 "640K ought to be enough for anybody"
Computer Arch. = Instruction Set Arch. + Organization

Computer Design
Instruction Set Design

Machine Language Compiler View "Computer Architecture" "Instruction Set Processor" "Building Architect"
Computer Hardware Design

Machine
Implementation
Logic Designer's View "Processor Architecture" "Computer Organization"
"Construction Engineer"
February 6, 2002
Instruction Set Architecture

. . . the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. Amdahl, Blaw, and Brooks, 1964
SOFTWARE
-- Organization of Programmable Storage -- Data Types & Data Structures: Encodings & Representations -- Instruction Formats -- Instruction (or Operation Code) Set -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions
MIPS R3000 Instruction Set Architecture

Instruction Categories
Load/Store Computational Jump and Branch Floating Point - coprocessor Memory Management Special
R0 - R31
PC HI LO
Instruction Format OP OP OP rs rs rt rt target rd sa funct
immediate
February 6, 2002
Organization
ISA Level FUs & Interconnect
Logic Designer's View
-- Capabilities & Performance Characteristics of Principal Functional Units (e.g., Registers, ALU, Shifters, Logic Units, etc. -- Ways in which these components are interconnected -- nature of information flows between components -- logic and means by which such information flow is controlled. Choreography of FUs to realize the ISA Register Transfer Level Description
February 6, 2002
Example Organization
TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20
SuperSPARC Floating-point Unit Integer Unit
MBus Module
L2 $
CC MBus
DRAM Controller
Inst Cache
Ref MMU
Data Cache Store Buffer
L64852 MBus control

M-S Adapter STDIO
serial kbd mouse audio RTC Boot PROM Floppy
SBus
SBus
DMA
SCSI Ethernet
Bus Interface
SBus Cards
February 6, 2002
Measurement and Evaluation

Design
Architecture is an iterative process -- searching the space of possible designs -- at all levels of computer systems
Analysis
Creativity
Cost / Performance Analysis
Good Ideas
Bad Ideas
Mediocre Ideas
February 6, 2002
Levels of Representation
temp = v[k]; High Level Language Program Compiler lw $15, Assembly Language Program Assembler Machine Language Program Machine Interpretation Control Signal Spec lw $16, sw $16, sw $15, 0($2) 4($2) 0($2) 4($2) v[k] = v[k+1]; v[k+1] = temp;
February 6, 2002
ECE468: Course Overview

Computer Design Instruction Set Deign
Machine Language Compiler View "Computer Architecture" "Instruction Set Processor" "Building Architect"
Computer Hardware Design

Machine Implementation\ Logic Designer's View "Processor Architecture" "Computer Organization" Construction Engineer
Few people design computers! Very few design instruction sets! Many people design computer components. Very many people are concerned with computer function, in detail.
February 6, 2002
ECE468:So what's in it for me?
In-depth understanding of the inner-workings of modern computers, their evolution, and trade-offs present at the hardware/software boundary.
Insight into fast/slow operations that are easy/hard to implementation hardware

Experience with the design process in the context of a large complex (hardware) design.
Functional Spec --> Control & Datapath

Learn how to completely design a correct single processor computer. No magic required to design a computer Foundation for students aspiring to work in computer architecture. Others: solidifies an intuition about why hardware is as it is.
February 6, 2002
The SPARCstation 20
SPARCstation 20
Memory Controller MBus MBu s MBu s Slot 1 Slot 0
Memory SIMMs Memory Bus Disk
SBus SBus
Slot 1 Slot 0 SBus
SBus SBus
Slot 3 Slot 2
Tape
MSBI
SEC
MACIO
SCSI Bus
Keyboard & Mouse
Floppy Disk
External Bus
February 6, 2002
Levels of Organization
SPARCstation 20
Computer SPARC Processor Control Datapath Memory Devices Input Output
February 6, 2002
The Underlying Network

SPARCstation 20
Memory Controller
Memory Bus Standard I/O Bus:
Processor Bus: MBus
SCSI Bus Suns High Speed I/O Bus: SBus
MSBI
SEC
MACIO
Low Speed I/O Bus: External Bus
February 6, 2002
Processor and Caches

SPARCstation 20
MBus Module SuperSPARC Processor

MBus MBu s MBu s Slot 1 Slot 0
Registers
Datapath
Internal Cache
Control
External Cache
February 6, 2002
Memory
SPARCstation 20
SIMM Slot 0 SIMM Slot 1 SIMM Slot 2 SIMM Slot 3 SIMM Slot 4 SIMM Slot 5 SIMM Slot 6 SIMM Slot 7
Memory Controller
Memory Bus
DRAM SIMM
DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM
February 6, 2002
Input and Output (I/O) Devices

SCSI Bus: Standard I/O Devices SBus: High Speed I/O Devices External Bus: Low Speed I/O Device
Disk
SPARCstation 20
SBus SBus
Slot 1 Slot 0 SBus
SBus SBus
Slot 3 Slot 2
Tape
SEC
MACIO
SCSI Bus
Keyboard & Mouse
Floppy Disk
External Bus
February 6, 2002
Standard I/O Devices

SPARCstation 20
SCSI = Small Computer Systems Interface A standard interface (IBM, Apple, HP, Sun ... etc.) Computers and I/O devices communicate with each other The hard disk is one I/O device resides on the SCSI Bus
Tape Disk
SCSI Bus
February 6, 2002
High Speed I/O Devices

SPARCstation 20
SBus is SUNs own high speed I/O bus SS20 has four SBus slots where we can plug in I/O devices Example: graphics accelerator, video adaptor, ... etc. High speed and low speed are relative terms
SBus SBus
Slot 1 Slot 0 SBus
SBus SBus
Slot 3 Slot 2
February 6, 2002
Slow Speed I/O Devices

SPARCstation 20
The are only four SBus slots in SS20--seats are expensive The speed of some I/O devices is limited by human reaction time--very very slow by computer standard Examples: Keyboard and mouse No reason to use up one of the expensive SBus slot
Keyboard & Mouse
Floppy Disk
External Bus
February 6, 2002
Summary
ISA--Principle of abstraction Hiding details from the level above Both software designers and hardware designers comply with
All computers consist of five components Processor: (1) datapath and (2) control (3) Memory (4) Input devices and (5) Output devices
Not all memory are created equally Cache: fast (expensive) memory are placed closer to the processor Main memory: less expensive memory--we can have more Input and output (I/O) devices has the messiest organization Wide range of speed: graphics vs. keyboard Wide range of requirements: speed, standard, cost ... etc. Least amount of research (so far)

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ECE 4680 Computer Architecture and Organization Lecture 1: A Short Journey to the World of Computer Architecture

Basic Ideas and Definition Major Components of Software/Hardware Computer Revolution

ece4680 Lect1 Intro.1

What is "Computer Architecture"

Application Operating System Instruction Set Architecture

ece4680 Lect1 Intro.2

Technology Trend: Clock rate

Clock rate (MHz)

30% per year ---> todays PC is yesterdays Supercomputer

Technology Trends: Transistor Count Growth

i8086 i8080 i8008

Technology => dramatic change

ece4680 Lect1 Intro.5

0.1 1965 1970 1975 1980 1985 1990 1995 2000

ece4680 Lect1 Intro.6

Processor Performance (SPEC)

200 150 100 50 0

CPU and LAN Performance

ece4680 Lect1 Intro.8

Moores Law (1965)

ece4680 Lect1 Intro.9

One quintillionth Thousand Million Billion Trillion Quadrillion Quintillion

Even the measure unit is changing !!!

How they predict the future

Computer Arch. = Instruction Set Arch. + Organization

Instruction Set Design

Computer Hardware Design

Logic Designer's View "Processor Architecture" "Computer Organization"

ece4680 Lect1 Intro.12

Instruction Set Architecture

MIPS R3000 Instruction Set Architecture

Instruction Format OP OP OP rs rs rt rt target rd sa funct

ece4680 Lect1 Intro.14

ece4680 Lect1 Intro.15

SuperSPARC Floating-point Unit Integer Unit

Data Cache Store Buffer

L64852 MBus control

ece4680 Lect1 Intro.16

Measurement and Evaluation

ece4680 Lect1 Intro.18

ECE468: Course Overview

Computer Hardware Design

ece4680 Lect1 Intro.19

ECE468:So what's in it for me?

Insight into fast/slow operations that are easy/hard to implementation hardware

Functional Spec --> Control & Datapath

ece4680 Lect1 Intro.20

Memory Controller MBus MBu s MBu s Slot 1 Slot 0

Memory SIMMs Memory Bus Disk

Slot 1 Slot 0 SBus

Keyboard & Mouse

ece4680 Lect1 Intro.21

Computer SPARC Processor Control Datapath Memory Devices Input Output

ece4680 Lect1 Intro.22

The Underlying Network

Memory Bus Standard I/O Bus:

Processor Bus: MBus

SCSI Bus Suns High Speed I/O Bus: SBus

Low Speed I/O Bus: External Bus

ece4680 Lect1 Intro.23

Processor and Caches

MBus Module SuperSPARC Processor