Cafc 166

No.
2012-1480
(Reexamination No. 95/001,166)

IN THE
United States Court of Appeals
FOR THE FEDERAL CIRCUIT

RAMBUS, INC.
Appellant,

v.

DAVID J. KAPPOS, DIRECTOR,
UNITED STATES PATENT AND TRADEMARK OFFICE,
Appellee.

Appeal from the United States Patent and Trademark Office,
Board of Patent Appeals and Interferences

BRIEF FOR APPELLANT RAMBUS INC.

Kara F. Stoll
FINNEGAN, HENDERSON, FARABOW,
GARRETT & DUNNER, LLP
901 New York Avenue, N.W.
Washington, D.C. 20001
(202) 408-4000
John M. Whealan
4613 Merivale Road
Chevy Chase, MD 20815
(202) 994-2195

Jeffrey A. Lamken
Counsel of Record
Michael G. Pattillo, Jr.
MOLOLAMKEN LLP
The Watergate, Suite 660
600 New Hampshire Avenue, N.W.
(202) 556-2010
Counsel for Appellant Rambus Inc.
Case: 12-1480 Document: 21 Page: 1 Filed: 09/07/2012

CERTIFICATE OF INTEREST

Counsel for Appellant Rambus Inc. certifies the following:

1. The full name of every party represented by me is: Rambus Inc.

2. The name of the real party in interest represented by me is: Rambus Inc.

3. All parent corporations and any publicly held companies that own 10 percent
or more of the stock of the party represented by me are: None

4. The names of all law firms and the partners or associates that appeared for
the party now represented by me in the trial court or agency or are expected
to appear in this Court are:

John M. Whealan

MOLOLAMKEN LLP:
Jeffrey A. Lamken

FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER,
LLP:
Kara F. Stoll
Jeffery P. Langer
Abhay A. Watwe

STERNE, KESSLER, GOLDSTEIN & FOX, PLLC:
Robert Greene Sterne
Jon E. Wright

September 7, 2012

/s/ Jeffrey A. Lamken
Jeffrey A. Lamken

i
TABLE OF CONTENTS
Page

STATEMENT OF RELATED CASES.................................................................. vii
JURISDICTIONAL STATEMENT ..........................................................................1
ISSUES PRESENTED...............................................................................................1
STATEMENT OF THE CASE..................................................................................2
STATEMENT OF FACTS ........................................................................................3
I. Technological Background..............................................................................3
A. DRAM Memory Devices ......................................................................3
B. Farmwald and Horowitzs Solution to the Memory Bottleneck...........5
1. Synchronous DRAM...................................................................5
2. The Farmwald Patent ..................................................................6
II. The 109 Patent................................................................................................9
A. The Claims ..........................................................................................10
B. The Specification.................................................................................11
III. Reexamination Proceedings ..........................................................................14
A. The Examiners Decision....................................................................14
B. The Boards Decision..........................................................................15
C. The Rehearing Decision......................................................................19
STANDARD OF REVIEW.....................................................................................20
SUMMARY OF ARGUMENT...............................................................................20

ii
ARGUMENT...........................................................................................................23
I. Farmwalds Delay-Value Method Does Not Anticipate the 109
Patents Use of a Separate and Later Signal..................................................24
A. Claim 1 Recites a Method Using a Decoupled and Subsequent
Signal To Initiate Data Transfer..........................................................25
1. The Claim Language.................................................................26
2. The Specification ......................................................................28
a. Decoupling......................................................................28
b. Signal ..............................................................................29
c. The Distinction and Critique of the Prior Art
Patent ..............................................................................31
B. The Board Erred in Construing the 109 Patent To
(1) Encompass the Use of Delay Values and (2) Dispense
With Decoupling .................................................................................37
1. The Board Erred by (1) Interpreting the Term Signal
Out of Context and (2) Relying on an Expansive
Dictionary Definition of That Term..........................................38
2. The Board Erred by Dispensing with Decoupling....................41
3. The Board Erred in Relying on an Alternate
Embodiment Not Claimed in the 109 Patent But
Claimed in Another Rambus Patent..........................................42
a. The Claim and Specification Exclude the
Alternate Embodiment....................................................44
b. Rambuss 914 Patent Claims the Delay
Value Embodimentthe 109 Patent Does
Not ..................................................................................46
4. The Boards Rationale for Rejecting the 109 Patents
Distinction of Prior Art Fails ....................................................48

iii
II. Even if the Boards Construction That Signal Encompasses
Value and Rejecting Decoupling Were Correct, Farmwald Still
Does Not Disclose All the Elements of the 109 Patents Claims in
the Same Arrangement ..................................................................................50
1. Option (1): In the Request Packet .........................................52
2. Option (2): Stored in an Access Register or
(Sometimes) Retriev[ed] from the Register ..........................53
3. Option (3): Comparing It to a Clock Value ..........................56
4. Option (4): Implicitly Used To Generate Another
Implicit Signal.........................................................................57
5. Options (1), (2), (3), and/or (4) in Some Combination.........59
CONCLUSION........................................................................................................60


iv
TABLE OF AUTHORITIES
Page(s)
CASES
Abbott Labs. v. Sandoz, Inc., 544 F.3d 1341 (Fed. Cir. 2008) ....................23, 51, 55
Altiris, Inc. v. Symantec Corp., 318 F.3d 1363 (Fed. Cir. 2003).............................28
Andersen Corp. v. Fiber Composites, LLC, 474 F.3d 1361
(Fed. Cir. 2007)...................................................................................................48
August Tech. Corp. v. Camtek, Ltd., 655 F.3d 1278
(Fed. Cir. 2011).................................................................................44, 45, 46, 47
Bancorp Servs., L.L.C. v. Hartford Life Ins. Co., 359 F.3d 1367
(Fed. Cir. 2004)...................................................................................................40
CAE Screenplates Inc. v. Heinrich Fiedler GmbH & Co. KG,
224 F.3d 1308 (Fed. Cir. 2000) ..........................................................................40
CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359 (Fed. Cir. 2002) ...........36, 50
Connell v. Sears, Roebuck & Co., 722 F.2d 1542 (Fed. Cir. 1983) ........................53
Cybor Corp. v. FAS Techs., Inc., 138 F.3d 1448 (Fed. Cir. 1998)
(en banc)..............................................................................................................20
Enzo Biochem, Inc. v. Applera Corp., 599 F.3d 1325 (Fed. Cir. 2010),
cert. denied, 131 S. Ct. 3020 (2011).............................................................24, 44
Finisar Corp. v. DirecTV Grp., Inc., 523 F.3d 1323 (Fed. Cir.),
cert. denied, 555 U.S. 1070 (2008)...............................................................51, 59
In re Hyatt, 211 F.3d 1367 (Fed. Cir. 2000)............................................................20
In re Suitco Surface, Inc., 603 F.3d 1255 (Fed. Cir. 2010) ...............................25, 37
Johnson & Johnston Assocs. Inc. v. R.E. Serv. Co., 285 F.3d 1046 (Fed.
Cir. 2002) (en banc) ............................................................................................44
Lindemann Maschinenfabrik GMBH v. Am. Hoist & Derrick Co.,
730 F.2d 1452 (Fed. Cir. 1984) ..........................................................................51

v
Mantech Envtl. Corp. v. Hudson Envtl. Servs., Inc., 152 F.3d 1368
(Fed. Cir. 1998)...................................................................................................27
Medrad, Inc. v. MRI Devices Corp., 401 F.3d 1313 (Fed. Cir. 2005).....................36
Modine Mfg. Co. v. U.S. Intl Trade Commn, 75 F.3d 1545 (Fed.
Cir.), cert. denied, 518 U.S. 1005 (1996) .....................................................42, 46
Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359 (Fed. Cir. 2008).........20, 50, 58
Omega Engg, Inc., v. Raytek Corp., 334 F.3d 1314 (Fed. Cir. 2003)....................48
Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc) ................. passim
Renishaw PLC v. Marposs Societa per Azioni, 158 F.3d 1243
(Fed. Cir. 1998)...................................................................................................36
Semitool, Inc. v. Dynamic Micro Sys. Semiconductor Equip. GMBH,
444 F.3d 1337 (Fed. Cir. 2006) ....................................................................54, 56
Teleflex, Inc. v. Ficosa N. Am. Corp., 299 F.3d 1313 (Fed. Cir.
2002) .......................................................................................................25, 38, 44
TIP Sys., LLC v. Phillips & Brooks/Gladwin, Inc., 529 F.3d
1364 (Fed. Cir.), cert. denied, 555 U.S. 1046 (2008)...................................44, 47
STATUTES
35 U.S.C. 102 ........................................................................................................50
35 U.S.C. 134(b)......................................................................................................1
35 U.S.C. 141 ..........................................................................................................1
35 U.S.C. 311 ..........................................................................................................1
35 U.S.C. 312 ..........................................................................................................1
35 U.S.C. 313 ..........................................................................................................1
35 U.S.C. 314 ..........................................................................................................1
35 U.S.C. 315(a)(1) .................................................................................................1

vi
OTHER AUTHORITIES
Websters Third New Intl Dictionary (2002)....................................................31, 54


vii
STATEMENT OF RELATED CASES

Appellant Rambus Inc. is unaware of any other appeals or petitions
taken in this reexamination proceeding. There are, however, other matters
pending that involve the patent at issue in this appeal, U.S. Patent No.
7,287,109:
Rambus Inc. v. LSI Corporation, No. 3:10-cv-05446 (N.D. Cal.)
Rambus Inc. v. STMicroelectronics NV, et al., No. 3:10-cv-05449
(N.D. Cal.)
Certain Semiconductor Chips and Products Containing Same, Inv.
No. 337-TA-753 (USITC)

JURISDICTIONAL STATEMENT
This appeal arises from an inter partes reexamination proceeding before the
U.S. Patent and Trademark Office (PTO). See 35 U.S.C. 311-314. Rambus
(the patent owner) appealed the Examiners final rejection of the claims to the
Board of Patent Appeals and Interferences (the Board), which had jurisdiction
under 35 U.S.C. 134(b) and 315(a)(1). The Board issued a final decision affirm-
ing the rejection on September 1, 2011. The Board denied Rambuss rehearing
request on March 22, 2012. Rambus filed a notice of appeal on May 16, 2012.
This Court has jurisdiction under 35 U.S.C. 141.
ISSUES PRESENTED
This case concerns the Boards finding that all 25 claims in Rambuss 109
patent were anticipated by another Rambus patent, the Farmwald 037 patent, that
the 109 patent improves upon and expressly distinguishes as prior art. The
questions presented are:
1. Whether the Board misinterpreted representative claim 1 by:
1

a. taking the word signal out of context, relying on the broadest
dictionary definition available, and equating it with a delay value stored in an
access-time register.
____________________________
1
Independent claims 12 and 20 of the 109 patent stand or fall with claim 1. A10.

2
b. dispensing with the claims requirement that its signal be de-
coupled from the command specifying the write operation.
2. Whether the Board erred in finding anticipation when it listed 4 possi-
ble aspects of the prior art patent andwithout explaining where and how the
patent discloses themdeclared that each of the 4, and perhaps some combination
thereof, anticipates the claims.
STATEMENT OF THE CASE
U.S. Patent No. 7,287,109 (109 patent) is titled Method of Controlling a
Memory Device Having a Memory Core. It claims priority to application No.
08/545,292, filed on October 19, 1995, by Richard M. Barth, et al. and is assigned
to Rambus. In 2009, NVIDIA Corporation requested inter partes reexamination of
the 109 patent, and the PTO granted the request. JA2057. The Examiner rejected
all claims as anticipated by an earlier Rambus patent, No. 6,584,037 (Farmwald),
and based on nonstatutory obviousness-type double patenting. JA11015-16,
JA11020-38.
2
The Examiner ultimately rejected NVIDIAs obviousness argu-
ments. JA11038-51. Rambus appealed to the Board, and NVIDIA cross-appealed.
The Board affirmed the rejection of all claims on anticipation grounds, but
reversed the Examiners nonstatutory double-patenting rejections. A10-23. The
____________________________
2
Citations to A__ are to the addendum to this brief. Citations to JA__ are to
the joint appendix.

3
Board did not address the Examiners conclusion that the claims were non-
obvious. A23.
Rambus sought rehearing. While that request was pending, NVIDIA and
Rambus settled and NVIDIA withdrew from the proceedings. JA17514-15. The
Board denied rehearing. JA17520-34. Rambus now appeals.
STATEMENT OF FACTS
The 109 patent teaches a method of controlling memory devices (such as
DRAM) that improves performance by issuing a separate signal to the memory
device to indicate when data transfer will begin. Four years after granting the 109
patent, the PTO invalidated each of its claims on the theory that a prior patent
issued to RambusFarmwaldanticipated every one of its limitations. The
Board so ruled even though the 109 patent distinguished and improved upon
Farmwald, and even though the Examiner conducting the original examination
allowed the 109 patents claims only after considering the very disclosures con-
tained in Farmwald.
I. Technological Background
A. DRAM Memory Devices
Memory devices are used to store and retrieve information in electronic
products, including computers. The 109 patent describes a method of controlling
a memory device containing multiple memory cells, and uses a dynamic random
access memory device (DRAM) as an example.

4
The process of storing information in a DRAM is referred to as a write
operation. The process of retrieving information from a DRAM is referred to as a
read. Information is written to or read from a DRAM using a memory controller
separate from the DRAM itself. For example, in a write operation, a controller
transmits control signals to the DRAM, along with address information
indicating where (by row and column) the data will be stored. The DRAM
receives the data from the controller and stores it at that location. The controller
and DRAM communicate and transfer data through a set of lines called a bus.
Before the 1990s, DRAMs operated asynchronouslythat is, DRAM read
and write operations were not conducted with reference to a system clock.
3

Instead, the DRAM would act as quickly as possible after being told to read or
write by the memory controller. Between the time the controller issued the read
or write request and the DRAM was ready to complete execution (placing the data
on the bus for a read, or transferring data from the bus for a write), the controller
had to wait because the DRAM had to perform internal preparatory functions.
Moreover, because of the nature of asynchronous communications, the bus
between the memory controller and the DRAM would be busy until the
____________________________
3
Computers have a system clock that functions like a metronome and provides a
common timing reference for the system. See JA16687.

5
commands completion. This created a wait state during which the controller
could not perform other functions until the DRAM responded.
B. Farmwald and Horowitzs Solution to the Memory Bottleneck
Developments in microprocessor technology have enabled the speed of
microprocessors to increase exponentially. The performance of DRAM, however,
increased more slowly. In the late 1980s and early 1990s, the disparity in proces-
sor and DRAM speeds created a memory bottleneck that diminished the advan-
tages of faster processors because memory could not keep up.
1. Synchronous DRAM
In 1990, Rambus founders Dr. Michael Farmwald and Dr. Mark Horowitz
invented a DRAM with an innovative architecture that substantially increased
speed and efficiency, partially addressing the memory bottleneck. To enable their
innovations, they made the DRAM synchronous rather than asynchronousi.e.,
they moved information between the controller and DRAM with reference to the
system clock, rather than having the DRAM execute an operation as quickly as
possible after receiving a request. Making DRAM synchronous was both
revolutionary and counterintuitive: It sped system performance up by slowing
certain operations down.
With asynchronous DRAM, the controller would issue a request and then
enter a wait state until the operation was completed. The controller used the

6
control and address lines throughout the operation, making it impossible for the
controller to issue other commands. The conventional wisdom had been that
DRAM performance could best be improved by minimizing the latencythe
delaybetween a controllers request and the DRAMs execution. Making
DRAM operations synchronous to the system clock was contrarian because it
added latency. But Farmwald and Horowitz determined, inter alia, that making
DRAM synchronous would allow the controller to make additional requests to
different DRAMs while waiting for a previous request to be fulfilled. Using the
system clock, the data associated with each read or write request would be sent at a
known interval following the DRAMs receipt of the request.
Making the DRAM synchronous allowed the controller to do other tasks
while the DRAM processed its requests, rather than waiting for the DRAM. That
process, known as interleaving, refers to the controllers ordering of data,
address, and control signals associated with multiple transactions to maximize
usage of the bus and DRAM resources. Farmwald and Horowitzs innovations
enabled DRAM data transmission rates of 500 Mb/s, about 20 times faster than
prior DRAM.
2. The Farmwald Patent
On April 18, 1990, U.S. Patent Application No. 07/510,898 was filed,
naming Farmwald and Horowitz as inventors. One patent that issued from that

7
application, No. 6,584,037 (Farmwald), discloses and claims specific methods
for controlling synchronous memory devices like DRAM. In Farmwald, the
DRAM transfers the data for a read or write command only after two events occur:
(1) the DRAM receives the command, and (2) a selected delay time lapses.
JA17614, 27:14-20.
Farmwald teaches using delay values stored in access-time registers: The
memory device contain[s] . . . access-time registers 173 which store a set of one or
more delay times at which the device can or should be available to send or receive
data. JA17603, 6:40-44 (referencing Fig. 16). Farmwalds access-time registers
can be modified and preferably are set as part of an initialization sequence that
occurs when the system is powered up or reset. JA17603, 6:45-47. Farmwald
thus claims outputting a value to the memory device, wherein the value is
representative of the delay time; and outputting a second operation code to the
memory device that instructs the memory device to internally store the value.
JA17614, 27:32-36. For example, one access-time register might store a value
representing 2 cycles of the system clock, another register 4 cycles, and another 8.
In Farmwalds preferred embodiment, the controller sends a request packet
to the DRAM. JA17604-05, 8:66-10:5. That request contains an operation code or
op code that specifies the type of access, including whether it is a read or
write, and that determines the access-time register to be used. JA17605, 9:54-

8
10:1.
4
On receiving the command, the DRAM checks the access-time register for
the appropriate delay period. The choice of register thus determines which
previously stored delay value is used.
Accordingly, the DRAM receives the command control information and
begins preparatory steps, but defers transferring data. JA17605, 9:23-25; JA17614,
27:19-20. The time after which data is driven onto the bus linesand data
transfer occursis selected from values stored in slave access-time registers.
JA17605, 9:23-25. For example, the controller might send a write request to the
DRAM, which will cause the DRAM to begin necessary internal operations. By
including information specifying a particular register, however, the request also
indicates that the DRAM should not begin sampling data (i.e., data transfer for a
write operation) until after the period in the specified register lapses. So, if register
1 is selected, there may be a delay of 8 cycles; register 2 might require a different
delay.
____________________________
4
Farmwald discloses a method that uses two 4-bit fields, in which the first bit
specifies a read or write, and the next indicates the type of access (e.g., page or
normal mode). JA17605-06, 9:54-66, 10:1-5, 11:30-39 (table). As the first table
in column 11 illustrates, each Access Type is associated with a particular register.
Farmwald also offered the alternative of having a fixed delay time associated with
a particular operation, with the slave respond[ing] to selected op codes with pre-
selected access times. JA17605-06, 9:66-10:2 & 11:30-39 (table).

9
II. The 109 Patent
The speed of computer processors continued to increase, requiring still more
efficient DRAM. Another group of Rambus inventors, led by Richard Barth,
determined that Farmwald was limited because it required delay values to be stored
in and selected from a pre-determined set of access-time registers. JA17603,
6:46-48; JA17605, 9:23-25. Farmwald was also limited because it required timing
to be determined when the controller sent the read/write request. That meant the
controller could not decide the timing of the read/write operation after the request
was sent. JA17605, 9:31-10:5. Those attributes and others constrained Farm-
walds flexibility; added delay between when the controller determined data trans-
fer should occur and the initiation of data transfer; imposed delay-value storage
steps; and required additional circuitry (e.g., access-time registers). A58, 10:27-
40. The Barth teams efforts culminated in a signal-based method of controlling
data-transfer timing that was simpler, more flexible, and more precise than
Farmwalds access-time-register-stored delay values.
Over five years after Farmwalds priority date, in October 1995, Barth filed
U.S. Patent Application No. 08/545,292, directed to, inter alia, systems and
methods for increasing the efficiency of communication between a memory
controller and memory devices. Eventually, the PTO issued seven patents claim-

10
ing priority to the initial Barth application. Those included the parent, Patent No.
5,748,914 (914 patent), as well as the 109 patent at issue here.
A. The Claims
The 109 patent teaches a new and different signal-based method for con-
trolling timing. It provides a mechanism that decouples (1) the transmission of
control information specifying the read/write operation from (2) the provision of a
signal determining when data transfer occurs. A55, 3:34-35. And the 109 patent
uses a signal issued by the controller to the DRAMwhen the controller deems
appropriateto indicate that the DRAM should transfer data at that time. A58,
9:2-6.
Claim 1 recites:
A method of controlling a memory device having a memory core,
wherein the method comprises:
[1] providing control information to the memory device, wherein
the control information includes a first code which specifies
that a write operation be initiated in the memory device;
[2] providing a signal to the memory device, wherein the signal
indicates when the memory device is to begin sampling write
data, wherein the write data is stored in the memory core during
the write operation;
[3] providing a first bit of the write data to the memory device
during an even phase of a clock signal; and
[4] providing a second bit of the write data to the memory device
during an odd phase of the clock signal.
A74-75, 41:62-43:2 (numbers added for reference).

11
B. The Specification
1. The specification explains that the controller transmit[s] data transfer
control information separate from command control information. A58, 9:26-27
(emphasis added). The controller first specifies the write operation (command
control information), and the DRAM begins preparatory functions. A58, 9:30-35.
But the controller does not at that time specify when data is to be transferred.
Instead, data transfer is deferred until the controllers transmission of the strobe
signal [data transfer control information] to begin the transfer specified. A58,
10:48-49. The method thus makes delay values and access-time registers to
store them potentially unnecessary. The timing of data transfer is controlled
instead through a signal sent separately from and subsequent to the write request.
2. The specification also expressly distinguishes prior-art systems (like
Farmwald) that did not permit decoupling of command control information from
data transfer control information and that utilized (1) delay values stored in (2)
access-time registers. A58, 10:33-39. The specification explains that, in the prior
art, a delay value was determined by selecting a particular register within the
DRAM at the time the write or read request was sent. A58, 10:33-37. The con-
troller thus could not later alter the delay in light of changing conditions. For ex-
ample, it could not, in light of a new series of requests, achieve a more efficient
interleave pattern by having the operation performed sooner or later than the period

12
stored in the selected register. A59, 11:16-21. The 109 patent explains: Because
the timing of a data transfer is dictated by the timing of the request for data trans-
fer and set at the time of the request, A58, 10:27-28, the prior art was compara-
tively inflexible with respect to how control and data signals may be interleaved.
A59, 11:4-6. In other words, the 109 patent recognized that, under Farmwald,
once the op code associated with a particular command and register was sent, the
controller was stuck with the delay associated with that register and the resulting
timing of data transfer.
In the 109 patent, by contrast, the data transfer control information which
controls the timing of the data transfer associated with a request packet is sent
separately from and subsequent to the command control information to which it
corresponds. A58, 10:40-43. Consequently, there is no fixed time between when
the command specifying the operation is sent and when sampling begins. A57,
7:63-67. If system conditions change after the write command has been sent to the
DRAM, the controller can adjust the timing of data transfer to achieve the most
efficient interleave. A57, 7:58-60. And more efficient interleave patterns yield
more efficient bus usage and greater system performance. A65, 23:37-42.
Moreover, prior-art systems such as Farmwald relied on a limited menu of
delay values previously stored in access-time registers, restricting the available
interleave patterns. A58, 10:33-37. For example, the DRAM might have 4 access-

13
time registers, one storing perhaps 1 cycle, another 4, another 8, and another 12
cycles. See, e.g., A17606, 11:30-39 (showing 4 register values). If the delay value
that would most efficiently utilize the bus in a particular instance were 6 cycles,
that was not an option; instead, the prior-art system would use 8 cycles, adding
unnecessary delay. The 109 patent presents no such limitations because the con-
troller can send a signal to begin transfer whenever it determines data transfer
should begin. A59, 11:24-26.
5
That also has the advantage of precision because it
reduces the interval between the signal governing when data transfer occurs and
the actual data transfer. A58, 9:41-46.
3. In initially examining the 109 patent, the PTO considered the delay-
value methods in the Farmwald patents. The Examiner found that the Farmwald
755 patent (which shares a specification with Farmwald) anticipated the 109
patents claims. JA863-66. The Examiner characterized the 755 patent as
disclosing (at 21:35-67) the claimed providing a signal to the memory device,
wherein the signal indicates when the memory device is to begin sampling write
data. JA887-88. After Rambus responded to the Office Action, the claims were
allowed and the 109 patent issued. JA901.
____________________________
5
The specification also mentions an alternate embodiment, previously claimed
in a parent patent (the 914 patent). That embodiment is not claimed in the 109
patent. See pp. 44-48, infra.

14
III. Reexamination Proceedings
NVIDIA initiated an inter partes reexamination of the 109 patent.
A. The Examiners Decision
The Examiner rejected all of the 109 patents claims as anticipated by
Farmwald. JA10989-10995, JA11020-38. He noted that claim 1 of the 109 patent
recites providing a signal to the memory device, wherein the signal indicates
when the memory device is to begin sampling write data. JA10992. The Exam-
iner found that limitation disclosed by claim 28 of Farmwald, which recites out-
putting a value to the memory device wherein the value is representative of the
delay time, where access-time registers on the DRAM store a set of one or
more delay times. Id. The Examiner thus interpreted the claimed signal in the
109 patentwhich tells the DRAM to begin data transferas being equivalent
to the value that, under Farmwald, is output[ ] to the memory device and stored
in an access-time register. JA10989. The Examiner understood that, under
Farmwald, the delay value is sent to the access-time register in advance,
acknowledging that the memory device in Farmwald relies upon the previously
received [delay] value to indicate when the DRAM is to begin sampling data.
JA10993 (emphasis added); JA10992 (the stored value in Farmwald 037 was
sent to the memory device previously (emphasis added)). The Examiner did not,
however, address the fact that claim 1 of the 109 patent reverses the order,

15
specifying that the command control information is sent to the DRAM first,
including a code which specifies that a write operation be initiated in the memory
device, and the signal that triggers data transfer follows afterward. A74, 41:65-
42:64 (emphasis added).
The Examiner also rejected various claims based on nonstatutory
obviousness-type double patenting. JA11014-16. But the Examiner ultimately
determined that the 109 patent was not obvious in light of other prior art.
JA11038-50. The Examiner also rejected NVIDIAs argument that the 109 patent
was anticipated by another Barth patent. JA11050.
B. The Boards Decision
The Board affirmed the Examiners decision in part and reversed in part.
1. The Board upheld the Examiners rejection of all claims of the 109
patent as anticipated by Farmwald, albeit on somewhat different grounds. The
Board did not perform separate claim construction and anticipation analyses, i.e.,
first examining what the claims mean followed by a detailed evaluation of whether
Farmwald discloses all elements of the 109 patents claims, arranged as the 109
patent arranges them. Instead, the Board focused on the delay value that is pro-
grammed into registers in Farmwald, asking whether it anticipates one aspect of
the 109 patentthe signal to begin sampling data recited in claim 1. A10.
Isolating the word signal, the Board observed that one of the (nine) definitions of

16
that term in the IEEE Standard Dictionary is the physical representation of data.
Id. It then concluded that the term signal in the 109 patent could encompass a
delay value.
The Board then ruled that the claimed signal was anticipated, not by a
specific transmission disclosed in Farmwald, but rather by any of four different
uses of delay values and possibly some combination thereof. The Board stated that
the 109 patents signal was anticipated by Farmwalds delay value, which is
either: 1) in the request packet; 2) stored in an access-register; 3) provided for
comparison to a clock; and/or 4) implicitly used to generate another implicit signal
after the comparison to signify a match. A13 (emphasis added); see A14. The
Board did not specify whether that and/or reflected any one of 16 possible
combinations.
The Board recognized that the 109 patent recites two initial stepsfirst
providing control information to the DRAM with a code specifying a write
operation and then providing a signal to the DRAM to begin transferring data.
A12. But it ruled that Farmwalds two separate instructions/codes satisfy those
steps: [T]he read or write bit constitutes providing control information (the 109
patents first step), while [a] transmitting, [b] storing or [c] retrieving the delay
value constitutes providing a signal to the memory device (the 109 patents
second step). Id. The Board did not address the fact that, for its first two

17
alternatives of transmitting or storing a delay value, Farmwald programs the
delay value into the DRAMs access-time register first, while the 109 patents
signal arrives separately after the write command. Nor did the Board address the
fact that its alternatives of storing the value in, or retrieving the delay value
from, the access-time register in Farmwald occur within a memory device, while
claim 1 requires a signal to the memory device. Id. (emphasis added). Instead,
in a footnote with no supporting citation, the Board asserted that a signal to the
memory device in the 109 patents claims could encompass providing the signal
from one part of the memory device to another part of it. A15 n.3 (emphasis
added).
2. The Board also rejected Rambuss argument that claim 1 of the 109
patent decouples the write command from the signal telling the memory device to
begin writing, with the command being sent first and a separate signal sent
seconda teaching not found in Farmwald. A10, A12. The Board acknowledged
(A13) that paragraph 1 of claim 1 recites that the control information includes a
first code which specifies that a write operation be initiated in the memory device,
and the next paragraph recites a subsequent signal to begin data transfer. A74,
41:65-67, 42:61. And the Board did not dispute that the 109 patents speci-
ficationunder the heading Decoupled Data Transfer Control Information
described the prior art in which the timing of data transfer is dictated by the

18
timing of the request for the data transfer, where the delay between them was (for
example) determined by a value stored in a register within the DRAM. A58,
10:25-37 (emphasis added). It recognized that the 109 patents specification
characterized that as inflexible.
The Board nevertheless concluded that claim 1 does not preclude the
recited signal from being sent in the same request packet as the write request.
A13-14. The Board relied primarily on the 109 patent specifications discussion
of an alternate embodiment operating without the use of strobe and terminate
signals. A58, 10:55-56. In that embodiment, the timing of data transfer could be
controlled by placing a delay value in the request packet together with the
control information (e.g., the read or write). A58, 10:52-60. The Board
rejected Rambuss argument that the alternate embodimentexpressly claimed in
the Barth 914 parent patentwas not claimed in the 109 patent because the 109
patent expressly distinguishes prior art that, like the alternative embodiment,
cannot decouple and uses delay values rather than signals.
The Board agreed that the 109 patent characterized such prior art as
inflexiblethe controller could not determine the timing of data transfer in light
of changing conditions after sending the write request. But the Board declared that
Farmwald is not inflexible because the controller could determine the delay
between the request and data transfer when the request is sent by sending a

19
request packet having a code for selecting different access-time registers each
storing a different delay value. A16.
3. The Board reversed the Examiners non-statutory double-patenting
rejections. A21-23. The Board stated that its affirmance of the rejection of all
claims as anticipated by Farmwald renders it unnecessary to reach other issues.
A23. The Board did not address the Examiners determination of non-
obviousness. A23. The 109 patent thus stands rejected on only one ground
anticipation.
C. The Rehearing Decision
The Board denied rehearing. The Board again identified four options that
purportedly catalogue different ways the delay value in Farmwald . . . corresponds
to the [109 patents] claimed signal: 1) the value comes from a request packet;
2) the value is stored in an access register; 3) the value is provided for comparison
to a clock; and/or 4) a value is used to generate another signal after match with the
clock. A17528. The lattermost options, the Board stated, simply explain how a
delay value constitutes a signal: i.e., 3) the memory device compares the delay
value number (a signal) to the clock, or 4) the new signal (a trigger) is created to
indicate the delay value number and the external clock match. A17529. [T]he
thrust of the Decision, the Board declared, is that Farmwalds delay value

20
embodiment satisfies the signal recited in claim 1 based on a similar embodiment
in the 109 patent. A17531; see A17526, A17533.
STANDARD OF REVIEW
We agree with the Board that the disputes [in this case] turn on claim
interpretation. A12. This Court reviews the Boards claim construction de novo.
Cybor Corp. v. FAS Techs., Inc., 138 F.3d 1448, 1456 (Fed. Cir. 1998) (en banc).
Anticipation is a question of fact reviewed for substantial evidence. In re Hyatt,
211 F.3d 1367, 1371-72 (Fed. Cir. 2000).
SUMMARY OF ARGUMENT
This case arises from the Boards ruling that the 109 patents claims are
anticipated by the very prior art that the 109 patent distinguishes. The Board did
not fully construe the 109 patents claims to determine their scope and then
compare those claims in detail to the Farmwald disclosures that allegedly
anticipated them. Instead, the Board simply equated the signal claimed in the
109 patent to control when data transfer occurs with the delay values disclosed
by Farmwald. But that truncated approach led the Board to ignore key features of
each technology, deeming the 109 patent anticipated even though it uses an
entirely different method, with parts distinct from, and that operat[e] in a
different way from, Farmwald. Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d
1359, 1370 (Fed. Cir. 2008).

21
I. The Board misconstrued the scope of claim 1 of the 109 patent in at
least two ways. First, the Board erroneously equated the 109 patents claimed
signal with a delay value. Rather than look to the claim language, the Board
relied on a dictionary definition to give signal an expansive meaningthe
physical representation of data. But the claim uses signal in a narrower sense to
mean a transmission that incites action. Where the claim means a different type of
transmission, it uses different terms like code and data. The specification
confirms those distinctions. The Board erred in adopting a definition of signal
that would obliterate the distinction between discrete claim terms that serve
different purposes.
Second, the Board erroneously dispensed with the 109 patents requirement
that the signal to begin data transfer be decoupled fromsent separate from and
subsequent tothe write command. The claim recites, in the first paragraph, a
first code specifying the write operation, followed by a second, separate
paragraph reciting the signal to begin sampling data. The specification confirms
the claims limitation of decoupling, explaining that the signal is sent separate
from and subsequent to the transmission of the command control information.
The Board nonetheless insisted that claim 1 must be read broadly to
encompass an alternate embodiment mentioned in the patent that describes
sending delay values in the request packet with the command control

22
information. But looking to the embodiment, rather than the claim, led the Board
astray. The alternate embodiment is not claimed by the 109 patentit is de-
scribed as operating without signals, the very thing claim 1 recites. Instead,
that delay value method is claimed in a parent patent also owned by Rambus, the
914 patent. The 914 patent, moreover, confirms the distinction between the de-
lay value method and a signal-based method by claiming them separately using
distinct terminology. And the 109 patent expressly distinguishes Farmwalds
register-based delay value method.
II. The Board independently erred regarding anticipation. The Board
identified four options (and possible combinations thereof) that purported to
catalogue how Farmwald might anticipate by using a delay value in a fashion
similar to the 109 patents use of a signal. Farmwalds delay value, the Board
stated, is either: (1) in the request packet; (2) stored in an access-register;
(3) provided for comparison to a clock; and/or (4) implicitly used to generate
another implicit signal after the comparison to signify a match. A13 (emphasis
added). But that catalogue is divorced from Farmwalds actual disclosures.
None of the options anticipates the 109 patents signal, even if claim 1 is
(incorrectly) construed as encompassing the alternate delay-value embodiment.
The Boards first option fails because Farmwald nowhere discloses sending
a delay value in the request packet with the write command. Rather, Farm-

23
wald discloses sending delay values to, and storing them in, the DRAMs access-
time register before the write command is transmitted. Farmwald thus discloses a
method requiring additional components and steps not required by the 109 patent.
The Boards remaining optionsstor[age] in an access-register, provided for
comparison to a clock, and/or implicitly used to generate another implicit signal
upon the delay times lapseare events within the memory device (DRAM
includes the access-time register) that cannot meet the 109 patents limitation of
providing a signal to the memory device. The Boards decision also suggests
that some combination of its four options may anticipate the 109s signal. But
the Board nowhere identified any specific combination, much less explained where
that combination is disclosed in Farmwald or how it would actually operate.
Because the Board failed to identify substantial evidence that Farmwald discloses
every claim element and limitation in the same form and order as the 109
patent, Abbott Labs. v. Sandoz, Inc., 544 F.3d 1341, 1345 (Fed. Cir. 2008), its
decision must be reversed.
ARGUMENT
The Board made three fundamental errors in finding the 109 patent
anticipated. First, the Board erred as a matter of claim construction in construing
the recited signal in claim 1 of the 109 patent broadly to encompass a delay
value. Second, the Board committed an independent claim construction error

24
when it dispensed with claim 1s requirement that its signal be decoupled from,
and sent subsequent to, the command specifying the write operation. Third, the
Board erred in finding anticipation by listing 4 possible options (and perhaps
some combination thereof) for how Farmwalds delay value might correspond to
the recited signal in claim 1, without ever explaining where those options are
disclosed or how they operate in Farmwald, and without establishing that those
options satisfy all the limitations of the 109 patents claims and are arranged as in
the 109 patent. The first two errors are primarily addressed in Section I below;
the third error in Section II.
I. Farmwalds Delay-Value Method Does Not Anticipate the 109 Patents
Use of a Separate and Later Signal
Anticipation analysis ordinarily begins with a construction of the patents
claims, focused on the claim language and informed by the patents specification.
It then makes a detailed comparison of the claims with the disclosures in the prior
art. Enzo Biochem, Inc. v. Applera Corp., 599 F.3d 1325, 1332 (Fed. Cir. 2010),
cert. denied, 131 S. Ct. 3020 (2011). The Board did not do that here. Instead, the
Board jumped straight to determining whether or not the recited signal in claim
1 [of the 109 patent] embraces a delay value as described in Farmwald.
A17525. The Boards focus[ ] on that issue drove its analysis, at the expense of
carefully examining the 109 patent itself. That resulted in the Board misconstru-
ing two basic limitations of claim 1:

25
Claim 1 of the 109 patent recites a signal indicating that the DRAM is
to begin sampling data. That signal cannot be conflated with Farm-
walds delay value, which is stored in a register, and which represents
how long the DRAM should wait before beginning to sample.
Claim 1 of the 109 patent requires the signal controlling the timing of
data transfer to be decoupled from, and sent subsequent to, the command
specifying the operation. By contrast, in Farmwald, the timing of data
transfer is determined at the same time the operation is specified.
The Boards contrary constructions defeat the advantages the 109 patent provides
over the prior art.
A. Claim 1 Recites a Method Using a Decoupled and Subsequent
Signal To Initiate Data Transfer
Claim construction begins with the words of the claim. Teleflex, Inc. v.
Ficosa N. Am. Corp., 299 F.3d 1313, 1324 (Fed. Cir. 2002). Those words are
generally given their ordinary and customary meaning, as a person of ordinary
skill in the art in question at the time of the invention would have understood
them. Phillips v. AWH Corp., 415 F.3d 1303, 1312-13 (Fed. Cir. 2005) (en banc)
(quotation marks omitted). On reexamination, claim terms are given their broad-
est reasonable construction; what is reasonable, however, must take into ac-
count the specification and teachings in the underlying patent. In re Suitco Sur-
face, Inc., 603 F.3d 1255, 1260 (Fed. Cir. 2010). The specification is highly rele-
vant to the claim construction analysis. Usually, it is dispositive; it is the single
best guide to the meaning of a disputed term. Phillips, 415 F.3d at 1315 (quota-
tion marks omitted).

26
1. The Claim Language
Claim 1 of the 109 patent recites a multi-step process for controlling a write
operation by a memory device, in which the controller (1) first sends to the
memory device command control information specifying a write operation,
followed by (2) a separate or decoupled signal from the controller telling the
memory device when to begin the data transferi.e., do it now. Claim 1 recites
a method of controlling a memory device by:
[1] providing control information to the memory device, wherein
the control information includes a first code which specifies
that a write operation be initiated in the memory device;
[2] providing a signal to the memory device, wherein the signal
indicates when the memory device is to begin sampling write
data, wherein the write data is stored in the memory core during
the write operation;
[3] providing a first bit of the write data to the memory device
[4] providing a second bit of the write data to the memory device
during an odd phase of the clock signal.
A74-75, 41:62-43:2 (numbering added for reference).
Claim 1 requires that the control information be provided to the memory
device from the controller. Claim 1 nowhere suggests that it might encompass the
transfer of information within the memory device. The sequential nature of the
claim steps that implement that method, moreover, is apparent from the plain

27
meaning of the claim language and its structure. Mantech Envtl. Corp. v. Hudson
Envtl. Servs., Inc., 152 F.3d 1368, 1376 (Fed. Cir. 1998).
Paragraph [1] states that the first code sent to the memory device
specifies that a write operation will be performed. For that to be the first code,
the other steps recited in claim 1 cannot precede it.
Next, Paragraph [2] recites the second and separate step of providing a
signal to the memory device, wherein the signal indicates when the memory device
is to begin sampling write data, wherein the write data is stored in the memory core
during the write operation. A74, 42:61-64. That signal is distinct from the first
code in Paragraph [1]it does not specif[y] the write operation, A74, 41:65-66,
and necessarily comes after the first code. Rather, the signal governs the timing
of data transferwhenby telling the memory device when to begin sam-
pling (i.e., the data-transfer step of the write operation) previously specified by the
first code. A74, 41:65-66, 42:62-63.
The first code recited in the methods first step thus operates like the
announcement On your marks! that tells a sprinter to poise to begin his race:
Upon receiving the command control information specifying a write, the DRAM
performs preparatory functions, making it poised to act. And the signal recited
in the methods second step is like the gun that tells the sprinter to start running:

28
At a moment of the memory controllers choosing, the signal to begin sampling
data is sent and the DRAM begins sampling in response.
The remaining paragraphs complete the sequence. Paragraph [3] recites
providing a first bit of the write data to the memory device during an even phase
of a clock signal. A74, 42:66-67. And Paragraph [4] describes the continuation
of that process, i.e., providing a second bit of the write data to the memory device
during an odd phase of the clock signal. A75, 43:1-2. Thus, it is clear as a
matter of logic [and] grammar that the steps in claim 1 of the 109 patent must
be performed in the order written and cannot be conflated. Altiris, Inc. v.
Symantec Corp., 318 F.3d 1363, 1369 (Fed. Cir. 2003).
2. The Specification
a. Decoupling
The invention by its terms requires decoupling, or separate transmission
of the command and the signal to begin data transfer. The specification repeatedly
distinguishes command control information (e.g., write) and data transfer
control information (the signal governing when data is transferred). And the
specification repeatedly emphasizes that claim 1s signal must be separate from the
command control information. Indeed, the inventions first cited object . . . is to
provide a mechanism to decouple control timing and data timing, so the controller
can provide the command control information first and later decide when the

29
DRAM should transfer the data. A55, 3:34-35 (emphasis added). The specifica-
tion thus explains that the DRAM is configured to start and end the transmission
of data based on data transfer control information sent by the controller to the
DRAM separate from and subsequent to the transmission of the command control
information. A57, 8:239:1-2 (emphasis added).
Indeed, the portion of the specification central to this casewhich distin-
guishes prior artbears the heading: Decoupled Data Transfer Control Informa-
tion. A58, 10:25 (emphasis added). It states: [T]he data transfer control infor-
mation which controls the timing of the data transfer associated with a request
packet is sent separately from the command control information to which it
corresponds. A58, 10:41-43 (emphasis added). Decoupling is emphasized
throughout the specification. See, e.g., A58, 9:26-27 (transmitting data transfer
control information separate[ly] from the command control information).
b. Signal
Claim 1s signal to the DRAM tells it to begin sampling data for the oper-
ation previously specified. The signal does not specify how long to wait (like a
countdown) before sampling; rather, it is a signal to begin sampling (like a starting
gun). The primary embodiment describes it as a strobe signal providing data
transfer start information . . . sent from the controller to indicate when the DRAM is
to begin sending data. A58, 9:4-6. The specification thus discusses the con-

30
trollers transmission of the strobe signal to begin the transfer specified. A58,
10:48-49. Similarly, in describing the control functions performed in a read
operation, the specification states that [t]he timing of the strobe signal indicates
to the DRAM when the DRAM is to begin retrieving and sending data for [the]
transaction, because the DRAM begins to receive data from the specified col-
umns and begins sending the data over BusData lines [i]n response to the
strobe signal. A64, 21:31-36 (emphasis added). Thus, [t]he timing of the strobe
signal itselfnot some aspect of the signals contentstells the DRAM when to
begin the data transfer. A64, 21:31-33. The DRAM begins to retrieve data . . .
and begins sending the data [ i]n response to the strobe signal. A64, 22:48-53;
see also A58, 9:35-37; A59, 11:38-44; A64, 21:57-60, 21:60-64; A65, 23:66-24:5.
The terminate signal makes that clearer still. Just as an event can have a
starting signal, it can have an end signal (e.g., the referees whistle). Claim 7 of
the 109 patent recites a terminate signal that causes the DRAM to initiate
termination of the data transfer. A58, 9:62-63 (emphasis added); see also A64,
21:41-43 ([t]he timing of the terminate signal indicates to the DRAM when to
stop sending data), 21:43-44 (In response to the terminate signal, the DRAM
ceases to retrieve data . . . .). The signal recited in claim 1 operates in the same
manner: The specification explains that the two signals have identical character-
istics. A60, 14:11-13. Just as claim 1s signal indicates start now, the

31
terminate signal indicates stop now. Neither claim term suggests start or stop
after a specified delay. Moreover, neither claim term suggests to look to an access-
time register to read its contents, and then start or stop that many clock cycles later.
Finally, the specification explains thatalthough some strobe [signal]-to-
data delay is intrinsic to the circuitone benefit of the 109 patent is reducing
the delay between the transmission of (1) a strobe signal for a transfer operation
and (2) the first packet in the transfer operation. A58, 9:41-46. That would make
little sense if the recited signals did not indicate that an operation was to begin (or
end) upon receipt of the signal, but instead to insert some further delay between the
signals receipt and execution.
That straightforward understanding of signal reflects ordinary usage. As
Websters explains, a signal means something that incites to action: an immedi-
ate cause or impulse. Websters Third New Intl Dictionary 2115 (2002). And
the specification uses signal consistently throughoutwhether with regard to
initiating or terminating sampling in read and write operationsto mean that
which incites an action by the DRAM.
c. The Distinction and Critique of the Prior Art Patent
Far from claiming the method disclosed in Farmwald, the 109 patent distin-
guishes itexplaining how the 109 patent is decidedly different, and decidedly
more flexible.

32
As noted above, Farmwald teaches a method of controlling a DRAM that
includes access-time registers that store delay values. JA17603, 6:40-45. The
values in the registers preferably are set as part of an initialization sequence that
occurs when the system is powered up or reset. JA17603, 6:46-48; see also
JA17614, 27:32-39 (claim 28). Laterafter receiving a read or write command
the DRAM uses that previously stored value to control timing, as the Examiner and
the Board both recognized. JA10993 (the memory device in Farmwald relies
upon the previously received [delay] value to control timing) (emphasis added);
A12 (delay value stored in, and thereafter retrieved from, an access-time
register) (emphasis added). The time after which the DRAM begins data
transfer is selected from values stored in slave access-time registers in the
DRAM. JA17605, 9:23-25.
In Farmwald, the controller sends command control information (an op
code) that specifies a read or write operation to the DRAM and also determines
which access-time register will be used. JA17605, 9:66-10:5. Thus, there are
limited choices for data transfer timing. The range is determined first, when the
DRAMs access-time registers are initialized and delay values stored therein.
The controller then determines the timing of data transfer through the selection of
an op code and a corresponding access-time register when it sends the command
control information (e.g., the write command). Because the system uses delay

33
values, the timing of data transfer is relative toa specified delay time
followingthe DRAMs receipt of the request. Farmwald thus teaches issuing an
operation code [that] specifies a write operation, in which the data is output to
the memory device after a delay time transpires. JA17614, 27:9-20 (emphasis
added).
The sequence in the 109 patent is differentwith good reason. The Barth
teams goal was to improve on Farmwalds method, increasing speed, flexibility,
and precision. In claim 1, the first code sent to the DRAM is the control informa-
tion specifying the write operation (Paragraph [1]), followed by a separate signal to
begin data transfer (Paragraph [2]). By contrast, Farmwald begins with delay
values being stored in the DRAMs access-time registers on initialization. The
109 patents signal governing data transfer is decoupled fromit is sent separ-
ately fromthe control information specifying a write operation. In Farmwald,
the controller determines data timing by selecting an access-time register when the
write operation is specified. Because the 109 patents signal itself initiates data
transfer, sampling in the 109 patent begins at a time that is independent of when
the command control information (the write command) is sent. Farmwald is
different: It stores delay values that set the time for data transfer relative to the
DRAMs receipt of the command control information.

34
Consequently, the 109 patent provides for the controller to send a signal
to begin data transfer that differs from Farmwalds delay values in function,
timing, sequence, location, and further processing. Unlike the prior art, the 109
patents signal:
Indicates a startnot a delay period relative to the write request;
Is sent to the memory device after the write request, not before;
Is sent separate from the write request (decoupled), not with it;
Is sent right before the data to be written;
Is not stored in access-time registers within the DRAM for later use;
Is not retrieved within the DRAM; and
Is not limited by previously stored values associated with particular op
codes.
Indeed, the 109 patent expressly distinguishes Farmwalds method and
explains the 109 patents advantages. In the section titled Decoupled Data
Transfer Control Information, the 109 patent explains:
In prior art systems, the timing of a data transfer is dictated by the
timing of the request for the data transfer. Thus, given that a transfer
request arrived on a particular clock cycle, it was known that the data
specified in the request would begin to appear on BusData[8:0] a
predetermined number of clock cycles from the particular clock cycle.
For example, the number of clock cycles that elapse between a request
packet and the transfer of data specified in the request packet may be
determined by a value stored in a register within the DRAM. This
fact renders prior art systems inflexible with respect to how control
and data signals may be interleaved to maximize the use of the
channel.

35
A58, 10:25-39.
The specification explains that one disadvantage of Farmwald is that the
timing between requests and data transfers is fixed at the time the request is sent,
and thus controllers cannot make interleave adjustments . . . in response to chang-
ing conditions in the system. A59, 11:16-21 (emphasis added). By comparison,
the 109 patent decouples the write command from the signal to begin data trans-
fer, so data transfer control information which controls the timing of the data
transfer associated with a request packet is sent separately from and subsequent
to the command control information to which it corresponds. A57-58, 8:65-9:2,
10:41-43. As a result, the controller can dynamically adjust the interleave to
maximize the use of the channel in response to changing conditions on the system
after the request is sent in variations that were not previously possible. A59,
11:22-28. The 109 patent therefore characterizes the prior art as inflexible.
Because Farmwalds disclosure relies on a limited number of delay values
previously stored in access-time registers, moreover, the interleave patterns were
limited to those made possible by those already-stored delay valuesthat is, the
controller might only be able to choose between delays of, for example, 1, 4, 8, and
12 clock cycles. See, e.g., JA17606, 11:30-39 (showing 4 register values). By
contrast, the 109 patent allows the controller to send a signal whenever it deter-

36
mines data transfer should begin. As a result, the options for interleave patterns
are virtually limitless. A59, 11:24-26.
Where the patentee distinguishe[s] th[e] term[s] of its claim from the
prior art, it is inappropriate to construe those terms to encompass the prior art.
CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002). That
is the case here. There can be no serious dispute that the prior art the 109 patent
identifies and distinguishes is Farmwald. Like the prior art the 109 patent dis-
tinguishes, Farmwald teaches the use of delay value[s] stored in a register within
the DRAM. A58, 10:35-36; A17603, 6:40-48. Like the prior art the 109 patent
distinguishes, Farmwald provides for outputting the data to the memory device
after a delay time transpires. JA17614, 27:19-20; see also JA17605, 9:23-25.
Even NVIDIA, the third-party requester in this reexamination, agreed that the prior
art the 109 patent distinguishes is the Farmwald delay-value system. A13885.
The ITC reached the same conclusion. JA13884-85. The Board nowhere suggests
any other prior art it might refer to.
Ultimately, the interpretation to be given a term can only be determined and
confirmed with a full understanding of what the inventors actually invented and
intended to envelop with the claim. Renishaw PLC v. Marposs Societa per
Azioni, 158 F.3d 1243, 1250 (Fed. Cir. 1998); see also Medrad, Inc. v. MRI De-
vices Corp., 401 F.3d 1313, 1319 (Fed. Cir. 2005). The 109 patents specification

37
could not be clearer that claim 1s method of controlling timing through a signal
sent separate from and subsequent to the write request is not intended to envelop
Farmwalds register-based delay value system, which it expressly distinguishes
as inflexible prior art.
B. The Board Erred in Construing the 109 Patent To (1) Encompass
the Use of Delay Values and (2) Dispense With Decoupling
The Boards contrary conclusionthat the claimed signal reads on Farm-
walds . . . delay value embodiment, A17533misconstrues the 109 patents
claims. The Boards broadest reasonable construction standard does not give it
an unfettered license to interpret claims to embrace anything remotely related to
the claimed invention. Rather, claims should always be read in light of the specifi-
cation and teachings in the underlying patent. Suitco, 603 F.3d at 1260. The
Boards failure to do that resulted in at least two independent errors.
First, the Board construed the 109 patents claimed signal to en-
compass a delay value, even though the claims and specification make
clear that the signal is not a value indicating the amount of time to
delay but rather a signal to begin data transfer.
Second, the Board read the 109 patent claims as permitting the signal to
be sent together with the write request, even though the claims make
clear that it must be sent separately from and subsequent to that
request.
Indeed, under the Boards construction, the 109 patent would claim the prior art
method the patent distinguishes. Rather than reading the claims and specification
together, the Boards analysis relied on a dictionary definition and an alternate

38
embodiment, mentioned in just two paragraphs, and claimed in a parent
application but not in the 109 patent.
1. The Board Erred by (1) Interpreting the Term Signal Out
of Context and (2) Relying on an Expansive Dictionary
Definition of That Term
The Boards analysis begins by isolating the word signal and noting that
one of the definitions of signal in the IEEE Standard Dictionary is the physical
representation of data. A10. Based on that, the Board concluded that the 109
patents step of providing a signal could encompass Farmwalds delay value.
A13-14. But this Court has expressly rejected such a begin-with-the-dictionary ap-
proach to claim construction. Phillips, 415 F.3d at 1320. In Phillips, the en banc
Court explained that extrinsic evidence like dictionary definitions are less
reliable than the patent and its prosecution history in determining how to read
claim terms. Id. at 1318. And it warned that, if the Board starts with the broad
dictionary definition . . . and fails to appreciate how the specification implicitly
limits that definition, the error will systematically cause the construction of the
claim to be unduly expansive. Id. at 1321.
6

____________________________
6
Dictionary definitions are particularly unhelpful where a term has multiple
ordinary and accustomed meaning[s]. Teleflex, 299 F.3d at 1325. That is true
regarding signal, for which the IEEE Standard Dictionary offers nine definitions
(and ordinary dictionaries offer still more). A claim should not rise or fall based
upon the Boards decision, uninformed by the specification, to rely on one
dictionary [definition]. Phillips, 415 F.3d at 1322.

39
Precisely that happened here. Rather than analyze the way signal is used
in claim 1 and throughout the 109 patent, the Board began with a dictionary
definition so broad that every communication between controller and DRAM
across the busany physical representation of datais a signal. See A9-10.
That reading would convert every step, every paragraph of claim 1, into step twos
signal, because the write command and the data transferred likewise can be
characterized as the physical representation of data. And in the prior art, any of
those could be used to initiate sampling.
But claim 1 deliberately uses different terms. Paragraph [1] recites pro-
viding a code indicating a write command. It does not recite providing a sig-
nal, because the inventors meant for content to be transferred, i.e., the command
to be performed. Paragraph [2] recites providing a signalnot a code
because the inventors were not calling for the provision of content or values
but a signal to begin. And Paragraphs [3] and [4] recite providing a third item
data. The inventors used the term data to differentiate data to be processed
from a code regarding how to process it, and from the signal to begin its
transfer.
The specification confirms that the signal functions differently from the
code in Paragraph [1] and the data in Paragraphs [3] and [4]. It does not
convey a command, data, or values. As the specification makes clear, signal

40
refers to the controllers indication to the DRAM that it is to begin the transfer
specified, A58, 10:48-49 (emphasis added), or take action [i]n response to the
signal, A64, 21:33-35 (emphasis added); pp. 29-31, supra. That is how signal is
often used. See p. 31, supra. And far from equating signal with value, the
specification distinguishes them, saying signal when it means signal and val-
ue when it means the communication of a quantitative figure, including when it
refers to a delay value.
7

If the term signal had the expansive dictionary-definition meaning the
Board attributed to itas encompassing any physical representation of data,
including a valuethe claim would have recited the code, signal, and data
all as signals. The inventors, however, used those three different terms to
describe three different things. This Court must presume that the use of these
different terms in the claims connotes different meanings. CAE Screenplates Inc.
v. Heinrich Fiedler GmbH & Co. KG, 224 F.3d 1308, 1317 (Fed. Cir. 2000); see
also Bancorp Servs., L.L.C. v. Hartford Life Ins. Co., 359 F.3d 1367, 1373 (Fed.
Cir. 2004). By starting and ending with the broad dictionary definition, the
Board improperly focused the inquiry on the abstract meaning of words rather
____________________________
7
Throughout the 109 patent, the term value consistently denotes a representa-
tion of data, not an indication to begin an operation. (See, e.g., A57, 7:9-35 (Pend
value); A62, 17:41-42 (value of the broadcast bit); A62, 18:41 (value of the
Open and Close bits).

41
than on the meaning of claim terms within the context of the patent. Phillips, 415
F.3d at 1321.
2. The Board Erred by Dispensing with Decoupling
The Board also disputed whether claim 1 decouples the command control
information (write) from the signal (which governs when data transfer begins).
It did not deny that claim 1 recites those as separate steps in separate paragraphs,
with command control information first and data transfer control information
second. But the Board urged that, because claim 1 recites that the control
information includes a first code, and the 109 patents specification sometimes
refers to the signal as providing control information, the signal governing
timing might be sent as control information recited in Paragraph [1]. A13-14.
The specification does variously refer to command control information
and timing control information. But the specification also makes clear that the
control information recited in step 1 of claim 1 refers only to command control
information: The command control information includes the operation code
i.e., the first codefollowed by an address in the DRAM for the data transfer.
A57, 7:1-14. Nowhere does the 109 patent suggest that the signal governing
timing, recited in the separate step 2 of claim 1, may be included in the initial
transmission of control information in step 1. If it did, there would have been no

42
point to making the providing a signal step in Paragraph [2] a separate paragraph
and separate step.
The advantages the 109 patent recites, moreover, are predicated on de-
coupling command control information from the signal. See pp. 33-36, supra. For
example, the specification repeatedly describes the benefits of decoupling:
Because there is no fixed time period between when the command
control information is sent and when the signal indicating that the DRAM
should begin sampling data is sent, the controller is free to adjust the
timing . . . as needed to provide the desired interleave in response to
changes in conditions on the system after the command control
information has been sent. A57, 7:63-67.
The controller thus can vary the timing of the transmission of data on
the fly, in variations that were not previously possible, A59, 11:22-26
(emphasis added), allow[ing] the channel to be used for other purposes
prior to the transmission of data, A65, 23:37-42.
Decoupling thus represents the essence of the 109 patents advance, and a
key basis for distinguishing the prior art in which the timing was fixed when the
request was sent. The Board erred in interpreting the 109 patent to exclude the
very heart of the inventors device. Modine Mfg. Co. v. U.S. Intl Trade
Commn, 75 F.3d 1545, 1550 (Fed. Cir.), cert. denied, 518 U.S. 1005 (1996).
3. The Board Erred in Relying on an Alternate Embodiment
Not Claimed in the 109 Patent But Claimed in Another
Rambus Patent
Ultimately, the Boards primary reason for finding Farmwald anticipating
was one of many embodiments identified in the 109 patents specification (which

43
discloses at least eight inventions). That alternate embodimentmentioned in
only two of the specifications 124 paragraphsoperates without the use of
strobe and terminate signals. A58, 10:55-56 (emphasis added). It is described as
utilizing
a [request] packet [that] contains a delay value that indicates to the
DRAM when the data specified in the request packet will begin to be
sent relative to the time at which the request packet is sent. The
DRAM would include a counter to count the clock cycles that elapse
from the arrival of the request packet in order to send or receive the
data specified in the request on the appropriate clock cycle.
A58, 10:52-64.
The Board invoked that embodimentwhich it characterized as a delay
value embodimentto drive its analysis. The Boards description of the 109
patent began not with the claims, but with the assertion it has at least two
embodiments, including the alternate delay value embodiment. A3-5. Invoking
that alternate embodiment repeatedly, see A5, A7-8, A11-12, A13, A15, A16, A17,
A18, the Board insisted that claim 1 must be read to include itand sending a
signal therefore had to encompass sending a delay valuebecause claims
rarely exclude disclosed embodiments. A9, A13-14, A16-18. [T]he 109 patents
delay value embodiment the Board summarized, supports the Examiners claim
interpretation under which the claimed signal reads on Farmwalds similar delay
value embodiment. A17533.

44
But a proper anticipation analysis proceeds in two steps: (1) interpretation
of the claims (2) followed by a detailed comparison of the claims with the
disclosures in the prior art. See Enzo, 599 F.3d at 1332. That did not occur here.
Instead, the Board assumed an unclaimed embodiment was covered by claim 1 of
the 109 patent, and then spent much of its opinion comparing that unclaimed em-
bodiment with one of Farmwalds embodiments. In doing so, the Board lost focus
on what the claims actually covered, and what the 109 patents invention was.
a. The Claim and Specification Exclude the Alternate
Embodiment
Claim 1 would not read on Farmwald even if it encompassed the alternate
embodiment. See pp. 50-60, infra. But the Board overlooked the more fundamen-
tal rule that the claims of the patent need not encompass all disclosed embodi-
ments. TIP Sys., LLC v. Phillips & Brooks/Gladwin, Inc., 529 F.3d 1364, 1373
(Fed. Cir.), cert. denied, 555 U.S. 1046 (2008); see also Teleflex, 299 F.3d at 1326
(That claims are interpreted in light of the specification does not mean that
everything expressed in the specification must be read into all the claims.) (quo-
tation marks omitted). This Courts precedent is replete with examples of subject
matter that is included in the specification, but is not claimed. Id.; see, e.g.,
August Tech. Corp. v. Camtek, Ltd., 655 F.3d 1278, 1285 (Fed. Cir. 2011); John-
son & Johnston Assocs. Inc. v. R.E. Serv. Co., 285 F.3d 1046, 1054 (Fed. Cir.

45
2002) (en banc). That is particularly common where, as here, claims in the parent
patent cover the excluded embodiment[ ]. August, 655 F.3d at 1285.
The language of claim 1 of the 109 patent excludes sending a delay value
coupled with the request. See pp. 26-28, supra. It recites providing a signal to
the memory device, wherein the signal indicates when the memory device is to
begin sampling write data. A74, 42:61-63 (emphasis added). But the delay value
embodiment is expressly described as operating without the use of strobe or ter-
minate signals. A58, 10:55-56 (emphasis added). The alternate embodiment
discusses sending a [request] packet that contains a delay value. A58, 10:57-
58. But the phrase delay value is not found in any portion of the 109 patents
specification describing the claimed signal. Instead, delay value is used when
describing and distinguishing the prior art. See A58, 10:33-37. The claim thus
carefully distinguishes between signals and other transmissions in each of its
steps, see p. 39, supra, and the specification distinguishes signals and values
as well, see pp. 39-40 & n.7, supra. Moreover, the alternate embodiment is
inconsistent with claim 1s requirement that the signal be decoupled from the
command control information; the alternate embodiment expressly sends them
together. A58, 10:52-64.
It is because of those limitationsthe signal is a signal, not a value, and
must be decoupledthat the alternate embodiment falls outside the claim.

46
Inverting that, the Board used the alternate embodiment to broaden the claim and
reject those limitations, stating that a claim interpretation that would exclude the
inventors device is rarely the correct interpretation. A17 (quoting Modine, 75
F.3d at 1550). But that begs the question as to what constitutes the invention.
Here, excluding the delay value embodiment from claim 1 presents little cause for
concern, August, 655 F.3d at 1285, because the signal-based method that is the
109 patents advance remains. And it is of particularly little moment given that
the alternate embodiment is claimed in a parent patentwhich is precisely why it
did not need to be claimed in the 109 patent.
b. Rambuss 914 Patent Claims the Delay Value
Embodimentthe 109 Patent Does Not
The parent of the 109 patentPatent No. 5,748,914makes it clear that
the 109 patent does not claim the alternate embodiment. The 914 patent claims
the alternate embodiment expressly. It does so in specific terms, distinguishing the
signal-based method from the use of delay values. Under the doctrine of claim
differentiation, that removes any doubt that the claimed signal in the 109 patent
does not encompass the delay value embodiment.
The 914 patents claims are clear. Claim 6 of that patent recites [a]
method, for use in a memory controller, for maximizing usage of a bus that
connects the memory controller to one or more memory devices. A17658, 43:36-
52. Claims 7 and 8 provide different methods of communicating when data

47
transfer is to begin. In claim 7, the transmission of start information is performed
by transmitting a delay value in the control information, the delay value indi-
cating when the data transfer operation is to begin relative to the time at which the
control information is transmitted over the bus. A17658, 43:53-57 (emphasis
added). In claim 8, that function is performed by transmitting a strobe signal a
selected number of clock cycles after transmitting the control information, wherein
the number of clock cycles is determined based on how much time must elapse
between transmission of the control information and the start of the data transfer
operation to provide the interleave pattern. A17658, 43:58-64 (emphasis added).
The 914 patents claims thus fatally undermine the Boards construction
here. Because claim 7 of the 914 patent expressly claims the delay value
embodimentreciting the transmi[ssion of] a delay value in the control
informationthe exclusion of that embodiment from the 109 patent is little
cause for concern. August, 655 F.3d at 1285. Even in ordinary cases, [t]he mere
fact that there is an alternative embodiment . . . that is not encompassed by [the]
claim construction does not outweigh the language of the claim, especially when
the courts construction is supported by the intrinsic evidence. Id. (quoting TIP
Sys., 529 F.3d at 1373). But that is especially true where, as here, . . . claims in the
parent patent cover the excluded embodiments. Id.

48
Under the doctrine of claim differentiation, moreover, different words or
phrases used in separate claimsin a single or related patentare presumed to
indicate that the claims have different meanings and scope. Andersen Corp. v.
Fiber Composites, LLC, 474 F.3d 1361, 1369 (Fed. Cir. 2007) (quotation marks
omitted); see also Omega Engg, Inc., v. Raytek Corp., 334 F.3d 1314, 1334 (Fed.
Cir. 2003) (rule applicable to terms in the same patent or related patents). The
914 patent separately claims a delay value methodessentially, the alternate
embodiment mentioned in the 109 patentas one method of controlling timing
and as distinct from a signal-based method. If the 109 patent were intended to
claim that delay value embodiment, it would have used similar language, reciting
transmission of a delay value in the control information. It would not invoke the
language of a signal used to convey a different methodology. The Board erred in
failing to give the different terms their different meanings.
4. The Boards Rationale for Rejecting the 109 Patents
Distinction of Prior Art Fails
The Board did not directly dispute that the prior art the 109 patent
distinguishesand deems inflexibleis the Farmwald patent the Board found
anticipating. Nor did the Board identify other prior art the 109 patent might have
been distinguishing. Instead, the Board urged that Farmwald is not inflexible.
A15-16. According to the Board, Farmwald is flexible because the controller
can vary the latency between the request packet and the data transmission by

49
selecting different registers with different delay values, thereby adjusting inter-
leave on the channel. Id.
That misses the point. Flexible and inflexible are relative terms. The
109 patents specification was not asserting that Farmwald is inflexible in the
abstract, nor would it: Farmwald represented an advance over the even less flexi-
ble prior art that preceded it. See pp. 5-8, supra. Rather, Farmwald is inflexible
relative to the 109 patent in at least two key respects: (1) Because Farmwald does
not decouple, the timing of data transfer is tied to the timing of the write request
and cannot be altered thereafter; and (2) Farmwald has a confined set of delay
choices determined by a limited number of access-time registers and op codes.
That renders Farmwald relatively inflexible because (among other things) the
timing between requests and data transfers is fixed once the request is sent. A59,
11:16-21. The 109 patent, by contrast, decouples the timing signal from, and
sends it subsequent to, command control information, allowing the controller to
alter the timing of data transfer in response to changing conditions on the system
after the request is sent. A58, 10:41-44, 10:47-50; A59, 11:22-26. That additional
flexibility ma[d]e it possible to interleave . . . in variations that were not previously
possible. A59, 11:22-26.
The Board also urged that Farmwald could not be inflexible because it is
similar to the 109 patents delay value embodiment. A16. But that is circular:

50
The question before the Board was whether the delay value embodiment is
claimed in the 109 patent. Stating that the delay value embodiment shares
Farmwalds inflexibilityit does not decouple command information from the
timing signal and instead fixes data transfer timing when the command is sent, see
A58, 10:57-60is one reason the 109 patent must be read to exclude it.
The Boards focus on the word inflexible, moreover, caused it to lose sight
of the larger point: The 109 patent specifically distinguishes prior art utilizing
delay value[s] stored in a register within the DRAM. A58, 10:35-36. That
describes Farmwald precisely. See pp. 6-8, supra. Because the 109 patent
distinguished th[e] term[s] from prior art, it was error for the Board to interpret
claim 1 of the 109 patent to encompass that very same prior art. CCS Fitness, 288
F.3d at 1366.
II. Even if the Boards Construction That Signal Encompasses Value
and Rejecting Decoupling Were Correct, Farmwald Still Does Not
Disclose All the Elements of the 109 Patents Claims in the Same
Arrangement
Even if the Boards claim construction were correct, its finding of antici-
pation also fails for other, independent reasons. [U]nless a reference discloses
within the four corners of the document not only all of the limitations claimed but
also all of the limitations arranged or combined in the same way as recited in the
claim, it cannot be said to prove prior invention of the thing claimed and, thus,
cannot anticipate under 35 U.S.C. 102. Net MoneyIN, 545 F.3d at 1371; see

51
also Abbott, 544 F.3d at 1345. Put differently, claims cannot be treated . . . as
mere catalogs of separate parts, in disregard of the part-to-part relationships set
forth in the claims and that give the claims their meaning. Lindemann Maschin-
enfabrik GMBH v. Am. Hoist & Derrick Co., 730 F.2d 1452, 1459 (Fed. Cir.
1984).
Rather than examine[ ] the [prior art] reference in some detail, Finisar
Corp. v. DirecTV Group, Inc., 523 F.3d 1323, 1335 (Fed. Cir.), cert. denied, 555
U.S. 1070 (2008), the Board hypothesized four options (and possibly multiple
combinations thereof) that supposedly catalogue the different ways the delay
value in Farmwald . . . corresponds to the claimed signal in the 109 patent.
A17528. Farmwalds delay value, the Board stated, is either: (1) in the request
packet; (2) stored in an access-register; (3) provided for comparison to a clock;
and/or (4) implicitly used to generate another implicit signal after the comparison
to signify a match. A13 (emphasis added). But the Board did not cite evidence
let alone substantial evidenceto show how any one of those four options
anticipates the signal as it appears in the sequence set forth in the 109 patents
claims. Moreover, despite its use of the terms either and and/or, the Board
nowhere explained or provided evidence to support which of the 16 possible
combinations anticipated the claimed signal. Respectfully, the Board is not free to
list 4 to 16 possible options and explain none.

52
1. Option (1): In the Request Packet
The Board stated, as the first of its four options, that Farmwald anticipates
the 109 patent by placing the delay value . . . (1) in the request packet, just like
the (unclaimed) alternate embodiment in the 109 patent. A13; A14 (delay value
within a request packet); A17527 (request packet delay value signal option).
But that misreads Farmwald. Farmwald never discloses placing a delay
value in the request packet with the command (e.g., the write), as the alternate
embodiment proposes. Instead, as the Examiner and the Board elsewhere recog-
nized, Farmwalds delay values are transmitted to the DRAM access-time registers
and stored there before the request is sent (upon initialization); they are not in the
request packet. See JA10993 (the memory device in Farmwald relies upon the
previously received [delay] value to control timing); A12 (delay value stored in,
and thereafter retrieved from, an access-time register); see p. 32, supra. The
information in Farmwalds request packet (the op code) indicates the operation
and directs the memory device to find a previously stored delay value in the
DRAMs access-time register. JA17605, 9:63-10:1; see also pp. 7-8, supra. The
Board thus got the location of the delay value wrong. It is never disclosed as
being in the request packet. The Boards primary basis for anticipation is thus
unfounded.

53
The Board also erred regarding when Farmwalds delay value is provided.
Farmwald discloses transmitting delay values to, and storing the values in, the
DRAM before the write request is issued. See pp. 32-33, supra. Claim 1 of the
109 patent reverses the order: The 109 patent requires that the first code the
memory device receives with respect to a transaction specif[y] that a write
operation be initiated in the memory device. A74, 41:65-67; see p. 26, supra.
That code is then followed by other steps, including the claimed signal that
initiates data transfer, later followed by the writing of the data. See pp. 26-28,
supra. The Board never disputed that the 109 patent requires that the steps be
performed in that order. Because Farmwald does not disclose all elements of the
109 patent arranged as in the claimeven if the 109 patent were construed to
encompass the delay value embodimentFarmwald does not anticipate. Connell
v. Sears, Roebuck & Co., 722 F.2d 1542, 1548 (Fed. Cir. 1983).
2. Option (2): Stored in an Access Register or (Sometimes)
Retriev[ed] from the Register
Storing. Alternatively, the Board found that storing the delay value in the
access-register in Farmwald anticipates the providing a signal step in the 109
patent. A14; see also A12, A13. That theory fares no better.
The Board is correct that Farmwald discloses a delay value that is stored
in an access register on the DRAM when the DRAMs access-time registers are
programmed at initialization. Those access-time registers are contain[ed] on

54
the DRAM chip and part of the DRAM itself, JA17603, 6:35-36, :43, as the Board
and Examiner recognized, see A8 (register in the slave DRAM memory device);
JA10992 (the stored value in Farmwald 037 was sent to the memory device).
But the 109 patent claims a method of controlling a memory device,
wherein the command and then the signal are provided to the memory device
by the controller. A74, 41:62, 42:61-62 (emphasis added). Storing a delay value
in an access-time register, which is physically part of the same memory device,
JA17603, 6:35-45, does not constitute providing a signal from one device to a
memory device. Claim 1 does not recite retaining a value within the memory
device, which is what the Boards storing option requires. See Semitool, Inc. v.
Dynamic Micro Sys. Semiconductor Equip. GMBH, 444 F.3d 1337, 1348 (Fed. Cir.
2006) (claim limitation of supplying drying gas to the process chamber not met
where condenser supplying the drying gas was located within the processing
chamber) (emphasis added). As used in the claim (and ordinary usage), to
indicate[s] movement toward . . . a thing that is . . . thought of as being reached.
Websters Third New Intl Dictionary 2401 (2002). The step of providing a signal
to the memory device is not the same thing as having information sitting statically
in the device.
The Boards effort to equate the 109 patents providing a signal to step
with Farmwalds storing a value in the memory devices access-time registers

55
fails for a second reasonsequencing. Farmwalds memory devices store the
delay values in access-time registers on start-up or reset. See p. 32, supra.
Farmwalds storing thus precedes the sending of a write request to the DRAM.
But the 109 patent provides its signal after the write request. See pp. 26-29, 33
supra. That is significant: By controlling timing without pre-stored values, using
a signal sent separate from and subsequent to the command code specifying a
write, the 109 patent provides advantages of flexibility and precision over prior
art. See pp. 35-36, supra.
Finally, it is impossible to equate Farmwalds storage of a delay value in a
register for later use with the 109 patents signal because there is no claimed
storage of a delay value in the 109 patent. The signal the 109 patent recites is
not a value that needs to be stored and then recalled for use with a later-arriving
command. It is a signal whose arrival indicates to begin the transfer specified.
A58, 10:48. And even if the signal were a delay valueand it is notthat
value would be utilized upon receipt and not stored for use with a later-arriving
command. See pp. 29-30, 33-34, supra. Because Farmwald does not disclose a
method in the same form and order as the 109 patent, it cannot anticipate.
Abbott, 544 F.3d at 1345.
Retrieving. Sometimes the Board identified retrieving Farmwalds delay
value from the register as equivalent to the 109 patents signal. [S]killed

56
artisans, the Board stated, would have considered . . . 2) retrieving [the delay
value] as also constituting providing a signal . . . . A14. (Other times, the Board
omits the retrieving option. A13, A17528.) That retrieving option fails for the
same reasons as storage. The access-time register is part of the DRAM. The
Boards retrieval of the value to determine when the memory device should act
thus occurs within the memory device. It cannot satisfy claim 1s limitation that
the signal be provided to the memory device from the controller. A74, 42:61-
62 (emphasis added).
Recognizing that concern, the Board urged that claim 1 does not preclude
providing the signal from one part of the memory device to another part of it.
A15 n.3. But claim 1s limitation of providing a signal to the memory device
precludes precisely that. Sending a signal from one part of a device to another is
providing a signal within a device, not to the device. See p. 54, supra. This
Court has already held that to does not mean within. See Semitool, 444 F.3d at
1348. The 109 patent is clear that the signal to the memory device is a signal
from one device (a controller) to a separate device (the memory device). The
Board gave no reason for or evidence supporting a different understanding.
3. Option (3): Comparing It to a Clock Value
The Boards third theory is that skilled artisans would have considered . . .
3) comparing [Farmwalds delay value] to a clock value . . . as also constituting

57
providing a signal, as recited in claim 1. A14; id. at A13 (delay value consti-
tutes claimed signal when provided for comparison to a clock); see A17528. But
the Board nowhere identified where Farmwald discloses making such a compari-
son. The theory thus fails for want of substantial evidence alone.
The Board, moreover, nowhere explained how comparing a delay value to
a clock constitutes a signal. And the Board in any event described the compar-
ing as occurring within the memory device: [T]he memory device, the Board
stated, compares the delay value number (a signal) to the clock. A17529. The
comparing option thus fails for the same reason as the storing and retrieving
options: Far from disclosing the step of providing a signal to the memory
device, it purports to describe an activity within the memory device.
4. Option (4): Implicitly Used To Generate Another Implicit
Signal
The Boards fourth theory is that Farmwalds delay value constitutes the
109 patents signal when it is implicitly used to generate another implicit sig-
nal after the comparison to signify a match. A12. According to the Board, Farm-
wald discloses that a new signal (a trigger) is created to indicate the delay value
number and external clock match. A17529. But the Board provided no citation
to Farmwald to support that. Given the Boards failure to identify where Farm-
wald actually discloses that new signal (a trigger), it is hard to imagine how it
could be anticipating.

58
The Board may have been assuming that there must be some mechanism in
Farmwald by which the memory device recognizes that the number of clock cycles
represented in the delay value has lapsed following the read/write request, and
whatever that is, it must be the 109 patents signal. But the required teaching of
that signal is absent from Farmwalds four corners. Net MoneyIN, 545 F.3d at
1371. The Board does not explain how such a disclosure could amount to the
elements of claim 1 of the 109 patent arranged or combined in the same way as
recited in the claim. Id.
Nor could it. Any such signal would suffer from the same defect as the
Boards other theories: The signal would be made within a memory device, and
not to the memory device, as claim 1 of the 109 patent requires. A74, 42:61-63
(emphasis added); see p. 54, supra. And that supposed signal would not be
arranged in the same manner as the claim, with the same part to part
relationships. It instead would be part of a complex series of actions involving the
storing of delay values in registers, retrieving them, comparing them, and
generating an implicit signal based on thema very different arrangement than
the controllers provision of a signal to begin sampling, as claimed in the 109
patent.

59
5. Options (1), (2), (3), and/or (4) in Some Combination
Although the Board used the terms and/or to suggest that some possible
combinations of the 4 Farmwald options might anticipate the claims, the Board
never identified which combinations nor cited evidence that Farmwald disclosed
those combinations. But anticipation requires a detail[ed] analysis of the prior
art and a comparison to the patents claims. Finisar, 523 F.3d at 1335. The Board
cannot just list a series of supposed disclosures without identifying where the prior
art reference discloses them and how they were combined in the same arrangement
as the claims at issue.
Even if the Board sought to read Farmwald as providing a delay value
with the write command, which then ping-pongs through the DRAM in various
steps, being stored in and then retrieved from access-time registers, before
being used to generate[ ] another signal for completing the data read or write
operation, see, e.g., A12, such a reading is without basis. That misconceives
Farmwald. For example, if Farmwald transmitted the delay value with the
commandthe moment where the DRAM needs to know the delay periodthere
would be no reason to store multiple delay values in multiple access-time registers
in advance. Farmwald discloses storing and retrieving delay values in registers
precisely because those values are sent to the memory device ahead of the
command for which they eventually will be utilized.

60
By contrast, the 109 patents signal is not stored in advanceor stored
at allbecause it is sent after the write command, when data transfer is to begin.
It is thus distinct fromand represents an advance overFarmwald in part
because it does not require a complex series of steps, such as storing delay
values or other information relating to data transfer timing in access-time
registers, transmitting op codes corresponding to particular registers, and retrieving
and utilizing register-stored values. And it enhances accuracy by reducing the
delay between the transmission of (1) a strobe signal for a transfer operation and
(2) the first packet in the transfer operation. A58, 9:41-46. In a system that
performs billions of functions per second, that fine-tuning can be invaluable. The
Boards effort to equate Farmwald with the 109 patent ignores those critical
differences.
CONCLUSION
The Court should reverse the Boards rejection of the claims of the 109
patent.

September 7, 2012 Respectfully submitted,
Kara F. Stoll
FINNEGAN, HENDERSON, FARABOW,
GARRETT & DUNNER, LLP
901 New York Avenue, N.W.
(202) 408-4000
John M. Whealan
4613 Merivale Road
Chevy Chase, MD 20815
(202) 994-2195

Jeffrey A. Lamken
Counsel of Record
MOLOLAMKEN LLP
The Watergate, Suite 660
600 New Hampshire Avenue, N.W.
(202) 556-2010

Counsel for Appellant Rambus Inc.


ADDENDUM
A1
A2
A3
A4
A5
A6
A7
A8
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A11
A12
A13
A14
A15
A16
A17
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A21
A22
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A24
11111111111111 111111111111111111111111111111111 1111111111111111111111111111
(12) United States Patent
Barth et al.
(54) METHOD OF CONTROLLING A MEMORY
DEVICE HAVING A MEMORY CORE
(75) Inventors: Richard Maurice Barth, Palo Alto, CA
(US); Frederick Abbot Ware, Los
Altos Hills, CA (US); John Bradly
Dillon, Palo Alto, CA (US); Donald
Charles Stark, Woodside, CA (US);
Craig Edward Hampel, San Jose, CA
(US); Matthew Murdy Griffin,
Mountain View, CA (US)
(73) Assignee: Rambus Inc., Los Altos, CA (US)
( *) Notice: Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.C. 154(b) by 285 days.
This patent is subject to a terminal dis-
claimer.
(21) Appl. No.: 10/966,767
(22) Filed: Oct. 15, 2004
( 65) Prior Publication Data
US 2005/0066114 Al Mar. 24, 2005
Related U.S. Application Data
(60) Continuation of application No. 10/094,547, filed on
Mar. 8, 2002, now Pat. No. 6,931,467, which is a
continuation of application No. 09/870,322, filed on
May 29, 2001, now Pat. No. 6,470,405, which is a
May 1, 2000, now Pat. No. 6,591,353, which is a
Jan. 10, 2000, now Pat. No. 6,810,449, which is a
Nov. 26, 1997, now Pat. No. 6,122,688, which is a
division of application No. 08/545,292, filed on Oct.
19, 1995, now Pat. No. 5,748,914.
US0072871 09B2
(10) Patent No.: US 7,287,109 B2
*Oct. 23, 2007 (45) Date of Patent:
(51) Int. CI.
G06F 13100 (2006.01)
(52) U.S. CI ........................................ 710/100; 710/107
(58) Field of Classification Search ................ 710/100,
(56)
710/107
See application file for complete search history.
References Cited
U.S. PATENT DOCUMENTS
4,744,062 A 511988 Nakamura et al.
(Continued)
FOREIGN PATENT DOCUMENTS
EP 0384620 81 311995
EP 0605887 81 912001
JP 61-160129 711986
JP 61-160130 711986
(Continued)
OTHER PUBLICATIONS
English Translation of Notice of the Reason for Refusal, Patent
Application No. JP500879195, Sep. 21, 2004.
Primary Examiner-George C. Neurauter, Jr.
(74) Attorney, Agent, or Firm-Vierra Magen Marcus &
DeNiro LLP
(57) ABSTRACT
Method embodiments including providing control informa-
tion to a memory device is provided. The control informa-
tion includes a first code which specifies that a write
operation be initiated in the memory device. A signal is
provided that indicates when the memory device is to begin
sampling write data that is stored in the memory core during
the write operation. A first bit of the write data is provided
to the memory device during an even phase of a clock signal.
A second bit of the write data is provided to the memory
device during an odd phase of the clock signal.
25 Claims, 21 Drawing Sheets
-
------------
--------
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US 7,287,109 B2
Page 2
U.S. PArENT DOCUMENTS FOREIGN PATENT OOCUMENTS
4,792,926 A
5,319,755 A
5,384,745 A
5,687,183 A
6,470,405 B2
6,931,467 B2
12/1988 Roberts
6/1994 F annwalrl et a!. . . .. . . . . . . 710/104
1/1995 Konishi et al.
11/1997 Chesley
10/2002 Barth et al. ................. 710/100
8/2005 Barth et al .................. 710/100
JP 61-245255
JP 62-135949
JP 01-163849
JP 6-103153
* cited by examiner
10/1986
6/1987
6/1989
4/1994
A32
U.S. Patent Oct. 23, 2007 Sheet 1 of 21 US 7,287,109 B2
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Oct. 23, 2007 Sheet 2 of 21 US 7,287,109 B2
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U.S. Patent Oct. 23,2007 Sheet 15 of 21
Figure 14
PRIOR ART
US 7,287,109 B2
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A48
U.S. Patent Oct. 23,2007 Sheet 17 of 21 US 7,287,109 B2
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A49
U.S. Patent
REQUEST
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US 7,287,109 B2
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A53
US 7,287,109 B2
1
METHOD OF CONTROLLING A MEMORY
DEVICE HAVING A MEMORY CORE
This application is a continuation of U.S. patent applica-
tion Ser. No. 10/094,547 filed on Mar. 8, 2002 now U.S. Pat. 5
No. 6,931,467; which is a continuation of U.S. patent
application Ser. No. 09/870,322 filed on May 29, 2001 (now
U.S. Pat. No. 6,470,405); which is a continuation of U.S.
patent application Ser. No. 09/561,868 filed on May I, 2000
(now U.S. Pat. No. 6,591,353); which is a continuation of 10
U.S. patent application Ser. No. 09/480,767 filed on Jan. I 0,
2000 now U.S. Pat. No. 6,810,449; which is a continuation
of U.S. patent application Ser. No. 08/979,402 filed on Nov.
26, 1997 (now U.S. Pat. No. 6,122,688); which is a divi-
sional ofU.S. patent application Ser. No. 08/545,292 filed on 15
Oct. 19, 1995 (now U.S. Pat. No. 5,748,914).
FIELD OF THE INVENTION
2
RData (a,!) is then transmitted by the DRAM and received
by the processor. This step can be repeated "n" times in the
currently loaded row before a new row is sensed and loaded.
Before a new row is sensed, the old row must be restored
back to the memory array.
Various attempts have been made to improve the perfor-
mance of conventional DRAMs. Such attempts have
resulted in DRAM architectures that deviate in varying
degrees from conventional DRAM architectures. Various
alternative DRAM architectures are described in detail in
NEW DRAM TECHNOLOGIES, by Steven A. Przybylskti,
published by MicroDesign Resources, Sebastopol, Calif.
(1994). Some of those architectures are generally described
below.
Extended Data-Out DRA.MS
The prior art includes Extended Data-Out (EDO) memory
systems. In EDO DRAMs, the output buffer is controlled by
The present invention relates to dynamic random access
memory (DRAM), and more specifically, to a method and
apparatus for controlling data transfers to and from a
dynamic random access memory.
BACKGROUND OF THE INVENTION
20 signals applied to output enable (OE) and column address
stobe (CAS) control lines. In general, data remains valid at
the output of an EDO DRA.M longer than it does for
conventional DRAMs. Because the data remains valid
longer, the transfer of the data to the latch in the memory
25 controller can be overlapped with the next column pre-
charge. As a result, burst transfers can be performed in fewer
clock cycles.
Dynamic random access memory (DRAM) components,
such as those illustrated in FIG. lA, provide an inexpensive
solid-state storage technology fortoday's computer systems.
Digital information is maintained in the form of a charge 30
stored on a two-dimensional array of capacitors. One such
capacitor is illustrated in FIG. lB.
FIG. 2 illustrates a prior art memory system including
DRAM with the corresponding control, address and data
wires which connect the DRAM to the processor or memory 35
controller component. In synchronous DRAMs, a write
access is initiated by transmitting a row address on the
address wires and by transmitting row address strobe (RAS)
signal. This causes the desired row to be sensed and loaded
by the column amplifiers. The column address is transmitted 40
on the address wires and the column address strobe (CAS)
signal is transmitted along with the first word of the write
data WData(a,l). The data word is then received by the
DRAM and written into the column amplifiers at the speci-
fied column address. This step can be repeated "n" times in 45
the currently loaded row before a new row is sensed and
loaded. Before a new row is sensed, the old row must be
restored back to the memory core and the bit lines of the
DRAM precharged.
FIG. 3A illustrates synchronous write timing. In the 50
figure, a, b ... represent a row address; 1, 2 ... n represent
a column address, WData [row, col] represents the DRAM
address of data words, the row address strobe (RAS) is a
control signal for initiating a sense operation, and WRITE
(CAS) initiates the write operation on the column amplifiers. ?5
In the present example, the row column address delay timing
parameter is equal to two clock cycles. After the row address
Synchronous DRAMS
The prior art also includes Synchronous DRAM
(SDRAM) memory systems. The interface of an SDRAM
includes a multiplexed address bus and a high-speed clock.
The high speed clock is used to synchronize the flow of
addresses, data, and control on and off the DRAM, and to
facilitate pipelining of operations. AU address, data and
control inputs are latched on the rising edge of the clock.
Outputs change after the rising edge of the clock. SDRAMs
typically contain a mode register. The mode register may be
loaded with values which control certain operational param-
eters. For example, the mode register may contain a burst
length value, a burst type value, and a latency mode value.
The burst length value determines the length of the data
bursts that the DRAM will perform The burst type value
determines the ordering of the data sent in the bursts. Typical
burst orders include sequential and sub-block ordered. The
latency mode value determines the number of clock cycles
between a column address and the data appearing on the data
bus. The appropriate value for this time interval depends
largely on the operating frequency of the SDRAM. Since the
SDRAM cannot detect the operating frequency, the latency
mode value is programmable by a user.
Request Oriented DRAM Systems
The prior art also includes memory systems in which data
transfer operations are performed by DRAMs in response to
transfer requests issued to the DRAMs by a controller.
Referring to FIG. 4, it illustrates a memory system in which
is asserted at the first clock cycle, column addresses and
write data are asserted after the delay to write the data into
the DRAM array. 60 data transfers are made in response to transfer requests. The
request packet format is designed for use on a high speed
multiplexed bus for communicating between master devices,
such as processors, and slave devices, such as memories.
FIG. 3B illustrates synchronous read timing. A processor
initiates a read access by transmitting a row address on the
address wires and by transmitting the row address strobe
(RAS) signal. This causes the desired row to be sensed by
the column amplifiers. The column address is then trans- 65
mitted on the address wire and the column address strobe
(CAS) signal is transmitted. The first word of the read data
The bus carries substantially all address, data, and control
information needed by the master devices for communica-
tion with the slave devices coupled to the bus. The bus
architecture includes the following signal transmission lines:
A54
US 7,287,109 B2
3
BusCtl, BusData [8:0], BusEnable, as well as clock signal
lines and power and ground lines. These lines are connected
in parallel to each device.
The processors communicate with the DRAMs to read
and write data to the memory. The processors form request
packets which are communicated to the DRAMs by trans-
mitting the bits on predetermined transmission lines at a
predetermined time sequence (i.e. at predetermined clock
cycles). The bus interface of the DRAM receiver processes
the information received to determine the type of memory 10
request and the number of bytes of the operation. The
DRAMs then perform the memory operation indicated by
the request packet.
FIG. 5 illustrates command control information 500 that
is sent in a data transfer request according to a prior art 1
5
protocol. In the illustrated example, the command control
information 500 is sent over a BusCtlline and a nine-bit data
bus (BusData[8:0]) in six clock cycles. The command con-
trol information 500 includes groups of bits 501, 502, 504,
506 and 508 that constitute an address, an operation code
20
consisting of six bits 510, 512, 514, 516, 518 and 520, and
groups of bits 522, 524 and 528 that specify a count. The
address identified in the command control information 500
specifies the target DRAM and the beginning location within
the DRAM of the data on which the operation is to be 25
performed. The count identified in the command control
information 500 specifies the amount of information on
which the operation is to be performed.
SUMMARY AND OBJECTS OF THE
INVENTION
30
4
Another object of the present invention is to provide a
DRAM core which allows a single high current RAS opera-
tion at any one time in order to minimize the cost and
complexity of the DRAM.
Another object of the present invention is to provide an
encoding of the command such that decoding space and time
is minimized and functionality is maximized.
The present invention provides a method and apparatus
for performing data transfers within a computer system The
method includes causing a controller to transmit control
information on a bus. The control information specifies a
data transfer operation and a beginning location of data to be
transferred. The controller determines, after transmitting the
control information on the bus, a desired amount of data to
be transferred in the data transfer operation. The controller
transmits over the bus a terminate indication at a time that
is based on the desired amount of data and a beginning time
of the data transfer operation. A memory device reads the
control information on the bus. The memory device per-
forms the specified data transfer operation on data stored at
the beginning location. The memory device continues to
perform the specified data transfer operation until detecting
the terminate indication on the bus. The memory device
ceases to perform the data transfer operation at a time that
is based on the time at which the terminate indication is
detected.
Other objects, features, and advantages of the present
invention will be apparent from the accompanying drawings
and from the detailed description that follows below.
BRIEF DESCRIPTION OF THE DRAWINGS
One object of the present invention is to provide a
mechanism to decouple control timing from data timing.
Another object of the present invention is to provide
mechanisms that use minimal bandwidth to determine data
timing while minimizing the latency from signaling that the
data transfer should terminate to the transmission of the final
data packet.
The present invention is illustrated by way of example,
and not by way of limitation, in the figures of the accom-
35 panying drawings and in which like reference numerals refer
to similar elements and in which:
FIG. 1A is a block diagram of prior art dynamic random
access memory (DRAM) component;
FIG. 18 illustrates a storage cell of the DRAM shown in
40 FIG. 1A;
mechanisms for arbitrarily long data transfers following a
command. This may include simultaneous provision of a
new column address for each data packet transferred.
Another object of the present invention is to provide a 45
means to signal simultaneously with termination of the data
transfer that a precharge operation should be performed.
mechanisms and methods for interleaving control and data
information in such a fashion that pin utilization is maxi-
50
mized without placing latency requirements upon the
DRAM core that are difficult or expensive to satisfy.
FIG. 2 is a block diagram illustrating a DRAM system and
input/output pins and signal lines for accessing the DRAM;
FIG. 3A is a timing diagram illustrating synchronous
write timing;
FIG. 3B is a prior art timing diagram illustrating synchro-
nous read timing;
FIG. 4 is a prior art memory system in which a memory
controller issues request packets to DRAM over a channel;
FIG. 5 illustrates command control information that is
sent from a controller to a DRAM according to a prior art
protocol;
FIG. 6 is a block diagram of a computing system that
includes the present invention;
mechanism for interleaving control and data information
that minimizes bandwidth consumed for signaling the begin-
ning and ending of data transfers.
FIG. 7 is a block diagram the illustrates the control and
55 decode circuitry of a DRAM according to one embodiment
of the invention;
Another object of the present invention is to provide for
devices that do not always interpret the information pre-
sented at their pins. Each command provides sufficient
60
information that all further control information related to the
command can be easily determined even in the presence of
control information related to previous command transfers.
mechanism for optionally sequencing a series of core opera- 65
tions prior to data transmission and, optionally, a final core
operation after data transmission is terminated.
FIG. 8 is a flow chart illustrating the protocol employed
by a controller to initiate data transfers according to an
embodiment of the present invention;
FIG. 9 illustrates a request packet according to one
embodiment of the present invention;
FIG. 10 is a timing diagram illustrating interleaved read/
write transaction timing when the read latency equals the
write latency according to a prior art protocol;
FIG. 11 is a timing diagram which illustrates synchronous
interleaved read timing with multiplexed data/row/control
information according to an alternative prior art protocol;
A55
US 7,287,109 B2
5
FIG. 12 illustrates the timing of five transactions per-
formed in a non-interleaved embodiment of the present
invention;
6
data packets transmitted by DRAM 603. The inforn1ation
communicated over lines 626 includes request packets, data
transfer control signals, and data packets.
FIG. 13 illustrates the timing of five transactions per-
formed in an interleaved embodiment of the present inven- 5
DRAM 603 is divided into three sections: an storage
section 632, a control section 634, and a I/0 section 636. The
storage section 632 includes a DRAM core consisting of two
independent memory banks 602 and 606. It should be noted
that a two-bank DRAM shall be described simply for the
purposes of explanation. The present invention is not limited
lion;
FIG. 14 illustrates circuitry for decoding operation codes
according to the prior art;
FIG. 15 illustrates circuitry for decoding operation codes
acconling to one embodiment of the present invention;
FIG. 16A illustrates an operation code encoding scheme
according to an embodiment of the invention;
FIG. 168 is a continuation of the table illustrated in FIG.
16A;
FIG. 17 illustrates a prior art circuit fur determining
whether a particular DRAM should respond to an operation
request; and
FIG. 18 illustrates a circuit for determining whether a
particular DRAM should respond to an operation request
according to an embodiment of the present invention;
FIG. 19 illustrates a mapping between Open and Close
bits and the operations that are performed by a DRAM in
response to the bits according to an embodiment of the
invention;
FIG. 20A is a block diagram illustrating a DRAM con-
figured to allow no more than one high current operation to
be performed over each internal power supply line according
to an embodiment of the invention; and
FIG. 208 is a block diagram illustrating a DRAM con-
figured to allow no more than one high current operation to
be performed within the DRAM at any given time according
to an embodiment of the invention.
DETAILED DESCRIPTION
10 to DRAMs with any particular number of memory banks.
Each of the memory banks 602 and 606 has a latching
sense amplifier cache 604 and 608. The caches 604 and 608
hold the currently sensed row of their respective memory
banks. The control section 634 includes control logic 610
15 and control registers 614. Control logic 610 performs ini-
tialization operations in response to control signals on line
624. Control registers 614 are read and written to using
special register space commands. The contents of the control
registers 614 determine how DRAM 603 operates. For
20 example, the control registers 614 may store values that
determine the output drive current used by DRAM 603, the
base address of DRAM 603 and the configuration and size
of DRAM 603.
The 110 section 636 includes a clock generator 618, a
25 receiver 620, and a transmitter 616. The clock generator 618
uses the external clock signals to create clock signals used
internally by DRAM 603. The receiver 620 and transmitter
616 contain multiplexing and storage hardware to permit
internal data paths to operate at a slower clock rate, but
30 equivalent bandwidth, to lines 626.
FIG. 7 is a biockdiagramofaDRAM in which the present
invention may be implemented according to one embodi-
ment of the invention. Referring to FIG. 7, a DRAM 700
generally includes 110 and control circuitry 722, four banks
35 of memory, a plurality of column decoders 718 and 720, and
FIG. 6 is a block diagram of a computing system that a plurality of row decoders 704, 706, 712 and 714. Each of
includes the present invention. The data transport system the four banks are split into two memory blocks. Specifi-
includes a central processing unit 600, a memory controller cally, BANKO is distributed over blocks 702A and 7028,
601 and a DRAM 603. The memory controller 601 connects BANK1 is distributed over blocks 708A and 7088, 8ANK2
the CPU 600 to a channel 622 to which DRAM 603 is 40 is distributed over blocks 710A and 7108 and 8ANK3 is
connected. For the purposes of explanation, a single DRAM distributed over blocks 716A and 7168.
is shown on channel 622. However, the present invention is 1/0 and control circuitry 722 receives request packets
not limited to any particular number of DRAMs on the from a controller over a channel 724. The request packets
channel 622. include an address that corresponds to a storage location and
The CPU 600 may be, for example, a microprocessor. 45 an operation code that specifies the operation to be per-
When the CPU 600 executes instructions that require a data formed on the data stored in the specified storage location.
transfer operation, the CPU 600 transmits control signals To perform a read operation, 110 and control circuitry 722
specifYing the desired transfer operations to memory con- transmits control signals to the row decoders 704, 706, 712
troller 601. Memory controller 601 may be, for example, an and 714 to cause the row that contains the specified data to
application specific integrated circuit (ASIC) memory con- 50 be moved into a cache. Then the 110 and control circuitry
troller configured to transmit request packets to DRAM 603 722 transmits control signals to the column decoders 718
over channel 622 to specifY the desired transfer operation. and 720 to cause the data from a column of the row in the
According to one embodiment, channel 622 includes a row cache to be transmitted out onto the channel 724. The
line 624 for initializing daisy chain input, a "clock to end" column that is transmitted is the column that corresponds to
line 650, a "clock from master'' line 628, a "clock to master" 55 the address contained in the request packet.
line 630, and a plurality of lines 626 that includes a
8usEnable line, a BusCtl line and a nine-bit data bus
(8usData[8:0]). The "clock to end" line 650 carries a clock
signal from memory controller 601 to the end of line 630.
The "clock to master" line 630 routes the clock signal to the 60
various devices on channel 622 and back to memory con-
troller 601. The "clock from master" line 628 routes the
clock signal from the "clock to master" line 630 back to the
various devices on channel 622. The clock signal on the
"clock from master" line 628 is aligned with request and 65
write data packets transmitted by controller 601. The clock
signal on the "clock to master" line 630 is aligned with read
Controller Operation
Referring to FIG. 8, it is a flow chart that illustrates the
protocol employed by a controller to initiate data transfers
according to one embodiment of the invention. At step 802,
the controller transmits a wakeup signal to the DRAM that
will be involved in the data transfer operation (the "target
DRAM''). At step 804, the controller transmits command
control information to the target DRAM. The contents of the
command control information according to one embodiment
of the invention are illustrated in FIG. 9.
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US 7,287,109 B2
7
Referring to FIG. 9, the command control information is
transmitted over the BusCtlline and BusData[8:0]lines over
three clock cycles, where each clock cycle has even and odd
phases. A start bit 902 is sent over the BusCtl line on the
even phase of the first clock cycle. As shall be described in
greater detail below, the start bit serves as a flag which
allows the DRAM to identify the signals as command
control information.
The command control information includes an address
904 that identifies the beginning memory location in the 10
target DRAM that will be involved in the specified data
transfer operation. The command control information fur-
ther includes an operation code, open and close bits, and a
Pend value.
8
conunand control information for other transactions
between execution of steps 804 and 806).
In one embodiment, the controller is configured to limit
the number of requests that are targeted to any given DRAM.
For example, if two data transfer operations have been
requested for a given DRAM, the controller will refrain from
issuing a third request until one of the outstanding requests
has been serviced. By limiting the number of requests any
DRAM must handle at any given time, the size of the
command queue within the DRAM may be reduced,
decreasing the complexity of the DRAM.
In one embodiment, the number of outstanding requests
on the channel may be larger than the number of requests
being processed by any single DRAM. Preferably, the
As shall be explained below, certain bits in the operation
code directly correspond to control lines within the target
DRAM. Specifically, the operation code includes a Write bit
906, a Reg bit 908 and a NoByteM bit 910 that correspond
15 number of outstanding requests is limited only by the size of
the field which indicates the number of outstanding requests,
and the aggregate number of requests which can be handled
by all of the DRAMs on the channel.
to control lines in the target DR.t\M. Upon receipt of the
command control information, the DRAM simply places the 20
value stored in these bits on the respective control line. The
operation code also contains a broadcast bit 912 to indicate
whether the specified operation is a broadcast operation.
The Open, Close and Pend values serve functions
described in greater detail below. In general, the Open and 25
Close bits specify whether precharge and/or sense opera-
tions are to be performed before and/or after the operation
specified in the operation code. The Pend value indicates
how many odd phase bits will appear on the BusCtlline after
the command control information and before the strobe 30
signal that corresponds to the operation specified in the
command control information (other than any odd phase bits
in request packets for other transactions). The command
control information also contains other values "EvalCC" and
"Mask" that do not relate to the present invention. 35
Referring again to FIG. 8, control passes from step 804 to
step 806. During step 806, the controller transmits the strobe
signal over the BusCtl line (step 810). If the transaction
involves more than one data packet, then the column address
for data packets that are to be sent subsequent to the first data 40
packet are transmitted serially over the BusEnable line (step
808). Steps 808 and 810 are combined in step 806 to indicate
that step 810 is performed concurrently with step 808. In one
embodiment, the transmission of the address for subsequent
data packets begins at a sufficient interval prior to the time 45
at which those data packets are to be sent to allow the second
and subsequent data packets to be sent after the first data
packet without interruption.
At step 814, the data is transmitted over the data bus
(BusData[8:0]). During this step, the data may be transmit- 50
ted to or from the target DRAM, depending on whether the
data transfer operation is write or read operation. At some
fixed period of time prior to the transmission of the last the
last data packet, the controller transmits the terminate signal
on the BusCtlline (step 816). Steps 816 and 814 are shown 55
as a single step 812 to indicate that step 816 is performed
during the performance of step 814.
As shall be explained below, one embodiment of the
memory controller dynamically adjusts the interleave of data
and control information to more fully utilize the channel. 60
Interleave refers to the relative ordering of data, requests and
control signals that are associated to multiple transactions.
To allow dynamic interleave adjustment, there is no fixed
time period between the execution of steps 804 and 806.
Rather, the controller is free to adjust the tiring of step 806 65
relative to the timing of step 804 as needed to provide the
desired interleave (e.g., to provide time to transmit the
Deferred Transfer Size Determination
In typical EOO and SDRAM components, only a finite
number of data transfer sizes are supported. For each data
transfer size, there is a fixed ratio between the amount of
control information that must be sent to a DRAM and the
amount of data to be transferred in the operation. Thus, the
larger the amount of data to be transferred, the larger the
amount of control information that must be sent to the
DRAM. For example, with an SDRAM that only supports
transfers of one or four data words, two four-word transfers
must be performed to transfer eight data words. Thus, all of
the control information that a controller must send to the
DRAM for a four data word transfer, including an operation
code and an address, must be sent twice.
In prior art request-oriented systems, a data transfer count
is part of the command control information that a controller
sends to a DRAM to initiate a data transfer operation. The
amount of bits allocated in the control information for
sending the data transfer count is fixed. Consequently, the
size of data transfers that a system may perform in response
to a single transfer request is limited to the number of data
packets that can be specified in the available number ofbits.
The size limit thus placed on data transfers makes it neces-
sary for transfers of large amounts of data to be performed
using numerous requests for smaller data transfer opera-
tions. For example, if the data transfer count is only five bits
long and data packets are eight bytes, then the maximum
size of a data transfer is 256 bytes (32 data packets). For
transfers larger than 256 bytes, more than one request packet
must be used.
In one prior art request-oriented system, the controller is
allowed to prematurely terminate a data transfer operation
by transmitting a terminate control signal to the DRt\M.
Upon receipt of the terminate control signal during a par-
ticular data transfer operation, the DRAM ceases to process
data for the operation, even if the amount of data that has
been transferred is less than the amount of data that was
specified in the data transfer count of the operation. This
technique allows the controller to shorten data transfers after
a particular transfer size has been specified, but does not
overcome the limitations associated with having a maximum
size limit per requested transaction.
According to one aspect of the present invention, the
command control information within a request packet no
longer contains size information. Rather, the DRAM is
configured to start and end the transmission of data based on
data transfer control information sent by the controller to the
A57
US 7,287,109 B2
9
DRAM separate from and subsequent to the transmission of
the command control infonnation. According to one
embodiment, the data transfer control information includes
data transfer start infonnation (a "strobe signal") sent from
the controller to indicate when the DRAM is to begin
sending data, and data transfer end information (a "tenninate
signal") to indicate when the DRAM is to stop sending data.
The nwnber of clock cycles that elapse between the trans-
mission of the strobe signal and the tenninate signal indi-
cates the size of the data transfer. 10
If a data transfer operation involves more than one data
packet, then the controller serially transmits column address
information on the BusEnable line to specifY the columns
that contain the data to be sent in the second and subsequent
data packets. Preferably, the controller begins to transmit the 15
column address infonnation at a time that allows the DRAM
10
between the transmission of the tenninate signal for the
transaction and the transmission of the last data packet of the
transaction. By reducing the latency between the terminate
signal for a transaction and the time at which the channel
ceases to be used to send data for the transaction, the amount
of time required for the controller to use the channel for
another transaction is reduced. This is particularly important
when there are multiple requesters that are contending for
use of the same channel.
According to one embodiment, the terminate signal may
be used to either end a transaction or suspend a transaction.
The exact timing of the tenninate signal may be used to
indicate whether a transfer operation should be terminated or
merely suspended. For example, if the tenninate signal is
sent at one modulus relative to the strobe signal, the DRAM
is configured to terminate the data transfer operation. A
modulus is the remainder obtained after dividing one integer
by another integer. If the tenninate signal is sent at a
to have sufficient time to reconstruct the column addresses
and prefetch the data from the specified colwnns in the
DR.A.M core before the data packets that correspond to the
column addresses are to be transmitted over the channel.
Because the DRAM continuously receives column
addresses over the BusEnable line during multi-packet trans-
fers, the DRA.M itself does not have to maintain a counter
20 different modulus relative to the strobe signal, the DRAM is
configured to suspend the transfer operation. The DRAM
may be configured to continue transfer operations that have
been suspended upon receipt of a continue control signal.
to detennine from where to retrieve data for the next data
packet. 25
By transmitting data transfer control information separate
from the command control infonnation, it is possible to
specifY a transfer operation for any amount of data. Thus,
large transfers do not have to be broken up into multiple
requests for smaller amounts of data In one embodiment, the 30
control circuitry within the DRAM is configured to begin
retrieving requested data from the DRAM core as soon as
possible after receipt of a request packet The DRAM does
not wait for the strobe signal to begin retrieving the data
from the DRAM core. However, the DRAM does not 35
transmit any data on the channel until the strobe signal is
received. Because the initial data packet to be transmitted by
the DRAM has been prefetched from the core, the data
packet can be transmitted over the channel with minimal
delay from when the strobe signal ultimately arrives. 40
There are numerous benefits to reducing the delay
between the transmission of (1) a strobe signal for a transfer
operation and (2) the first packet in the transfer operation.
For example, the minimum latency between a transfer
request and the beginning of the transfer can never be less 45
than the strobe-to-data delay. Therefore, the strobe-to-data
delay may determine the critical path for DRAMs that
support fast core operations. In addition, the longer the
strobe-to-data delay, the more complex the controller must
be to accurately and efficiently pipeline the command con- 50
trol infonnation and strobe signals.
The bandwidth required to indicate the start and end of a
data transfer operation with single bit strobe and tenninate
signals is minimal. In one embodiment, a single line (the
BusCtl line) is used to carry a variety of control signals, 55
including the strobe and tenninate signals. Further, the
channel utilization employed to start and tenninate a transfer
operation docs not vary with the size of the data to be
transferred.
Decoupled Data Transfer Control lnfonnation
In prior art systems, the timing of a data transfer is
dictated by the timing of the request for the data transfer.
Thus, given that a transfer request arrived on a particular
clock cycle, it was known that the data specified in the
request would begin to appear on BusData[8:0] a predeter-
mined number of clock cycles from the particular clock
cycle. For example, the number of clock cycles that elapse
between a request packet and the transfer of data specified
in the request packet may be detennined by a value stored
in a register within the DRAM. This fact renders prior art
systems inflexible with respect to how control and data
signals may be interleaved to maximize the use of the
channel.
As mentioned above, the data transfer control infonnation
which controls the timing of the data transfer associated with
a request packet is sent separately from the command
control information to which it corresponds. According to
another aspect of the invention, the timing of the data
transfer control infonnation is variable relative to the timing
of the corresponding request packet. That is, the number of
clock cycles between the transmission of a request packet
and the transmission of the strobe signal to begin the transfer
specified in the request packet may vary from transaction to
transaction.
According to an alternate embodiment of the invention,
the amount oftime that elapses between the transmission of
a request packet and the transmission of the data specified in
a request packet is varied without the use of strobe and
tenninate signals.
In this embodiment, the reset packet contains a delay
value that indicates to the DRAM when the data specified in
the request packet will begin to be sent relative to the time
Due to intrinsic circuit delays, the DR.t\M does not
instantly terminate data transmission upon the receipt of the
terminate signal. Rather, the terminate signal causes the
DR.t\M to initiate tennination of the data transfer. Trans-
mission of the last data packet in a transfer actually occurs
on some clock cycle after the receipt of the terminate signal.
When a tenninate signal is used to specifY the end of a
transfer operation, it is important to minimize the latency
60 at which the request packet is sent. The DRAM would
include a counter to count the clock cycles that elapse from
the arrival of the request packet in order to send or receive
the data specified in the request on the appropriate clock
cycle. Because the controller may vary the latency between
65 request packet and data transmission, the controller is able
to dynamically adjust the operative interleave on the chan-
nel, as shall be described in greater detail below.
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US 7,287,109 B2
11
Dynamic Interleave Adjustment
As mentioned above, the fixed timing between requests
and data transmissions renders prior art systems inflexible
with respect to how control and data signals may be inter-
leaved. For example, FIGS. 10 and 11 illustrate the timing
of transactions for particular prior art protocol systems.
12
information was otherwise unused. Significantly, five trans-
actions are completed by clock cycle 131 using the inter
leaved example shown in Appendix B, while completion of
five transactions requires 172 clock cycles in the non
interleaved system shown in Appendix A.
The ability to dynamically adjust the interleave of control
and data information allows controllers to increase the
utilization of the channel. In addition, the controller can
adapt the interleave to the changing demands being placed
Referring to FIG. 10, it illustrates interleaved timing of
read and write accesses. The interleave structure permits
read accesses to a DRAM to be interleaved with write
accesses to another DRAM. FIG. 11 illustrates synchronous
interleaved read timing with multiplexed data/row/control
information according to an alternative prior art protocol.
Both of these prior art interleave patterns increase utilization
of the channel and the internal resources of the DRAM
relative to non-interleaved protocols. However, the timing
between requests and data transfers is fixed, so the interleave
patterns are fixed. Consequently, controllers cannot make
interleave adjustments to maximize usage of the channel and
DRAM resources in response to changing conditions in the
system.
10 on the bus to minimize latency. Fur example, the controller
can transition from a cold start, where the bus is idle, to an
active state by issuing a series of requests back-to-hack and
then waiting for the data that will be sent in response to the
requests. After start, the controller adjusts the interleave to
15 shift from minimizing latency to maximizing utilization of
the channel and internal resources of the DRAM. Therefore,
after a steady state has been achieved, the controller avoids
having too many back-to-hack requests. Rather, the control-
ler switches to a smoother interleave pattern, such as the
The ability to vary the timing between the transmission of
20 pattern illustrated in Appendix B. An exemplary series of
transactions that illustrate how a controller that employs the
protocol of the present invention is able to dynamically
change the interleave of transactions shall be discussed in
greater detail below with reference to Appendix C.
a request packet and the transmission of the data specified in
the command control information makes it possible to
interleave the information on BusData[8:0] in variations that 25
were not previously possible. According, to one embodiment Signal Overload
To help maximize utilization of the channel, the same
control line may be used to carry numerous control signals.
of the invention, controllers dynamically adjust the inter-
leave to maximize the use of the channel in the face of
internal DRAM latencies that are long with respect to the
transmission of control information or data.
Referring to Appendix A and FIG. 12, they illustrate the
timing of five non-interleaved data transfer operations. At
clock cycle 0, a wakeup signal associated with transaction 0
30 For example, in the protocol illustrated in Appendixes A and
B, the BusCtlline is used to carry wakeup signals, strobe
signals, portions of the co=and control information, and
terminate signals. According to one embodiment of the
is transmitted from the controller to the DRAM on the
BusCtlline "BC". At clock cycles 4 through 6 the co=and 35
control information for transaction 0 is sent from the con-
troller to the DRAM over the BusCtlline and nine bus data
lines "BD[8:0]". At clock cycle 10 the DRAM begins
sensing the row specified in the co=and control informa-
tion of the bank specified in the co=and control informa- 40
tion. At clock cycle 17 the controller sends the strobe signal
associated with transaction 0 to the DRAM. At clock cycle
23 the DRAM begins transferring data beginning at the
address specified in the command control information. At
clock cycle 30 the controller sends a terminate signal 45
associated with transaction 0 to the DRAM. At clock cycle
38, the DRAM sends the last data associated with transac-
tion 0.
The wakeup signal for transaction 1 is transmitted at clock
cycle 35. At clock cycles 39 through 41 the co=and 50
control information for transaction 1 is transmitted. The
timing for transactions 1 through 4 proceeds as illustrated.
This example clearly illustrates that there is minimal timing
overlap between transactions when signals for different
transactions are not interleaved. Consequently, bandwidth 55
that may be used to begin subsequent transactions goes
unused.
Referring to Appendix B and FIG. 13, they illustrate the
timing of interleaved data-transfer operations. In the illus-
trated example, the wakeup signal for transaction 1 is 60
transmitted at clock cycle 20, even before data has started to
be sent for transaction 0. By the time the terminate signal has
been sent for transaction 0, the wakeup signal and co=and
control information have been sent to the DRAM for trans-
action 1. The transmission of this information during the 65
execution of transaction 0 does not result in any perfor-
mance penalty because the bandwidth used to transfer the
invention, clock cycles are divided into even and odd
phases.
The co=and control information is preceded by a non-
zero value "start bit" on the BusCtl line at an even phase of
the clock cycle. Upon detection of a start bit, a DRAM
knows that any signals on the BusCtlline during the three
subsequent odd phases of the clock cycle are part of the
co=and control information, and not strobe, wakeup or
terminate signals. The strobe signals, wakeup signals and
terminate signals are all indicated by non-zero values on the
BusCtl line at an odd phase of the clock cycle. Consequently,
the DRAM must have some mechanism for distinguishing
between the signals.
In an embodiment of the invention that uses fixed inter
leaves, an operation begins at a fixed interval relative to the
co=and control information that specifies the operation.
Therefore, DRAMs simply use the arrival time of the
co=and control information and the known interval to
determine when to perform the operation. The terminate
signal associated with a transaction is always the next
odd-phased signal on the BusCtlline after its corresponding
co=and control information. Therefore, if the co=and
control information can be identified, the terminate signal
can also be identified. Any signal on the BusCtlline during
an odd phase of a clock cycle is a wakeup signal.
The method described above for distinguishing between
identical control signals (i.e. control signals that use the
same line and have the same characteristics) works well in
an embodiment that employs fixed interleaves. However,
where the timing interval between a request packet and its
corresponding strobe signal is variable, a mechanism must
he provided to indicate to the DRAMs when to look for the
strobe signal that corresponds to a request packet that has
been received.
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US 7,287,109 B2
13
In the example illustrated in Appendix B, the period
between the transmission of the command control informa-
tion for a transaction and the strobe signal for the transaction
is not fixed. Consequently, the DRAM must have some other
mechanism for determining that, of all the signals that arrive
on the BusCtlline, the signal at clock cycle 47 is the strobe
signal associated with the command control information for
transaction 1.
According to one embodiment of the present invention,
the DRAM is able to distinguish between identical signals 10
on the BusCtlline based on knowledge of what information
has previously appeared on the channel. To obtain informa-
tion about data on the channel, the DRAM constantly
monitors the channel. Because the DRAM constantly moni-
tors the channel, the controller does not have to transmit 15
wakeup signals to the DRAM. Therefore, the only identical
signals on the BusCtl line are the strobe signal and the
terminate signal.
According to this embodiment, the order in which the
controller sends strobe and terminate signals must match the
20
order in which the controller sends request packets. For
example, if the controller transmits request packets for
transactions 0, 1, and 2, in that order, then the controller
must send strobe and terminate signals for transactions 0, 1,
and 2, in that order. 25
Under the constraints described above, the DRAM has the
information it requires to correctly identifY the strobe and
terminate signals on the channel. Specifically, the first
control signal on the BusCtl line will always be a strobe
30
signal associated with the first transaction. The control
signal that follows any strobe signal is always the terminate
signal for the transaction that corresponds to the preceding
strobe signal. The control signal that follows any terminate
signal will always be a strobe signal for the transaction that
immediately follows the transaction associated with the
35
previous strobe signal.
While the approach described above allows a DRAM to
accurately identifY strobe and terminate signals, it has two
obvious disadvantages. First, it requires that all DRAMs
40
monitor the channel at all times. If any DRAM fails to
monitor the line for any period, the DRAM will not be able
to accurately identify the identical control signals. Because
the DRAM has to constantly monitor the channel, the
DRAM will not be able to conserve energy by entering a
45
power-down mode. The expense associated with keeping all
DRAMs powered up at all times is significant.
The second disadvantage is that the controller must send
the control signals in exactly the same order as the command
control information. As a result, the controller is limited with 50
respect to the type of interleave patterns it may select.
Specifically, the controller may not select any interleave
patterns that retire a transaction out of order.
According to an alternate embodiment of the present
invention, the controller is configured to transmit, as part of 55
the command control information in a request packet, data
which allows the DRA.M to identifY the strobe signal that
corresponds to the command control information. For
example, in one embodiment, the controller includes a
"Pend" value in the command control information. The Pend 60
value in a request packet indicates how many control signals
that arc identical to the strobe signal will occur between the
end of the command control information for a transaction
and the actual strobe signal for the transaction. Based on the
Pend value, a DRAM is able to identify control signals 65
without having to know what has transpired on the channel
prior to the arrival of the command control information.
14
In the example illustration Appendix B, the command
control information for transaction 1 is sent at clock cycle
24, and the strobe signal for transaction 1 is sent at clock
cycle 47. Between the transmission of the command control
information for transaction 1 and the transmission of the
strobe signal for transaction 1, a terminate signal for trans-
action 0, a wakeup signal for transaction 2 and a request
packet for transaction 2 are sent. (The DRAM knows to
ignore the command control information for transaction 1 by
detecting its start bit on an even phase of the clock cycle.).
The terminate signal for transaction 0 and the wakeup
signal for transaction 2 both have identical characteristics to
strobe signals. Therefore, the Pend value sent in the com-
mand control information for transaction 1 is two. By this
Pend value, the DRAM is made aware that two strobe-like
signals will appear on the BusCtl line prior to the actual
strobe signal for transaction 1. The DRAM monitors the
channel after the receipt of the command control informa-
tion for transaction 1. Based on the Pend information in the
command control information for transaction 1 and the
signals that occur on the channel after receipt of the com-
mand control information for transaction 1, the DRAM can
identify the strobe for transaction 1.
The Pend approach overcomes the disadvantages of the
constant channel monitoring approach because the DRAM
involved in a transaction does not need to know what
transpired on the channel prior to the arrival of the command
control information for the transaction. Consequently, a
DRAM may assume a powered down mode until the arrival
of a wakeup signal just prior to the transmission of a request
packet. In addition, the Pend approach does not require
transactions to be retired in the same order as the order in
which they are requested. Therefore, a controller may
specifY interleave patterns in which some transactions are
retired out of order.
Deferred Precharge Notification
At the time that a request packet is transmitted by a
controller, the controller may not have enough information
to determine whether a precharge operation should be per-
formed after the completion of the transaction. Therefore,
according to one embodiment of the invention, the com-
mand control information sent in request packets does not
contain an indication of whether or not a precharge is to be
performed after the transaction. Rather, the controller com-
municates to the DRAM whether a precharge is to be
performed when the terminate signal that initiates the ter-
mination of a transfer operation is sent to the DRAM.
Because the transmission of the terminate signal is deferred,
the determination of whether or not a precharge operation is
appropriate may be made by the controller based on infor-
mation obtained between the transmission of the request
packet and the transmission of the terminate signal.
For example, at the time that the request packet is sent,
additional requests for data from different rows in the same
DRAM may not have arrived. Therefore, it would appear
that no post-operation precharge is required. However, prior
to the transmission of the terminate signal, a request may
arrive for an operation to be performed on a different row of
the same bank within a DRAM. When the controller sends
the terminate signal for the current operation, the controller
can communicate to the DRAM that a precharge operation
is to be performed. The DRAM can therefore begin a
precharge operation for the bank containing the appropriate
row while the current data transfer operation is being
completed.
A60
US 7,287,109 B2
15 16
The technique used by the controller to communicate Referring to FIG. 14, a decoding circuit 1400 includes a
whether a precharge is to be performed after an operation plurality of pins 1402, a plurality of global control lines
preferably takes advantage of the fact that data is typically 1404, and a plurality of decode units 1406. Each decode unit
transferred as a series of one or more fixed-sized packets, 1406 corresponds to a particular global control line 1404.
where each packet contains more data than can be transmit- 5 When a multiple-bit operation code is received at pins 1402,
ted during a single clock cycle. Because the transmission of the entire operdtion code is routed to each of decode units
a single packet is performed over multiple clock cycles, the 1406. Each of decode units 1406 decodes the operation code
terminate. signal may be sent during any one of a plurality to determine the appropriate signal to apply to the control
of clock cycles to specify that a particular packet is the last line 1404 to which it corresponds.
packet For example, assume that it takes four clock cycles 10 Referring to FIG. 15, it illustrates a decode circuit 1500
to send a single packet of data, and that the DRAM is according to an embodiment of the invention. Similar to
configured to send exactly one data packet after receipt of decode circuit 1400, decode circuit 1500 includes a plurality
the terminate signal. As long as the terminate signal is sent of pins 1502, 1504 and 1506, a plurality of decode units
at any one of the four clock cycles during which the 1508,. 1510 and 1512, and a plurality of global control lines
penultimate data packet is sent, the data transmission will 15 1516, 1518 and 1520. Each of decode units 1508, 1510 and
terminate at the appropriate time. 1512 corresponds to one of the control lines 1516, 1518 and
1520. Unlike the prior art decode circuit 1400, each of
According to one embodiment of the invention, the con- decode units
1508
, 1510 and 1512 receives only the signal
troller uses the exact tiring of the terminate signal to indicate from one pin. Based on the signal from the pin and state
to the DRAM whether the DRAM is to perform a precharge 20 information stored in the decode unit, the decode unit
operation. For example, assume that the controller can applies the appropriate signal to the control line to which it
terminate a transfer at the appropriate time by sending the
corresponds.
terminate signal during any one of four clock cycles, as The advantages of decode circuit 1500 over the prior art
described above. The controller can indicate to the DRAM circuit shown in FIG. 14 include decreased wiring require-
that precharge is to be performed by transmitting the termi- 25 ments, decreased power consumption and decreased circuit
nate Sl .gna!Jn the first of the fiour possJ.ble clock cycles, and d
complexity. Specifically, only one line per pm 1s reqmre to
indicate that precharge is not to be performed by transmit- route the signals from pins 1502, 1504 and 1506 to decode
ting the terminate signal on the second of the four possible units
1508
,
1510
and 1512, respectively. Further, the com-
clock cycles. The DRAM decodes the precharge information plexity of decoders 1508, 1510 and 1512 is significantly
by determining on which of the four possible clock cycles
30
reduced.
the terminate signal appeared. The DRAM may make this For decode circuit 1500 to work correctly, the operation
determination, for example, by determining the modulus of codes transmitted by the controller must include bits that
the clock cycle on which the terminate signal was received directly correspond to the signals carried on lines 1516, 1518
relative to the clock cycle on which the corresponding strobe and
1520
. Typically, the global control lines include a
was received. 1
35 NoByteM line, a Reg line, and a Write me. The NoByteM
According to an alternate embodiment, a particular pre- line indicates whether a byte mask should be used on the
charge operation is associated with each of the four available data specified in the operation. The Reg line indicates
clock cycles. For example, the DRAM may contain four whether the operation relates to a register or to memory. The
banks of memory. The technique described above may be Write line indicates whether the operation is a read operation
extended so that a terminate signal in the first possible clock
40
or a write operation.
cycle causes the DRAM to precharge the first memory bank, FIGS. 16A and 16B illustrates an operation code encoding
a terminate signal in the second possible clock cycle causes scheme according to an embodiment of the invention. Refer-
the DRAM to precharge the second memory bank, a termi- ring to FIGS. 16A and 16B, they illustrate an operation-to-
nate signal in the third possible clock cycle causes the operation-code mapping in which bits in the operation code
DRAM to precharge the third memory bank, and a terminate
4
5 directly dictate the signals to be placed on each of the global
signal in the fourth possible clock cycle causes the DRAM control lines to perform the corresponding operation. Spe-
to precharge the fourth memory bank. Significantly, this cifically, each operation code has a bit "OP[2]" that specifies
embodiment allows the position of the terminate signal for whether a signal should be placed on the NoByteM control
an operation on one memory bank to indicate that a pre- line, a bit "OP[l]" that specifies whether a signal should be
charge operation is to be performed on a different memory 50 placed on the Reg control line, and a bit "OP[O]" that
bank. In this embodiment, the command control information specifies whether a signal should be placed on the Write
may contain a bit for specifying that no precharge is to be control line. The operation code that corresponds to each
performed, regardless of the timing of the terminate signal. possible type of operation has the various operation code
bits set so as to cause the appropriate signals to be generated
Optimized Operation Encoding
Typically, a controller indicates to a DRAM the operation
55 on the global control lines. For example, to perform a
register read directed operation, a signal must be generated
on the NoByteM and Reg control lines, but not on the Write
control line. Therefore, in the operation code that corre-
sponds to the register read directed operation, the bits that
it desires the DRAM to perform by transmitting to the
DRAM a request packet that includes an operation code that
corresponds to the desired operation. To determine how to
respond to a request packet, each of the bits of the operation
code must be wired from its point of reception on the DRAM
and to a decoder prior to being globally transmitted througli
the interface in order to control functionality. The wiring and
decoding process consumes space and power. A typical 65
circuit for performing operation code decoding is illustrated
in FIG. 14.
60 correspond to the NoByteM, Reg and Write control lines are
respectively "I", "I" and "0".
Broadcast Operations
DRAMs respond to request packets if the operations
specified in the request packets arc specifically directed to
the DR..A.M, or if the request packets specify broadcast
A61
US 7,287,109 B2
17
operations. FIG. 17 illustrates a prior art circuit for deter-
mining whether a particular DRAM should respond to an
operation request.
Referring to FIG. 17, a comparator 1702 compares the
address bits in an request packet with the device D of the
DRAM. If the address bits in the request packet do not match
the device ID, then a logical LOW is transmitted to one input
of AND gate 1706. Consequently, the output of AND gate
1706 will be LOW. The operation code contained in the
request is decoded by decode unit 1704. Decode unit 1704 10
decodes the operation code in the request packet and trans-
mits signals over lines 1708 and 1710 based on the operation
specified by the operation code. If the operation code
represents a broadcast operation, then the decode unit 1704
applies a logical HIGH to line 1710. If the operation code 15
represents a non-broadcast operation, then the decode unit
1704 transmits a signal on line 1708 indicative of the
command, and a logical LOW on line 1710. Line 1710 and
the output of AND gate 1706 are applied to an OR gate 1712.
The signal at output of OR gate 1712 determines whether the 20
DRA.M should process the specified operation. When the
specified operation is a broadcast operation, the output of
OR gate 1712 will be HIGH regardless of the output of AND
gate 1706.
Referring to FIG.l8, it illustrates a circuit for determining 25
whether a DRAM should respond to request packet, accord-
ing to an embodiment of the present invention. Similar to the
circuit shown in FIG.17, circuit 1800 includes a comparator
1802 for comparing the address bits in a request packet with
the device ID of the DRAM. However, circuit 1800 is
30
configured for a protocol in which one bit in the operation
code of a request indicates whether the request is for a
broadcast operation. Referring again to FIGS.16Aand 16B,
the operation codes employed in one embodiment include a
bit "Op[3]" that indicates whether the operation specified by
35
the operation code is a broadcast operation.
Because the operation code contains a bit which indicates
whether the operation is a broadcast operation, it is not
necessary to decode the operation code to determine whether
the operation is a broadcast operation. Rather, the value of
40
the broadcast bit is fed directly into one input of an OR gate
1804. The other input of the OR gate 1804 receives a signal
that indicates whether the address in the request matched the
device ID of the DRAM. The output of the OR gate 1804
indicates whether the DRAM should respond to the request.
45
Because the operation code for every type of operation
contains a bit that specifies whether the operation is a
broadcast operation, the need to decode the operation codes
to identify broadcast operations is avoided. Consequently,
50
circuit 1800 is clearly simpler and more efficient that the
circuit shown in FIG. 17.
Controller-Specified State Changes
18
DRAM in question is said to be in a closed state. At all other
times, the DRAM is said to be in an open state.
In the prior art, DRAMs are configured to determine
whether precharge and sense operations have to be per-
formed prior to seNicing a data transfer request from a
controller. Typically, the DRAM performs this determina-
tion by comparing the address contained in the request
packet to the current address in the bank. If the addresses
match, then the data is transmitted from the sense amplifiers
and no precharge or sense operations are required. If the
addresses do not match, then the DRAM performs a pre-
charge and sense operation to load the sense amplifiers with
data from the appropriate row, but does not seNice the data
tmnsfer request.
The overhead and complexity required for the DRAM to
perform the address comparison results in a significant cost
and performance penalty. Consequently, the present inven-
tion provides a controller that determines whether precharge
and/or sense operations are required prior to making data
transfer requests. Because the controller makes the determi-
nation, the complexity of the DRAM is reduced while the
performance of the overall data transfer system is improved.
The controller makes the determination of whether pre-
charge and/or sense opemtions are required based on the
address of the data in the operation, the current state of the
bank that corresponds to the address and the address of the
data that is currently stored in the bank. Typically, this
information is already maintained by the controller for other
purposes. Therefore, little additional overhead is required
for the controller to make the determination.
Once the controller has made the determination for a
particular data transfer operation, the controller must com-
municate the decision to the DRAM. Preferably, the con-
troller communicates the determination to the DRAM
through data sent with the command control information for
the transaction. According to one embodiment of the inven-
tion, the command control information includes two bits
("Open" and "Close") that indicate to the DRAM what
action to take with respect to the sensing and precharging the
memory cells that correspond to the operation. Based on the
current bank state and the value of the Open and Close bits,
the DRAM determines what action to perform.
In geneml, the Close bit indicates whether to precharge
the memory bank after performing the operation specified in
the command control information, and the Open bit indi-
cates whether some type of sense or precharge/sense opem-
tion must be performed before the opemtion. The actions
performed in response to the Open and Close bits depends
on the previous state of the bank in question. FIG. 19
illustrates how the combinations of values for the Open bit,
Close bit, and previous bank state are mapped to actions to
be performed according to one embodiment of the invention.
Referring to FIG. 19, if the current bank state is closed
and the Open and Close bits are "0'' and "1", respectively,
In typical DRAMs, data is not directly transmitted from
the storage cells. Rather, data is temporarily copied to sense
amplifiers prior to transmission. Typically, the sense ampli-
fiers only store one row of data. If an operation is to be
performed on a row of data other than the currently stored
row, two operations must be performed. The first operation
is referred to as a precharge operation, where pairs of bit
lines within the memory are equalized to a midpoint voltage
level. The second operation is referred to as a sense opera-
tion, where the row on which the operation is to be per-
formed is copied onto the sense amplifiers. Between the
precharge operation and the subsequent sense operation, the
55 then the DRAM performs no action in response to the data
transfer request. Since no action is performed, the state of
the bank remains closed If the current bank state is closed
and the Open and Close bits are "I" and "0", respectively,
then the DRAM senses the bank and then performs the
60 operation specified in the command control information.
After the opemtion is performed, the bank will be in the open
state. If the current bank state is closed and the Open and
Close bits are both "1 ", then the DRAM senses the bank,
performs the specified operation, and precharges the bank.
65 After these actions have been performed, the bank will be in
the closed state. If the current bank state is closed, then both
Open and Close bits cannot be "0".
A62
US 7,287,109 B2
19
If the current bank state is open and the Open and Close
bits are both "0" then the DRAM simply performs the
operation specified in the command control information.
After the operation, the bank will still be in the open state.
If the current bank state is open and the Open and Close bits 5
are "0" and "1", respectively, then the DRAM performs the
command and then precharges the memory bank. After the
bank is precharged, it will be in the Closed state. If the
current bank state is open and the Open and Close bits are
"!"and "0", respectively, then the DRAM precharges the 10
bank, senses the bank, and performs the specified operation.
After the operation is performed, the bank will be in the open
state. If the current bank state is open and the Open and
Close bits are both "!", then the DRAM precharges the
bank, senses the bank, performs the specified operation, then 15
precharges the bank. After these actions have been per-
formed, the bank will be in the closed state.
In addition to giving the controller significantly more
control over internal DRAM operation, the present invention
establishes a one-to-many correspondence between request 20
packets and specified operations. Specifically, a single
request packet can cause a DRAM to perform (1) a plurality
of DRAM core operations, (2) a DRAM core operation and
a data transfer operation, or (3) a data transfer operation and
a plurality of DRAM core operations. By increasing the 25
number of operations performed by the DRAM in response
to a request packet, the ratio of control information per
operations performed is significantly reduced.
20
bond site 2020. The control circuit 2002 receives request
packets from the controller 2004 over the channel 2008
through an I/0 unit 2030. The request packets specifY data
transfer operations and the memory banks on which the
operations are to be performed. The control circuit 2002 is
configured to detect when the specified operations require
precharge or sense operations. When a requested operation
requires a precharge or a sense operation, the operation is
placed on the queue associated with the power supply line to
which the memory bank specified in the request packet is
connected. For example, assume that control circuit 2002
receives a request packet that specifies an operation that
requires bank 2010 to be precharged, and a request packet
that specifies an operation that requires bank 2012 to be
sensed. Banks 2010 and 2012 are powered by the same
power supply line 2014. Therefore, control circuitry 2002
will place both operations in the queue 2016 associated with
power supply line 2014.
The control circuit 2002 services the operations in any
given queue one at a time. Thus, in the example given above,
the control circuitry 2002 may cause the operation on bank
2010 to be performed, then cause the operation on bank
2012 to be performed. Because the operations are serviced
Line Noise Reduction
In typical DRAMs, multiple banks of memory receive
power over the same power supply line. Every precharge or
sense operation performed on a bank of memory generates
some noise on the power supply line to which the bank is 35
connected. In general, memory banks are not aware of
operations that are concurrently being performed by other
memory banks. Consequently, two or more memory banks
that are powered over the same power supply line may
concurrently perform precharge and/or sense operations. 40
The increased noise that the power supply line experiences
due to the concurrent execution of multiple noise-producing
operations impairs the reliability of the DRAM in question
sequentially, no more than one sense or precharge operation
will be performed concurrently on banks connected to the
same power supply line. Because the control circuitry 2002
maintains separate queues for each power supply line,
precharge and sense operation may be perform concurrently
on banks that are powered by different power supply lines
30
within the same DRAM 2000. In this embodiment, the
controller 2004 is preferably configured to set the Open and
Close bits in each request packet to prevent the queues
associated with the power supply lines from overflowing.
or forces the power supply line to be larger, consuming
precious die area.
To prevent these reliability problems, those prior art
DRAMs must be exhaustively tested to ensure that all
possible sense and precharge patterns can be performed
without error. In the present invention, the DRAM includes
45
a control circuit that is configured to allow no more than one 50
bank on any given power supply line from performing
precharge or sense operations at any given time. Because the
DRAM does not allow more than one bank on a power
supply line to be charged or sensed at a time, the DRAM is
not susceptible to the noise problems that concurrent sense 55
and precharge operations create. Further, the DRAM does
not need to be tested for patterns that will never occur. In
addition, the die size of the DRAM may be reduced because
the power supply lines do not have to be able to handle
current for more than one operation. The control circuit 60
within the DRAM may enforce this restriction in a variety of
ways.
In an alternate embodiment, control circuitry 2002 is
configured to ignore request packets for operations that
require a sense or precharge operation to be performed on a
bank that is connected to the same power supply line as
another bank on which a sense or precharge operation is
currently being performed. In yet another embodiment,
control circuitry 2002 does not process request packets that
would violate the restriction, but transmits a message back
to the controller 2004 to in<licate that the request packet will
not be serviced.
While a prohibition against concurrent sense and pre-
charge operations by banks on the same power supply line
limits the amount of concurrency that can take place
between the memory banks, the overall architecture of the
present invention is designed to maximize channel utili7.a-
tion without violating this restriction. Specifically, the con-
troller adjusts the interleave of transactions in such a way as
to maximize usage of the channel. No amount of concur-
rency within a DRAM will increase the throughput of a
channel that is already fully utilized. Therefore, the enforce-
ment of a prohibition against concurrent sense and precharge
operations by banks on the same power supply line does not
detrimentally affect the performance of the data transport
system.
In an alternate embodiment illustrated in FIG. 20B, the
DRAM 2000 contains a single queue 2050. AU operations
that require the DRAM 2000 to perform a precharge or sense
operation on any memory bank within DRAM 2000 are
placed in the queue 2050 by control circuitry 2002. The
control circuitry 2002 processes the operations stored in the
In one embodiment, the control circuit includes a queue
for each power supply line. Such an embodiment is illus-
trated in FIG. 20A. Referring to FIG. 20A, a DRAM 2000
includes control circuitry 2002 and four memory banks
powered over two power supply lines that extend from a
65 queue 2050 sequentially, preventing more than one pre-
charge or sense operation from being performed at the same
time. While this embodiment does not allow the concurrency
A63
US 7,287,109 B2
21
that is possible with the one-queue-per-power supply line
embodiment, it requires less complex control circuitry.
In yet another embodiment, the control circuitry on the
DRAM does not enforce the one core operation per power
supply line restriction. Rather, control circuitry within the
controller is configured to transmit request packets by select-
ing an order and timing that will not cause more than one
core operation to be performed at the same time on banks
connected to the same power supply line. In this embodi-
ment, the DRA.M may be manufactured with power supply
lines designed to only support one core operation at a time,
even though the DRAM itself does not enforce the restric-
tion.
Example of Dynamically Adjusting Interleave
Referring to Appendix C, it illustrates a series of trans-
actions in which a controller has dynamically adjusted the
interleave. The controller transmits the wakeup signal for the
first transaction (transaction 0) over the BusCtrlline at clock
cycle 0. The controller transmits the request packet for
transaction 0 over the BusCtrl line and the BusData[8:0]
lines from clock cycle 4 to clock cycle 6. The controller
transmits column address information over the BusEnable
line from clock cycle 8 to clock cycle 10. This column
address information indicates the column address of the data
for the second and subsequent data packets that will be
involved in the transaction. The column address of the data
for the first packet is included in the request packet. At clock
cycle 10, the controller transmits the strobe signal for
transaction 0. The timing of the strobe signal indicates to the
DRAM when the DRAM is to begin retrieving and sending
data for transaction 0. In response to the strobe signal, the
DRAM begins to retrieve data from the specified columns at
clock cycle 10, and begins sending the data over BusData
[8:0]lines at clock cycle 16. The DRAM first retrieves data
from the column specified in the request packet, and then
from the columns specified in the column address informa-
tion that is sent over the BusEnable line. The controller
22
signal for transaction 1 over the BusCtrlline at clock cycle
35. The timing of the terminate signal indicates to the
DRAM when to stop sending data for transaction 1. In
response to the terminate signal, the DRAM ceases to
retrieve data after clock cycle 38, and ceases to transfer data
after clock cycle 43. A total of four oct byte data packets are
transmitted for transaction 1.
The controller transmits the wakeup signal for the trans-
action 2 over the BusCtrl line at clock cycle 20. The
10 controller transmits the request packet for transaction 2 over
the BusCtrlline and the BusData[8:0]1ines from clock cycle
24 to clock cycle 26. The controller does not transmit
column address information over the BusEnable line
because transaction 1 involves only one oct byte data packet,
15 the column address for which is included in the request
packet. At clock cycle 50, the controller transmits the strobe
signal for transaction 2. The timing of the strobe signal
indicates to the DRAM when the DRAM is to begin reliev-
ing and sending data for transaction 2. In response to the
20 strobe signal, the DRAM begins to retrieve data from the
specified columns at clock cycle 51, and begins sending the
data over BusData[8:0]1ines at clock cycle 56. The control-
ler transmits the terminate signal for transaction 2 over the
BusCtrlline at clock cycle 51. The timing of the terminate
25 signal indicates to the DRAM when to stop sending data for
transaction 2. In response to the terminate signal, the DRAM
ceases to retrieve data after clock cycle 54, and ceases to
transfer data after clock cycle 59. A single octbyte data
packet is transmitted for transaction 2.
30 The controller transmits the wakeup signal for the trans-
controller transmits the request packet for transaction 3 over
the BusCtrlline and the BusData[8:0]lines from clock cycle
44 to clock cycle 46. The "open, no-close" parameters
35 contained within the request packet indicates to the DRAM
that the DRAM must perform a precharge and sense opera-
tion prior to performing the requested data transfer. Without
waiting for the strobe signal for transaction 3, the DRAM
performs the precharge operation from clock cycle 50 to
clock cycle 57, and the sense operation from clock cycle 58
to clock cycle 65. After the sense operation, a RAS operation
is performed from clock cycle 66 to clock cycle 73. The
controller does not transmit column address information
over the BusEnable line because transaction 3 involves only
transmits the terminate signal for transaction 0 over the 40
BusCtrlline at clock cycle 15. The timing of the terminate
signal indicates to the DRAM when to stop sending data for
transfer data after clock cycle 23. A total of two oct byte data
packets are transmitted for transaction 0.
45 one octbyte data packet, the column address for which is
included in the request packet. At clock cycle 66, the
controller transmits the strobe signal for transaction 3. The
timing of the strobe signal indicates to the DRAM when the
DRAM is to begin retrieving and sending data for transac-
action 1 over the BusCtrlline at clock cycle 8. 'The controller
transmits the request packet for transaction 1 over the
BusCtrlline and the BusData[8:0]lines from clock cycle 12
to clock cycle 14. The controller transmits column address
information over the BusEnable line from clock cycle 20 to
clock cycle 31. This column address information indicates
the column address of the data for the second and subsequent
data packets that will be involved in the transaction. The
column address of the data for the first packet is included in
the request packet. At clock cycle 22, the controller trans-
mits the strobe signal for transaction 1. The timing of the
strobe signal indicates to the DRAM when the DRAM is to
begin retrieving and sending data for transaction 1. In
response to the strobe signal, the DRAM begins to retrieve
data from the specified columns at clock cycle 23, and
begins sending the data over BusData(8:0] lines at clock
cycle 28. The DRAM first retrieves data from the column
specified in the request packet, and then from the columns
specified in the column address information that is sent over
the RusEnable line. The controller transmits the terminate
50 tion 3. In response to the strobe signal, the DRAM begins to
retrieve data from the specified columns at clock cycle 66,
and begins sending the data over BusData[8:0]1ines at clock
cycle 72. The controller transmits the terminate signal for
transaction 3 over the BusCtrlline at clock cycle 67. The
55 timing of the terminate signal indicates to the DRAM when
to stop sending data for transaction 3. In response to the
terminate signal, the DRAM ceases to retrieve data after
clock cycle 70, and ceases to transfer data after clock cycle
75. A total of one octbyte data packet is transmitted for
60 transaction 3.
controller transmits the request packet for transaction 4 over
the BusCtrlline and the BusData[8:0]lincs from clock cycle
65 52 to clock cycle 54. The controller does not transmit
column address information over the BusEnablc line
because transaction I involves only one octbytc data packet,
A64
US 7,287,109 B2
23
the column address for which is included in the request
packet. At clock cycle 58, the controller transmits the strobe
signal for transaction 4. The timing of the strobe signal
indicates to the DRAM when the DRAM is to begin retriev-
ing and sending data for transaction 4. In response to the
strobe signal, the DRAM begins to retrieve data from the
specified columns at clock cycle 59, and begins sending the
data over BusData[8:0]lines at clock cycle 64. The control-
ler transmits the terminate signal for transaction 4 over the
BusCtrl line at clock cycle 59 .The timing of the terminate 1 o
signal indicates to the DRAM when to stop sending data for
transfer data after clock cycle 67. A single octbyte data
packet is transmitted for transaction 4. 15
The transactions described-above illustrate how the pro-
tocol employed by the present invention enables a controller
to dynamically adjust numerous parameters relating to the
timing and interleave of signals on the channel. For
example, each of the transactions illustrates how the con- 20
troller uses strobe and terminate signals to determine the
timing and size of data transfers. Thus, the size of the request
packets for transaction 1 and transaction 3 are equal, but four
times as much data is transmitted in transaction 1 as in
transaction 3 because of the relative delay between the 25
strobe and terminate signals for transaction 1.
In addition, the controller can dynamically adjust the Le
between a request packet and the transmission of the data
associated with the request. For example, three clock cycles
elapse between the transmission of the request packet and 30
the transmission of the strobe signal that dictates when the
DRAM starts to send data for transaction 0. In contrast,
twenty-one clock cycles elapse between the transmission of
the request packet for transaction 2 and the strobe signal that
dictates when the DRAM starts to send data for transaction 35
2.
Because the controller is able to adjust the time between
the transmission of a request packet of a transaction and the
transmission of data involved in the transaction, the con-
troller can delay the transmission of data to allow the 40
channel to be used for other purposes prior to the transmis-
sion of data. For example, the only signals sent over the
BusCtrl and BusData[8:0]lines between the request packet
for transaction 0 and the strobe for transaction 0 is a wakeup
signal for transaction 1. Therefore, the strobe signal for 45
transaction 0 is sent three clock cycles after the request
packet for transaction 0. In contrast, the signals sent over the
BusCtrl and BusData[8:0]lines between the request packet
for transaction 2 and the strobe signal for transaction 2
include the data for transaction 1, the terminate signal for so
transaction 1, the wakeup signal for transaction 3, the
request packet for transaction 3 and the wakeup signal for
transaction 4. To allow all of this information to be sent
before the data for transaction 3, the strobe signal for
transaction 3 is not sent until 24 clock cycles after the ss
request packet for transaction 3.
The transactions illustrated in Appendix C also illustrate
that the protocol of the present invention enables a controller
to alter the retirement order of transactions. In a typical
DRAM system, transactions are serviced in the same order 60
in which they are requested. However, the protocol of the
present invention enables a controller to retire transactions
out of order. In the example illustrated in Appendix C, the
request packet for transaction 3 is transmitted at clock cycle
44 and the request packet for transaction 4 is transmitted 8 65
clock cycles later at clock cycle 52. However, the strobe to
start the data transfer for transaction 4 is transmitted at clock
24
cycle 58, while the strobe to start the data transfer for
transaction 3 is not transmitted until clock cycle 66. Con-
sequently, transaction 4 is completely retired before the
transmission of the data involved in transaction 3 even
begins.
The transactions illustrated in Appendix C also illustrate
that the protocol of the present invention enables a controller
to adjust the interleave in a manner that causes the number
of transactions outstanding on the channel to vary over time.
For example, at clock cycle 15, two transactions have been
requested and none have been completed. Thus, two
requests are outstanding. At clock cycle 55, five transactions
have been requested and two have been completed. Thus,
three requests are outstanding.
As explained above, the protocol of the present invention
enables a controller to dynamically adjust (I) the time at
which data is sent relative to the time at which it is
requested, (2) the retirement order of transactions, and (3)
the number of outstanding requests. In addition, the protocol
enables a controller to dictate the core operations to be
performed by the DRAM, and the sequence in which the
DRAM is to perform the core operations. The enhanced
channel control bestowed by the protocol gives the control-
ler the flexibility necessary to maximize the channel usage,
allowing any given set of data transactions to be completed
within a shorter period of time.
In the foregoing specification, the invention has been
described with reference to specific embodiments thereof. It
will, however, be evident that various modifications and
changes may be made thereto without departing from the
broader spirit and scope of the invention. The specification
and drawings are, accordingly, to be regarded in an illus-
trative rather than a restrictive sense.
Appendix A
Explanation of Transaction Templates
1.0 Introduction
This appendix contains a transaction template that shows
the information that is communicated over a channel and the
internal DRAM core states that occur during a series of
transactions.
Timing information proceeds down the template, with
each horizontal row representing a clock cycle or two bus
samples. Each row represents 4 ns at 500 MHz or 3.75 ns at
533 MHz.
1.1 Clk Cyc Column
The first column, labeled clock cycles, represents the time
in clock cycles since the beginning of this template.
1.2 BE Column
The 2nd column labeled BE, is the state of the BusEnable
pin during that clock cycle. BusEnable is only used to send
serial addresses to the R.DRAM.
1.3 BC Column
The 3rd column labeled BC, is the state of the BusCtrl pin
during that clock cycle. BusCtrl is used to send request
packets, strobe, terminate and wakeup information. During
a request packet, this fields identifies the request number, so
requests and data can be tracked, the request type, and the
value of the Pend field for that transaction. For wakeup,
strobes, and terminates it also indicates which transaction is
being started, strobed and terminated, by the value carried
with it, i.e. (strobe 0)
1.4 BD[8:0] Column
The 4th column, labeled 80[8:0], is the state of the
BusData wires during that clock cycle. During the data
packet it indicates the transaction number and the octbyte
A65
US 7,287,109 B2
25
being sent or received. During request packets it indicates
the state of the control bits Open and Close. These bits are
used to tell the RDRAM what core operations to perform.
The state that is assumed for the bank being accessed and the
addressed bank is also included in the last field of a request
packet.
1.5 DRAM Internal State Columns
26
represent the activity in any other RDRAM, labeled L with
the lOth column being it's CAS activity, and the next four
being the activity or state of each of the 4 banks (Bank[0:3]).
1.6 Column Encoding
The column encodings consist of two numbers. The first
is the request number. The second is the octbyte number.
1.7 Bank[0:3] Encodings.
The 5th through 9th Columns represent the activity in an
RDRAM labeled 0, with the 5th column being it's CAS
activity, and the next four being the activity or state of each
of the 4 banks (Bank[0:3]). The lOth through 14th Columns
These columns include a symbol that represents an opera-
tion and the number of the transaction that caused the
10 operation. The meaning of the symbols is given in the table
below.
Symbol Name Meaning Length
p ?recharge Precharge is the 8 Clocks
closing of a page
(deassertion of
RAS) and can be
caused by closing
at the end of a
transaction, or
opening a page that
has not previously
been precharged
Sense Sense is the 8 Clocks
operation of
loading the sense
amps to prepare for
a CAS and is
caused by a
command with
Open required
RAS RAS always 8 Clock
follows the sense,
and is needed to
insure that the
minimum RAS low
time of the core is
met.
Non-interleaved precharged 4 oct I bank RWWRR
Clk 0 Bank I Bank
Cyc BEBC BD[8:01 Col 0 Col 0
- wakeupO
3
4 - reqO open
5 -read close
6 -pend 0 precharged 0
7
8
9
10 sO
11 sO
12 sO
13 sO
14 sO
15 01- sO
16 01- sO
17 OlstrobeO sO
18 01- 00 rO
19 02- 00 rO
20 02- 00 rO
21 02- 00 rO
22 02- hlnl 0 I rO
23 03- data 0 0 0 I rO
24 03- data u u u 1 rU
25 03- data 0 0 01 rO
26 0 3 - data 0 0 02
27 data 0 I 02
28 data 0 1 0 2
29 data 0 1 02
A66
US 7,287,109 B2
27 28
-continued
30 -term 0 data 0 I 03
31 data 0 2 03
32 data 0 2 03
33 data 0 2 0 3
34 data 0 2
35 -wakeup I data 0 3 pO
36 data 0 3 pO
37 data 0 3 pO
38 data 0 3 pO
39 -- req 1 open pO
40 ~ w r i t e close pO
41 -pend 0 precharged 0 pO
42 pO
43
44 11-
45 11- sl
46 11- sl
47 1 I strobe 1 sl
48 12- datal 0 sl
49 12- data 1 0 sl
50 12- data I 0 sl
51 12- data 1 0 sl
52 13- data 1 1 sl
53 1 3 -- data 1 I I 0 rl
54 13- data 1 1 1 0 rl
55 13- data 1 1 1 0 rl
56 data 1 2 10 rl
57 data 1 2 11 rl
58 data I 2 II rl
59 data I 2 II rl
60 -term 1 data 1 3 11 rl
61 data 1 3 1 2
62 data I 3 1 2
63 data 1 3 1 2
64 I 2
65 1 3
66 1 3
67 -wakeup 2 I 3
68 1 3
69 pi
70 pi
71 - req 2 open pi
72 -write close pi
73 -pend 0 precharged 0 pl
74 pi
75 pi
76 21- pi
77 21- s2
78 21- s2
79 2 I strobe 2 s2
80 2 2- data 2 0 s2
81 2 2- data 2 0 s2
82 2 2- data 2 0 s2
~ 3 2 2- data 2 0 s2
84 2 3- data 2 I s2
85 2 3- data 2 I 20 r2
86 2 3- data 2 1 20 r2
87 2 3 data 2 1 20 r2
~ ~ data 2 2 20 r2
89 data 2 2 2 1 r2
90 data 2 2 2 1 r2
91 data 2 2 2 1 r2
92 term 2 data 2 3 2 1 r2
93 data 2 3 2 2
94 data 2 3 2 2
95 data 2 3 2 2
96 22
97 23
98 23
99 -wakeup 3 2 3
100 2 3
101 p2
102 p2
103 - req3 open p2
104 -read close p2
105 -pend 0 precharged 0 p2
106 p2
107 p2
108 p2
A67
US 7,287,109 B2
29 30
-continued
109 s3
110 s3
Ill s3
112 s3
113 s3
114 3 I s3
115 31- s3
116 3Istrobe3 s3
117 31- 3 0 r3
II R 3 2- 3 0 r3
119 3 2- 3 0 r3
120 3 2- 3 0 r3
121 32- turn 3 I r3
122 33- data 3 0 3 I r3
123 3 3- data 3 0 3 I r3
124 33- data 3 0 3 I r3
125 33- data 3 0 3 2
126 data 3 I 3 2
127 data 3 I 3 2
128 data 3 I 3 2
129 - tcnn 3 data 3 I 3 3
130 data 3 2 33
131 data 3 2 3 3
132 data 3 2 3 3
133 data 3 2
134 - wakeup4 data 3 3 p3
135 data 3 3 p3
136 data 3 3 p3
137 data 3 3 p3
138 - req 4 open p3
139 -read close p3
140 -pend 0 precharged 0 p3
141 p3
142
143
144 s4
145 s4
146 s4
147 s4
148 s4
149 41- s4
150 41- s4
!51 4 I strobe 4 s4
!52 41- 40 r4
153 42- 40 r4
!54 42- 40 r4
155 42- 40 r4
156 42- turn 41 r4
!57 43- data 4 0 41 r4
158 43 data 4 0 41 r4
159 43- data 4 0 41 r4
160 43- data 4 0 42
161 data 4 I 4 2
162 data 4 1 42
163 data4 I 42
164 - tenn 4 data4 I 43
165 data 4 2 43
166 data 4 2 43
167 data 4 2 43
168 data 4 2
169 data 4 3 p4
170 data 4 3 p4
171 data 4 3 p4
172 data 4 3 p4
173 p4
--
174 p4
175 p4
176 p4
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31
Appendix B
1.0 Introduction
the information that is communicated over a channel and the
internal DRAM core states that occur during a series of
tmnsactions.
Timing information proceeds down the template, with
each horizontal row representing a clock cycle or two bus 10
533 MHz.
1.1 Clk Cyc Column
32
1.4 BD[8:0] Column
The 4th column, labeled BD[8:0], is the state of the
13usData wires during that clock cycle. During the data
packet.
The first column, labeled clock cycles, represents the time
in dock cycles since the beginning of this template.
1.2 BE Column
serial addresses to the RDRAM.
15
represent the activity in any other RDRAM, labeled 1, with
1.3 BC Column 20
being the activity or state of each of the 4 banks (Bank[0:3 ]).
packets, strobe, terminate and wakeup information. During
requests and data can be tracked, the request type, and the 25
with it, i.e. (strobe 0)
Symbol
1.6 Column Encoding
The column encodings consist of two numbers. The first
is the request number. The second is the octhyte number.
operation. The meaning of the symbols is given in the table
below.
Name
Pre charge
Sense
RAS
Meaning
?recharge is the
closing of a page
( deassertion of
RAS) and can be
caused by closing
at the end of a
transaction, or
opening a page that
has not previously
been precharged
Sense is the
operation of
loading the sense
amps to prepare for
a CAS and is
caused by a
command with
Open required
RAS always
follows the sense,
and is needed to
insure that the
minimum RAS low
time of the core is
met.
Length
8 Clocks
8 Clocks
8 Clocks
Interleaved prccharge 4 oct 2 bank I RDRAM RWWRWWRRR
Clk 0 Bank 1 Bank
Cyc BE BC BD[8:0] Col 0 Col 0
-wakeup 0
- rcqO open
-read close
-pend 1 precharged 0
A69
US 7,287,109 B2
33 34
-continued
9
10 sO
11 sO
12 sO
13 sO
14 sO
15 sO
16 sO
17 sO
18 00 rO
19 00 rO
20 0 1 wakeup I 00 rO
21 01- 00 rO
22 0 1 strobe 0 0 0 rO
23 01- 00 rO
24 02reql open 00 rO
25 0 2 write close 00 rO
26 02pend2 precharged 1 00
27 02- tum 0 I
28 03- data 0 0 0 I
29 03- data 0 0 0 I
30 03- data 0 0 0 I sl
31 03- data 0 0 02 sl
32 data 0 I 02 sl
33 data 0 I 02 sl
34 data 0 I 02 sl
35 -term 0 data 0 1 03 sl
36 data 0 2 0 3 sl
37 data 0 2 03 sl
38 data 0 2 03 rl
39 data 0 2 rl
40 -wakeup 2 data 0 3 pO rl
41 data 0 3 pO rl
42 data 0 3 pO rl
43 datJt 0 3 pO rt
44 1 I req 2 open pO rl
45 I 1 write close pO rl
46 llpend2 precharged 0 pO
47 1 I strobe 1 pO
48 12- datal 0
49 12- data I 0
50 12- datal 0 s2
51 12- data I 0 s2
52 13- data I I s2
53 13- data I I I 0 s2
54 13- data I I I 0 s2
55 13- data I I 1 0 s2
56 data I 2 I 0 s2
57 data I 2 II s2
58 data I 2 II r2
59 data I 2 11 r2
60 - tenn I data I 3 11 r2
61 data I 3 I 2 r2
62 data I 3 I 2 r2
63 data I 3 I 2 r2
64 2lreq3 open 1 2 r2
65 2 1 read close I 3 r2
66 2lpend3 precharged 1 I 3
67 21strobe2 I 3
68 22- data 2 0 I 3
69 2 2- data 2 0 pi
70 2 2 - data 2 0 pi -
71 2 2- data 2 0 pi
72 2 3- data 2 I pi
73 2 3- data 2 1 2 0 pi
74 2 3- data 2 1 2 0 pi
75 2 3 data 2 1 2 0 pl ---
76 data 2 2 2 0 pi
77 datA 2 2 2 I
78 data 2 2 2 1 s3
79 data 2 2 2 I s3
80 -term 2 data 2 3 2 1 s3
81 data 2 3 2 2 s3
82 data 2 3 2 2 s3
83 data 2 3 2 2 s3
84 2 2 s3
85 23 s3
86 2 3 r3
A70
US 7,287,109 B2
35 36
-continued
87 2 3 r3
88 3 I wakeup 4 23 r3
89 31- 3 0 p2 r3
90 3 I strobe 3 3 0 p2 r3
91 3 I- 3 0 p2 r3
92 32req4 open 3 0 p2 r3
93 3 2 write dose 3 0 p2 r3
94 3 2 pend 2 precharged 0 3 0 p2
95 3 2- tum 3 I p2
96 3 3 data 3 0 3 I p2
97 3 3- data 3 0 3 I
98 3 3- data 3 0 3 I s4
99 33- datA 3 0 3 2 s4
100 datll3 I 3 2 s4
101 data 3 I 3 2 s4
102 data 3 I 3 2 s4
103 - tenn 3 data 3 I 3 3 s4
104 data 3 2 3 3 s4
105 data 3 2 33 s4
106 data 3 2 3 3 r4
107 data 3 2 r4
108 -wakeup 5 data 3 3 r4 p3
109 data 3 3 r4 p3
110 data 3 3 r4 p3
111 datll3 3 r4 p3
112 4lreq5 open r4 p3
113 41 write close r4 p3
114 41pend2 precharged I p3
115 4 I strobe 4 P3
116 42- data 4 0
117 42- data 4 0
118 42- datll4 0 s5
119 42- data 4 0 s5
120 43- data4 I s5
121 43- data 4 I 40 s5
122 43- data4 I 40 s5
123 43- dalll4 I 40 s5
124 datll4 2 40 s5
125 data 4 2 41 s5
126 datll4 2 41 r5
127 data 4 2 41 r5
128 - tenn 4 datll4 3 41 r5
129 data 4 3 42 r5
130 data 4 3 42 r5
131 datll4 3 42 r5
132 51req6 open 42 r5
133 5 I read close 43 r5
135 5 I strobe 5 43
136 52- data 50 43
137 52- data 5 0 p4
138 52- datll5 0 p4
139 52- datll5 0 p4
140 53- data 5 I p4
141 53- datAS I 50 p4
142 53- data 5 I 50 p4
143 53- datA 5 1 50 p4
144 data 5 2 50 p4
145 data 5 2 5 I
146 data 5 2 5 I s6
147 data 5 2 5 I s6
148 - term 5 datll5 3 5 1 s6
149 data 5 3 52 s6 --
!50 datll5 3 52 s6
!51 datA 5 3 52 s6
152 52 s6
153 53 s6
!54 53 r6
155 53 r6
156 6 I wakeup 7 53 r6
157 61- 60 r6 p5
158 6 I strobe 6 60 r6 p5
!59 61- 6 0 r6 p5
160 62req7 open 6 0 r6 p5
161 6 2 read close 6 0 r6 p5
162 62pend2 precharged I 60 p5
163 6 2- tum 6 1 p5
164 6 3- datll6 0 6 I p5
165 6 3- data 6 0 6 I
A71
US 7,287,109 B2
37 38
-continued
166 6 3- data 6 0 6 I s7
167 6 3- data 6 0 6 2 s7
168 data 6 I 62 s7
169 data 6 I 6 2 s7
170 data 6 I 6 2 s7
171 - tenn 6 data 6 I 6 3 s7
172 data 6 2 63 s7
173 data 6 2 6 3 s7
174 data 6 2 70 r7
175 data 6 2 70 -- r7
176 data 6 3 70 p6 r7
177 data 6 3 70 p6 r7
178 data 6 3 7 0 p6 r7
179 data 6 3 7 0 p6 r7
180 70 p6 r7
181 70 p6 r7
182 70 p6
183 70 p6
184 7 I wakeup 8 70
185 71- 70
186 7 I st-obe 7 70
187 71- 70
188 72req8 open 7 0
189 7 2 read close 70
191 72- tum 7 I
192 7 3- data 7 0 7 I
193 73- data 7 0 7 I
194 73 data 7 0 7 I s8
195 7 3- data 7 0 72 s8
196 data 7 1 7 2 s8
197 data 7 I 7 2 s8
198 data 7 I 7 2 s8
199 - tenn 7 data 7 I 73 s8
200 data 7 2 7 3 s8
201 data 7 2 7 3 s8
202 data 7 2 8 0 r8
203 data 7 2 80 r8
204 8 I wakeup 9 data 7 3 80 r8 p7
205 81- data 7 3 80 r8 p7
206 81stmbe8 data 7 3 80 r8 p7
207 81- data 7 3 8 0 r8 p7
208 8 2- 80 r8 p7
209 8 2- 80 r8 p7
210 8 2- 80 p7
211 8 2- tum 8 I p7
212 8 3- data 8 0 8 I
213 8 3- data 8 0 8 I
214 8 3- data 8 0 8 I
215 8 3- data 8 0 8 2
216 data 8 I 8 2
217 data 8 1 8 2
218 data 8 I 82
219 - tenn 8 data 8 1 8 3
220 data 8 2 8 3
221 data 8 2 8 3
222 data 8 2 8 3
223 data 8 2
224 data 8 3 P8
225 data 8 3 P8
226 data 8 3 P8
227 data 8 3 p8
228 P8
229 P8
230 P8
231 P8
Appendix C
60
Timing infonnation proceeds down the template, with
each horizontal row representing a clock cycle or two bus
1.0 Introduction
533 MHz.
1.1 Clk Cyc Column
the information that is communicated over a chaunel and the 65
internal DRAM core states that occur during a series of The first colunuo, labeled clock cycles, represents the time
transactions. in clock cycles since the beginning of this template.
A72
US 7,287,109 B2
39
1.2 BE Column
serial addresses to the RDRAM.
1.3 BC Column
packets, strobe, tenninate and wakeup information. During
40
packet.
represent the activity in any other RDRAM, labeled 1, with
being the activity or state of each of the 4 banks (Bank[0:3]).
1.6 Column Encoding
requests and data can be tracked, the request type, and the 10
with it, i.e. (strobe 0) The column encodings consist of two numbers. The first
15 is the request number. The second is the oct byte number.
1.4 BD[8:0] Column
The 4th column, labeled BD[8:0], is the state of the
BusData wires during that clock cycle. During the data
operdtion. The meaning of the symbols is given in the table
below.
Symbol Name Meaning Length
Pre charge Precharge is the 8 Clocks
closing of a page
(deaasertion of
RAS) and can be
caused by closing
at the end of a
transaction, or
opening a page that
has not previously
been precharged
Sense Sense is the 8 Clocks
operation of
loading the sense
amps to prepare for
a CAS and is
caused by a
command with
Open required
RAS RAS always 8 Clocks
follows the sense,
and is needed to
insure that the
minimum RAS low
time of the core is
met.
Vazy data size, retirement order, outstanding requests, data time
Clk 0 Bank I Bank
Cyc BE BC BD[8:0] Col 0 Col 0
0 -wakeup 0
4 -reqO no-open
5 -read no-close
6 -pend I sensed 0
7
8 0 I wakeup I
9 01-
10 0 I strobe 0
II 01- 00
12 - req 1 no-open 00
13 -read no-close 00
14 -pend 2 sensed 0 00
15 - term 0 turn 0 1
16 data 0 0 0 I
17 data 0 0 0 1
18 data 0 0 01
A73
US 7,287,109 B2
41
-continued
19 data 0 0
20 1 1 wakeup 2 data 0 1
21 11 data 0 1
22 1 1 strobe I data 0 I
23 II- data 0 I I 0
24 12req2 no-open I 0
25 I 2 read no-close I 0
26 12pend3 sensed 0 I 0
27 12- turn II
28 13- data I 0 II
29 13- data 1 0 11
30 13- data I 0 II
31 13- data I 0 I 2
32 data I 1 I 2
33 data I I I 2
34 data I I I 2
35 -term I data 1 I I 3
36 data I 2 I 3
37 data I 2 I 3
38 data I 2 I 3
39 data I 2
40 -wakeup 3 data 1 3
41 data I 3
42 data I 3
43 data I 3
44 - n:q3 open
45 -read no-close
46 -pend 5 sensed 0
47
48 -wakeup 4
49
50 -strobe 2 p3
51 - term 2 20 p3
52 - req 4 no-open 2 0 p3
53 -read no-close 20 p3
54 -pend 0 sensed 0 20 p3
55 nrm p3
56 data 2 0 p3
57 data 2 0 p3
58 - strobe4 data 2 0 s3
59 -term 4 data 2 0 s3 40
60 s3 40
61 s3 40
62 s3 40
63 turn s3
64 data 4 0 s3
65 data 4 0 s3
66 -strobe 3 datA4 0 3 0 r3
67 -term 3 data 4 0 30 r3
68 3 0 r3
69 3 0 r3
70 3 0 r3
71 turn r3
72 data 3 0 r3
73 data 3 0 r3
74 data 3 0
75 data 3 0
What is claimed is:
1. A method of controlling a memory device having a
memory core, wherein the method comprises:
60
providing control information to the memory device,
wherein the control information includes a first code 65
which specifies that a write operation be initiated in the
memory device;
42
providing a signal to the memory device, wherein the
signal indicates when the memory device is to begin
sampling write data, wherein the write data is stored in
the memory core during the write operation;
providing a first bit of the write data to the memory device
A74
US 7,287,109 B2
43
providing a second bit of the write data to the memory
2. The method of claim 1, wherein the control information
further includes:
address information that specifies a location in the 5
memory con: for tlu: write operation;
a second code that specifies whether to perform a sense
operation; and
a third code that specifies whether to perform a precharge
operation.
3. The method of claim 1, wherein the memory device
receives the write data in alignment with the clock signal.
10
4. The method of claim 1, wherein the memory core
includes a plurality of banks, wherein each bank of the
plurality ofbanks includes a memory cell array, wherein the 15
method further includes:
transmitting bank selection information to the memory
device, wherein the bank selection information identi-
fies a bank of the plurality of banks, wherein the write
operation is initiated in a subset of the memory cell 20
array included in the bank identified by the bank
selection information; and
transmitting address information to the memory device,
wherein the address information identifies the subset of
the memory cell array. 25
44
12. A method of controlling a memory device, wherein the
memory device includes a plurality of banks, wherein each
bank of the plurality of banks includes a memory cell array,
wherein the method comprises:
providing a plurality of operation codes to the memory
device, wherein the plurality of operation codes
includes a first code which specifies that a write opera-
tion be initiated in the memory device;
providing bank selection information to the memory
device, wherein the bank selection information identi-
fies a bank of the plurality of banks, wherein the write
operation is initiated in the memory cell array included
in the bank identified by the bank selection informa-
tion;
providing address information to the memory device,
wherein the address information identifies where to
initiate the write operation in the memory cell array
included in the bank identified by the bank selection
information;
signal indicates when the memory device is to begin
receiving write data to be written during the write
operation;
providing a first bit of the write data to the memory device
providing a second bit of the write data to the memory
5. The method of claim 4, wherein the control information
further includes a second code which specifies that a pre-
charge operation be initiated in the bank identified by the
bank selection information after the write data is written to
the subset of the memory cell array.
6. The method of claim 1, wherein:
providing the first bit of the write data includes transmit-
ting the first bit of write data, to the memory device, in
a predetermined alignment with the clock signal; and
13. The method of claim 12, wherein the plurality of
operation codes further includes a second code which speci-
30 fies that a precharge operation be initiated in the bank
identified by the bank selection information after the write
data is written during the write operation.
providing the second bit of the write data includes trans- 35
mitting the second bit of write data, to the memory
device, in a predetermined alignment with the clock
signal.
7. The method of claim 1, further comprising providing,
to the memory device, a signal that indicates when the 40
memory device is to terminate the sampling of the write
data.
8. The method of claim 7, wherein the signal that indicates
when the memory device is to terminate the sampling of the
write data specifies whether the memory device is to per- 45
form a precharge operation after the write operation.
9. The method of claim 8, wherein the signal that indicates
when the memory device is to terminate the sampling of the
write data further indicates which bank of the plurality of
banks to precharge when the memory device performs the so
precharge operation after the write operation.
10. The method of claim 1, wherein the control informa-
tion is provided in a request packet.
11. The method of claim 1, further comprising:
providing to the memory device, control information that 55
specifies a read operation in the memory device, the
memory device to output read data in response to the
control information that specifics a read operation in
the memory device;
providing, to the memory device, a signal that indicates 60
when the memory device is to begin outputting read
data, wherein the read data is accessed from the
memory core during the read operation;
receiving a first bit of the read data from the memory
device during an even phase of a clock signal; and
receiving a second bit of the read data from the memory
65
14. The method of claim 12, further comprising provid-
ing, to the memory device, a signal that indicates when the
memory device is to terminate the receiving of the write data
to be written during the write operation.
15. The method of claim 14, wherein the signal that
indicates when the memory device is to terminate the
receiving of the write data further indicates whether the
memory device is to perform a precharge operation after the
write operation.
16. The method of claim 15, wherein the signal that
indicates when the memory device is to terminate the
receiving of the write data further indicates which bank of
the plurality of banks to precharge when the memory device
performs the precharge operation after the write operation.
operation codes and the address information are included in
a first packet.
18. The method of claim 17, wherein the write data is
included in a second packet, wherein the first packet and the
second packet are communicated to the memory device over
a common set of signal lines.
operation codes includes a second code which specifies that
the memory device initiate a sense operation in the bank
identified by the bank selection information.
20. A method of controlling a memory device having a
memory core, wherein the method comprises:
providing control information to the memory device,
wherein the control information includes a first code
which specifies that a transfer operation be initiated
with the memory device;
signal indicates when the memory device is to begin the
transfer operation; and
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US 7,287,109 B2
45
during the transfer operation, transferring a first bit of data
during an even phase of a clock signal, and transferring
a second bit of data during an odd phase of the clock
signal.
21. The method of claim 20, wherein the control infor-
mation further includes:
address information that specifies a memory location of
the data; and
a second code that specifies whether to perform a sense
operation, wherein the data is transferred from a row of 10
the memory core to a plurality of sense amplifiers when
a sense operation is performed.
46
22. The method of claim 20, wherein during the transfer
operation the data is transferred in alignment with the clock
signal.
23. The method of claim 20, wherein the transfer operd-
tion is a read operation.
24. The method of claim 20, wherein the transfer operd-
tion is a write operation.
25. The method of claim 20, further comprising provid-
ing, to the memory device, a signal that indicates when the
memory device is to end the transfer operation.
* * * * *
A76
A17519
A17520
A17521
A17522
A17523
A17524
A17525
A17526
A17527
A17528
A17529
A17530
A17531
A17532
A17533
A17534
A17535
5,748,914
43
causing the memory device to begin perfonning the
specified data transfer operation at a time that is based
upon when the memory device detects the strobe signal
on the bus.
44
transmitting a request packet that specifies a data transfer
operation over a channel to which the one or more
memory devices are connected. wherein the request
packet includes a value that indicates how to identify a
strobe signal associated with the data transfer operation
that will appear on a particular control line of the
channel;
3. The method of claim 2 further comprising the steps of:
5
causing the controller to select an interleave pattern based
on the specified data transfer operation and requests
received for one or more data transfer operations other
than the specified data transfer operation; and transmitting zero or more control signals with signal
causing the controller to transmit control information over characteristics identical to the strobe signal on the
the bus for at least one of the one or more data transfer
10
particular control line after transmitting the request
operations after transmitting the control information for packet and prior to transmitting the strobe signal; and
the specified data transfer operation and prior to trans- transmitting the strobe signal on the particular control
mitting the strobe signal. line.
4. The method of claim 1 further comprising the steps of: 10. The method of claim 9 wherein the value indicates
during the transfer operation, causing the controller to
15
how many signals that are identical to the strobe signal will
determine whether the memory device is to perform a appear on the particular control line prior to the strobe
precharge operation after the memory device performs signal.
the data transfer operation; 11. The method of claim 9 wherein the data transfer
at or about the end of the data transfer operation, causing operation is one of a plurality of data transfer operations to
the controller to communicate to the memory device
20
be performed over the channel, the method further compris-
whether the memory device is to perform a precharge ing the step of dynamically determining an interleave pattern
operation after the memory device performs the data for the plurality of data transfer operations, wherein the
transfer operation. amount of time between the transmission of the request
5. The method of claim 4 further wherein the step of packet and the transmission of the strobe signal varies based
causing the controller to communicate to the memory device 2S on the interleave pattern.
whether .the memory device is to perform a precharge 12. The method of claim 9 further comprising the steps of
operation after the memory device performs the data transfer
operation includes the steps of: causing the one or more memory devices to enter a
establishing a correlation between a plurality of clock powered down mode in which the one or more memory
cycles and a plurality of precharge options; 30 devices do not monitor the channel; and
selecting a pecharge option from the plurality of pre- transmitting a wakeup signal over the particular control
charge options; and line prior to transmitting the request packet, the wakeup
causing the controller to transmit the termination indica- signal causing the memory device of the one or more
tion during a clock cycle that corresponds to the memory devices that is required to service the data
selected precharge option.
35
transfer operation to exit the power down mode and to
6. A method. for use in a memory controller, for maxi- begin monitoring the channel.
mizing usage of a bus that connects the memory controller 13. A method for performing data transfers within a
to one or more memory devices, the method comprising the computer system, the method comprising the steps of:
steps of: causing a controller to perform the steps of
selecting an interleave pattern based on requests received
40
transmitting control information on a bus, the control
for a plurality of data transfer operations; and information specifying a data transfer operation and
for each data transfer operation of the plurality of data a first location of data to be transferred;
transfer operations determining a delay interval;
transmitting control information over the bus, wherein transmitting a control signal over the bus after the delay
the control information specifies the data transfer
4
5 interval bas elapse from when the step of transmit-
operation; ting the control information on the bus was per-
determining how much time must elapse between trans- formed;
mission of the control information and the start of the causing a memory device to perform the steps of
data transfer operation to provide the interleave reading the control information on the bus;
pattern; and so detecting the control signal on the bus;
transmitting a start indicator over the bus that specifies performing the specified data transfer operation on data
when the data transfer operation is to begin. stored at the first location at a time based on when the
7. The method of claim 6 wherein the step of transmitting control signal was detected on the bus.
a start indicator is performed by transmitting a delay value 14. The method of claim 13 further comprising the step of
in the control information, the delay value indicating when 55 causing the controller to change the delay interval for
the data transfer operation is to begin relative to the time at successive data transfer operations.
which the control information is transmitted over the bus. 15. The method of claim 13 further comprising the step of
8. The method of claim 6 wherein the step of transmitting causing the controller to determine a desired interleave,
a start indicator is performed by transmitting a strobe signal wherein the controller perfonns the step of determining a
a selected number of clock cycles after transmitting the 60 delay interval based on the desired interleave.
control information. wherein the number of clock cycles is 16. The method of claim 13 further comprising the steps
determined based on how much time must elapse between of:
transmission of the control information and the start of the causing the controller to transmit a terminate signal over
data transfer operation to provide the interleave pattern. the bus; and
9. A method for reducing the number of lines required to 65 causing the memory device to continue to perform the
transmit control information to one or more memory data transfer operation until detecting the terminate
devices, the method comprising the steps of: signal on the bus.
A17658
CERTIFICATE OF SERVICE
I certify that on September 7, 2012, the foregoing Brief for Appellant
Rambus Inc. was filed electronically with the Clerk of the Court for the U.S. Court
of Appeals for the Federal Circuit using the CM/ECF system and served
electronically by ECF on the following counsel:

Raymond T. Chen
William LaMarca
Coke Stewart
United States Patent and Trademark Office
Office of the Solicitor
P.O. Box 1450
Mail Stop 8
Alexandria, Virginia 22213

Jeffrey A. Lamken

CERTIFICATE OF COMPLIANCE
1. This brief complies with the type-volume limitation of Fed. R. App. P.
32(a)(7) because:

X This brief contains 13,936 words, excluding the parts of the brief exempted
by Fed. R. App. P. 32(a)(7)(B)(iii) and Local Rule 32(b).

This brief uses a monospaced typeface and contains [state the number of ]
lines of text, excluding the parts of the brief exempted by Fed. R. App. P.
32(a)(7)(B)(iii).

2. This brief complies with the typeface requirements of Fed. R. App. P.
32(a)(5) and the type style requirements of Fed. R. App. P. 32(a)(6) because:

X this brief has been prepared in a proportionally spaced typeface using
Microsoft Word in Times New Roman 14 point font, or

this brief has been prepared in a monospaced typeface using [state name and
version of word processing program] with [state number of characters per
inch and name of type style].

Jeffrey A. Lamken


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