1 Digital Logic Review

Digital Logic Circuits Review
Dr. Voicu Groza

SITE Hall, Room 5017 562 5800 ext. 2159 Groza@EECS.uOttawa.ca
CEG 2136 Computer Architecture I
Outline
Logic Functions Boolean Algebra Logic Functions Minimization Logic Gates Combinational Circuits Sequential Circuits
Specification Analysis Design
Logic function
x0 x1 x2 x3
Logic Circuit
z = F(x0, x1, x2, ) | z {0, 1}, xk {0, 1}, k = 0,1,2, F can be represented by logic expression truth table K-map
x 1
Logic Inverter
U1A
1 7404
0
0 10 20 30 40 50
t [ns]
z=x
x 0 1
z 1 0
1 0
0 10 20 30 40 50
t [ns] 3
BOOLEAN ALGEBRA
{B, =, +, , 0, 1}, where: B = set with at least 2 distinct elements; 0, 1 = 2 constants B + OR
AND = equivalence relationship, with usual properties: reflexivity: ( x B) (x = x) symmetry: ( x, y B) (x = y y = x) transitivity: ( x, y, z B) (x = y and y = z x = z) Parentheses are allowed
4
BOOLEAN ALGEBRA AXIOMS

B={0,1} OR AND
abB a1=1a=a ab=ba a (b + c) = ab + ac aa=0 (a b) c = a (b c) [2] [10] [13] [8]
5
Closeness: a+bB a, b B Identical element: aB a + 0 = 0 + a = a [1] Commutative: a, b B a+b=b+a [9] Distributive: a, b, c B a+(bc) = (a+b) (a+c) [14] Complement: a B, a a + a = 1 [7] and Associative: a, b, c B (a + b) + c = a + (b + c) [11]
[12]
BOOLEAN ALGEBRA
Proof : X. (Y+Z) = X.Y+X.Z AND rules X Y Z X. (Y+Z) X.Y+X.Z 0.X=0 1 .X = X X .X = X X .X = 0 X .Y = Y .X X . (Y . Z) = (X . Y) . Z X . (Y + Z) = X . Y + X . Z X .Y = X + Y
____________________________________________________________
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1
BOOLEAN ALGEBRA continued

Proof :
OR rules 0+X=X 1+X=1 X+X=X X+X=1 X=X X+Y=Y+X X + (Y + Z) = (X + Y) + Z X + Y . Z = (X + Y) . (X +Z) X+Y=X.Y X Y Z X + Y.Z (X+Y) . (X+Z)
_____________________________________________________________________
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 1 1 1 1 1
0 0 0 1 1 1 1 1
DeMorgans Theorems
X Y X.Y =X+Y 0 0 1 1 0 1 0 1
X.Y X+Y X+Y X.Y

_______________________________
X+Y=X.Y
1 0 0 0
1 0 0 0
1 1 1 0
1 1 1 0
Digital Logic Gates
Minterms
ABC 000 001 010 011 100 101 110 111 m0= m1 = m2 = m3 = m4 = m5 = m6 = m7 = ABC ABC ABC ABC ABC ABC ABC ABC 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1
10
Logic functions representation using Canonical form

Sum of Products: F = ABC + ABC + ABC + ABC Sum of minterms: F = (m2, m3, m5, m7) ; F = (2, 3, 5, 7) F = mi , K = {2, 3, 5, 7}
iK
A.B .C
A.B .C
minterm
A B C F 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1
F
A.B .C
A.B .C
A A
B B
C C
(m0) (m1) (m2) (m3) (m4) (m5) (m6) (m7)
Simplifying logic functions using Boolean algebra rules

F = ABC + ABC + ABC + ABC
A B C
F = (ABC + ABC) + (ABC + ABC) F = A(BC + BC) + A ( BC + BC) F = AB( C + C) + AC ( B + B) 1 1
A.B
F F = AB + AC
A.C
Logic functions representation using Karnaugh maps Karnaugh map => graphical representation of a truth
table of a logic function. Each line in the truth table corresponds to a square in the Karnaugh map. The Karnaugh map squares are labeled so that horizontally or vertically adjacent squares differ only in one variable. (Each square in the top row is considered to be adjacent to a corresponding square in the bottom row. Each square in the left most column is considered to be adjacent to a corresponding square in the right most column.) Recommending for functions represented by sum of minterms logic expressions
A BC 00 01 11 10
0 1 5
A B C ( 0) ( 1) ( 2) ( 3) ( 4) ( 5) ( 6) ( 7) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
F ... ... ... ... ... ... ... ...
B A BC 00 01 11 10 0
0 4 1 5 3 7 2 6
B
3 7 2 6
0 1
0 4
1 5
3 7
2 6
C C
4 variable logic functions representation on Karnaugh maps

A B C D F (0) (1) (2) (3) (4) (5) (6) (7) ( 8) ( 9) (10) (11) (12) (13) (14) (15) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ... ... ... ... ... ... ... ... C AB CD 00 01 11 10 00 01 A 11 10
0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10
Recommend for functions represented by sum of minterms logic expressions

AB CD 00 01 11 10 00 01 11 10
0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10 0 4 12 1 5 13 9
C
3 7 15 11 2 6 14 10
Implicants
F
Given a logic function z = F(x0, x1, x2, ) Implicant = product term that, if equal to 1, implies f = 1
whenever the implicant is 1=> f = 1 f can be 1 other times, as well: may be implied by other implicants, than the 1 at hand
ABC 0 A 0
0 4
AB B 0 1
1 5
ABC
2 6
1 1
3 7
1 0
BC ABC
C ABC AC B AC 0
0 4
1 5
3 7
1*
2 6
AB BC
A 0
1*
1 0
from the K-map point of view, an implicant is a rectangle of 1, 2, 4, 8, (any power of 2) 1s Prime Implicant = cannot be totally covered by another implicant (e.g., AC, BC, AB) Each 1 which is covered by a single implicant is marked with a star (*) Essential Prime Implicant = a prime implicant that contains at least one 1* A minimum cover of a logic function has to 15 contain all its prime implicants
Simplifying logic functions using Karnaugh maps looping

The logic function can be simplified by replacing canonical terms with a minimum cover of prime implicants, obtained by properly combining squares (looping) of the Karnaugh maps which contain 1s. Looping a pair of adjacent 1s eliminates the variable that appears in both direct and complemented form. 1 ABC 0 PI: AC, BC, AB EPI: AC, AB 0 1 00 0 0 Redundant Implicant: BC 2 3 01 1 1 6 7 C F F = (2,3,5,7 ) = AC + AB 11 0 1 4 5 0 0 0 1 10 1 0 B 0 1 A BC 00 01 11 10 1 1 0 1 3 2 AB 0 0 1 1* 0 0 0 1 1 3 1*2 A B 0 0 0 4 5 7 6 1 1 A 0 1* 1 0 0 4 1*5 17 0 6 1 BC BC 0 0 C AC AC 1 1
A B (0) (1) (2) (3) (4) (5) (6) (7) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1
F = (0,2,5,6,7,8,10,13,14,15) =
A B C D F (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1
Simplifying logic functions using Karnaugh maps more looping

Looping a quad of adjacent 1s eliminates the two variables that appears in both direct and complemented form. CD 00 AB 00 01 11 10 1* 0 0 1*
0 4
= ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
01 0
1
11 0
3
10 1 1 1 1
2
EPI*
Secondary PI
BD BC
1*
12
1* 0
13
1 0
15
14
11
10
BD
CD
F = BD + BD +
CD or BC
DeMorgans Theorem
A.B=A+B
A B
Equivalent Gate Symbols

A.B
A = B
A+B
A+B=A.B
A B
A+B
A B
A. B
SoP & PoS implementation
19
TWO-LEVEL NAND gate implementation of the Sum-of-Product logic functions

F = AB + AC
A B C
NAND gates are faster than ANDs and ORs in most technologies
X=(X)
A B C
F
A
Incompletely Specified Logic Functions

F = (0,1,3,7,8,12 ) + dc(5,10,13,14)
A B C D F (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 x 0 1 1 0 x 0 1 x x 0 dc -> x = dont care terms EPI* CD 00 AB 00 01 11 10 1 0 1* 1
0 4
01 1
1
11 1*
3
10 0 0 x x
2
Secondary PI ABC
AD
x 1* x 0
13 9
12 8
0 0
15 11
14
AD
10
BC D
F = AD + AD +
ABC or BCD
21
Combinational Circuits
A combinational circuit is a setup of a number of connected logic gates implementing the logic function between n input variables and m output variables. In a combinational circuit, the output is time-independent and does only depend on the circuit's input In a combinational circuit, the output is re-computed" as soon as a change in the input occurs, and it is presented to the output with a delay
x0 x1 x2 x3 z = F(x0, x1, x2, ) | z {0, 1}, xk {0, 1}, k = 0,1,2, F can be represented by logic expression truth table K-map
22
Logic Circuit
Combinational Circuit Design Procedure

1. Define the problem 2. Assign different letter symbols to the input and output variables 3. Derive the truth table defining the relationship between the inputs and the outputs 4. Obtain the simplified boolean expression for each output variable 5. Draw the circuit's logic diagram Cout A Half Adder HA S B A B Cout S 0 0 0 0 Cout 0 1 0 1 Cout = (A and B) HA A 1 0 0 1 S S = A exor B B 1 1 1 0 23
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
Cin 0 1 0 1 0 1 0 1
Cout 0 0 0 1 0 0 0 1
S 0 1 1 0 0 1 1 0
Full Adder
Equations are modified as follows.

Cout = ((A exor B) and CIN) or (A and B). S = A exor B exor CIN.
A B C_IN
HA1 HA2
C_OUT SUM
24
Sequential Circuits
The output of sequential circuits is logic function of the present state of external inputs, but also on the state of these inputs in past. Therefore, they are also referred to as circuits with memory. The sequential circuits are formed by additional feedback signals, looped backward from the output to the input of the circuit (referred to as signals of internal state of the circuit). By this backward loop, the dependence on previous values of inputs is implemented as dependence on the current internal state of the machine. The sequential switching circuits are
Asynchronous circuits = operate at time events defined by changes of inputs Synchronous circuits = operate at time events defined by additional control signal called clock.
Memory
25
Sequential Circuits
Sn Xn Sn+1 = (Sn,Xn) Sn+1 Sn
Memory
Zn
Zn = (Sn,Xn)
S-R Latch
Q S R Q
Q R
26
ELEMENTARY MEMORY ELEMENTS: I1 LATCHES AND FLIP-FLOPS
I1 I2 F 0 0 1 1 0 1 0 1
F 1 1 1 0
S-R Latch
(Set-Reset) S Q
S=0
I2
Q =1 S=0
Q =1
R= 0 R S R 0 0 1 1 0 1 0 1 Q Q Q S =1
Q =1
SET
R= 1 Q =0
RESET
Q =0 Q =1
S =1
1 1 1 0 0 1 Q Q
Weird state!! Set state Reset state Hold state HOLD
R= 0
Q =1 R= 1 Q =0
SR latch
S R Q
FUNCTIONAL or CHARACTERISTIC TABLE

St 0 0 1 1 Rt Qt+t 0 Qt 1 0 0 1 1 1 Function Hold Reset Set Forbidden (non-sense)
EXCITATION TABLE
Qt Qt+t 0 0 0 1 1 0 1 1 S t Rt 0 x 1 0 0 1 x 0
Q Q
CHARACTERISTIC EQUATION:
Qt + t = St + Qt R t condition : St Rt = 0
28
JK Flip Flop
Positive-Edge -Triggered JK Flip-Flop (rising edge)

Jn Kn Qn+1 Function 0 0 1 1 0 1 0 1 Qn 0 1 Qn Hold Reset Set Toggle
EXCITATION TABLE
Qn Qn+1 Jn Kn 0 0 1 1 0 1 0 1 0 1 x x x x 1 0
J
CLK
K
Negative-Edge -Triggered JK Flip-Flop (falling edge)
J
CLK
CHARACTERISTIC EQUATION:
Qn +1 = Qn J n + Qn K n
29
Synchronous D Flip-Flop
Positive-Edge -Triggered D Flip-Flop D CLK Q Q
FUNCTIONAL CHARACTERISTIC
Dn Qn Qn+1 0 0 1 1 0 1 0 1 0 0 1 1
EXCITATION
Qn 0 0 1 1 Qn+1 Dn 0 1 0 1 0 1 0 1
Qn+1 = Dn
D CLK Q
Q = Din* The state of the flip-flops output Q copies input D when the positive edge of the clock CLK occurs Din* Input data D may change
Dn = Qn+1
1 0 1 0 Positive-Edge-Triggered D Flip-Flop
T Flip-Flop
Positive-Edge -Triggered T Flip-Flop (rising edge)
T CLK Q Q

Tn Qn Qn+1 0 0 0 0 1 1 1 1 0 1 1 0
EXCITATION TABLE
Qn 0 0 1 1 Qn+1 0 1 0 1 Tn 0 1 1 0
Qn+1 = Qn T + Qn T
31
SEQUENTIAL CIRCUITS
Sn Next State Logic Sn+1 = (Sn,Xn) Transition function
Sn+1 State Register
Sn
Flip Flops
Xn
Output Logic Zn = (Sn,Xn) Output function

Clk
32
Zn
Mealy FSM
Output based on present state and present input
State Register
Next state
s(n)
present state
x(n)
Present input
s(n+1)
z(n)
clk
Moore FSM Output based on present state only

State Register
Next state
s(n)
present state
z(n)
33
x(n)
Present input
s(n+1)
clk
SEQUENTIAL CIRCUITS ANALYSIS

D (Transparent) Latch
D S Q Enable D 0 Q R Enable 1 1 x 0 1 Q Q Q Q 0 1 1 0 D-FF Characteristic (functional) table
S=D.Enable R=D.Enable Q Q Q Q Q Q
USE SR Characteristic (functional) table S R 0 0 1 1 0 1 0 1 Q Q 1 1 0 Q 1 0 1 Q
Q(t+t) = D(t)
Enable D S R 0 0 1 1 0 1 0 1 1 1 1 1
1 0 0 1 0 1 1 0
When the Enable input is =1 (i.e. TRUE or HIGH) the information present at the D input is stored in the latch and will appear as it is at the Q output ( => it is like that there is a transparent path from the D input to the Q output)
D Latch
D S Q Enable D 0 0 0 1 S R 1 1 1 1 1 0 0 1 Q Q Q Q Q Q 0 1 1 0
Enable
Enable
Q R
1 0 1 1
1 0 1 0 1 0 1 Hold 0 1 0
D S R Q
Holdstate Transparent state
Holdstate

Latch 1 Latch 2
Synchronous D Flip-Flop
Q Q
Q Q
D1
Q Q
Positive-Edge -Triggered D Flip-Flop D CLK Q Q
Enab.
Enab.
CLK
D CLK EN1 D1 EN2 Q
EN1
Din*
EN2
1 Input data D may change 0 1 0 1
Latch 1 is Holding Latch 1 is Transparent
Latch 1 is Transparent
0 1 0 1 0 1 0
D1 = Din*
Latch 2 is Holding Latch 2 is Transparent
Changed input data D enter Latch 1

Latch 2 is Holding
Q = D1 = Din* The state of the flip-flops output Q copies input D when the positive edge of the clock CLK occurs
Positive-Edge-Triggered D Flip-Flop
Sequential Circuit Design Procedure

Step 1: (State Table: transition and output functions ) Make a state table based on the problem statement. The table should show the next states Sn+1 and outputs Zn as functions of present states Sn and inputs Xn (transition function: Sn+1 = (Sn,Xn), output function Zn = (Sn,Xn). A state table without is called transition table - it shows only Sn+1 = (Sn,Xn). It may be easier to find a state diagram first, and then convert that to a table Step 2: (States Binary Encoding) Assign binary codes to the states in the state table, if you havent already. If you have N states, your binary codes will have at least log2 N digits, and your circuit will have at least log2 N flip-flops Step 3: (Excitation Table and Equations) For each flip-flop and each row of your state table, find the flip-flop input values that are needed to generate the next state from the present state. You can use flip-flop excitation tables here. Step 4: Find simplified equations for the flip-flops inputs & the circuit outputs Zn. Step 5: Build the circuit!
37
CEG 2136 Computer Architecture I D-Latch Characteristic (functional) table En D 0 1 1

En 0 0 0 0 1 1 1
Design D-Latch using SR Latch

SR Excitation Table
Qt 0 0 1 1
Qt 0 1 0 1 0 1 0 1
Qt+t 0 1 0 1
Qt+t 0 1 0 1 0 0 1 1
St 0 1 0 x
S 0 x 0 x 0 0 1 x
Rt x 0 1 0
R x 0 x 0 x 1 0 0
Qt+t Qt 0 1
D 0 0 1 1 0 0 1 Qt 0 1 0 1 0 1 0 Step 1
D Enable
Step 3 Comb. Circuits
x 0 1
Qt+t 0 1 0 1 0 0 1
En 0 0 0 0 1 1 1 1
D 0 0 1 1 0 0 1 1
Qt 0 1 0 1 0 1 0 1
S 0 x 0 x 0 0 1 x
R x 0 x 0 x 1 0 0
1 1 1 1 State table of the Sequential Circuit to be Designed
Design D-Latch using SR Latch

SR Excitation Table
Qt 0 0 1 1 I Qt 0 1 0 1 0 1 0 1 Qt+t 0 1 0 1 0 0 1 1 S 0 x 0 x 0 0 1 x Qt+t 0 1 0 1 St 0 1 0 x II R x 0 x 0 x 1 0 0 0 1 R 3 Rt x 0 1 0 D S Q 4 R D S
Step 4 En DQt 00 01 11 10 Enable
S = En.D R = En.D 5
Step 5
Enable
Step 3
Step 1
S R
En D 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1
0 1
0 0 x 1 x 3 0*2 0
4
0*5 x7 1 6 En.D D
S = En.D R = En.D 5 Q
En DQt 00 01 11 10
S En R Q
x 0 0 1 0 3 x*2 x
4
1 5 07 0 6
En.D
SEQUENTIAL CIRCUITS ANALYSIS

DA= x A +x B = A+ Transition function DB= x A = B+ Output function y = x A +x B
State Table
State Register
Present State In
Next State
Out
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
A+ 0 0 0 1 0 1 0 1
B+ 0 1 0 1 0 0 0 0
y 0 0 1 0 1 0 1 0
Logic Diagram State Diagram

40
SEQUENTIAL CIRCUITS DESIGN

Finite State Machine FSM => => => => Transition Table
State Diagram
x=
Step 1
x=0
Sn+1 = (Sn,Xn) => => => =>

x=1
Present State Sn
In x 0 1 0 1 0 1 0 1
Next State Sn+1
A 0 0 0 0 1 1
B 0 0 1 1 0 0 1 1
A'
B'
00
1 x=
x=0
01
x=
11
1 x=
10
x=0
1 1
SEQUENTIAL CIRCUITS DESIGN FSM => => => Transition Table

x=0
Step 1
Sn+1 = (Sn,Xn) => => => =>

x=1
Present State Sn
In x 0 1 0 1 0 1 0 1
Next State Sn+1
A 0 0 0 0 1 1
B 0 0 1 1 0 0 1 1
A' 0
B' 0
x=
00
1 x=
x=0
01
x=
11
1 x=
10
x=0
1 1
SEQUENTIAL CIRCUITS DESIGN FSM => => => Transition Table

x=0
Step 1
Sn+1 = (Sn,Xn)
x=1
Present State Sn
In
Next State Sn+1
=0
00
1 x=
=> => => =>

x=0
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
x
0 1 0 1 0 1 0 1
A' 0
B' 0
01
x=
11
1 x=
10
x=0
SEQUENTIAL CIRCUITS DESIGN FSM => => => Transition Table Step 1
x=0
Sn+1 = (Sn,Xn)
x=1
Present State Sn
In
Next State Sn+1
=0
00
1 x=
=> => => =>

x=0
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
x
0 1 0 1 0 1 0 1
A' 0 0
B' 0 1
x=
11
1 x=
10
x=0
SEQUENTIAL CIRCUITS DESIGN FSM => => => Transition Table Step 1
x=0
Sn+1 = (Sn,Xn) => => => =>

x=1
Present State Sn
In
Next State Sn+1
=0
00
1 x=
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
x
0 1 0 1 0 1 0 1
A' 0 0 0 1 1 1 1 0
B' 0 1 0 0 0 1 1 0
x=0
x=
11
1 x=
10
x=0
FSM Excitation Table

A
Next State Excitation Equations State Register JA
clk
Step 3
B 0 0 1 1 0 0 1 1
x 0 1 0 1 0 1 0 1
A' 0 0 0 1 1 1 1 0
B' 0 1 0 0 0 1 1 0
JA
KA
JB
KB
0 0 0 0
QA
Sn
KA Combinational Circuits JB
Clk
QB
1 1 1 1
KB
Clk

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 A' 0 0 0 1 1 1 1 0 B' 0 1 0 0 0 1 1 0 JA 0 KA x JB KB 0 0 1 1
Step 3
Qn Qn+1 0 1 0 1 Jn Kn 0 1 x x x x 1 0
JK FF Excitation Table

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 A' 0 0 0 1 1 1 1 0 B' 0 1 0 0 0 1 1 0 JA 0 KA x JB 0 KB x 0 0 1 1
Step 3
Qn Qn+1 0 1 0 1
Jn Kn 0 1 x x x x 1 0

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 A' 0 0 0 1 1 1 1 0 B' 0 1 0 0 0 1 1 0 JA 0 0 KA x x JB 0 1 KB x x 0 0 1 1
Step 3
Qn Qn+1 0 1 0 1
Jn Kn 0 1 x x x x 1 0
SEQUENTIAL CIRCUITS DESIGN Efficient Derivation of JK Excitation Equations

Qn Qn+1 0 0 1 1 0 1 0 1 Jn Kn 0 1 x x x x 1 0
Step 3 Qn+1 if Qn= 0 (J = next state where present state is 0) J= x if Qn= 1 (J = dont care where present state is 1)
Qn Qn+1 0 0 1 1 0 1 0 1
Jn Kn 0 1 x x x x 1 0
Qn+1 if Qn= 1 K= x
(K = complement of the next state
where present state is 1) if Qn= 0 (K = dont care where present state is 1)
FSM Excitation Table (JA)

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 A' 0 0 0 1 1 1 1 0 B' 0 1 0 0 0 1 1 0 JA 0 0 0 1 x x x x KA x x JB 0 1 KB x x Qn Qn+1 0 0 1 1 0 1 0 1
Step 3
Jn Kn 0 1 x x x x 1 0
Qn+1 if Qn= 0 J= x if Qn= 1
FSM Excitation Table (JB)

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 A' 0 0 0 1 1 1 1 0 B' 0 1 0 0 0 1 1 0 JA 0 0 0 1 x x x x KA x x JB 0 1 x x 0 1 x x KB Qn Qn+1 0 0 1 1 0 1 0 1
Step 3
Jn Kn 0 1 x x x x 1 0
Qn+1 if Qn= 0 J= x if Qn= 1
FSM Excitation Table (KA)

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 A' 0 0 0 1 1 1 1 0 B' 0 1 0 0 0 1 1 0 JA 0 0 0 1 x x x x KA x x x x 0 0 0 1 JB 0 0 x x 0 1 x x KB Qn Qn+1 0 0 1 1 0 1 0 1
Step 3
Jn Kn 0 1 x x x x 1 0
Qn+1 if Qn= 1 K= x if Qn= 0
FSM Excitation Table (KB)

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 A' 0 0 0 1 1 1 1 0 B' 0 1 0 0 0 1 1 0 JA 0 0 0 1 x x x x KA x x x x 0 0 0 1 JB 0 0 x x 0 1 x x KB x x 1 1 x x 0 1 Qn Qn+1 0 0 1 1 0 1 0 1
Step 3
Jn Kn 0 1 x x x x 1 0
Qn+1 if Qn= 1 K= x if Qn= 0
Excitation Equations & Implementation

A B x A' B' JA KA JB KB 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1 0 1 1 0 0 1 0 x 1 0 1 1 1 x 1 1 0 1 1 x 1 1 1 0 0 x x x x x 0 0 0 1 0 0 x x 0 1 x x x x 1 1 x x 0 1
Step 4 JA
Bx A 0 1 B 00 01 11 10
KA
Bx
A 0 1
B 00 01 11 10
0 0 01 1 3 0 2 4 5 7 6 x x x x
x
x 0 x1 x3 x2 4 5 7 6 0 0 1 0
x
KA = Bx Step 5
JA = Bx KB
Bx A 0 1 B 00 01 11 10
JB
A 0
B Bx 00 01 11 10
00 11 x3 x2 4 5 7 6 0 1 x x
x
x 0 x1 1 3 0 2 4 5 7 6 x x 1 0
x
JB = x
KB = x
Synchronous 4-bit Counter

Reset 0001 0011 0010 0110 1110 0000 1000 1100 1101 1111
Present state Sn Q3 Q2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 x x 0 x 1 x x x 1 1 0 1
Next state Sn +1 Q3 Q2 0 0 0 0 x x 0 x 1 x x x 1 1 1 1 Q1 0 0 1 0 x x 1 x 0 x x x 0 1 1 1 56 Q0 0 0 1 1 x x 0 x 0 x x x 1 1 0 0
C o u n t e r D e s i g n
57
Present state Sn Q3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Q3 1 0 0 0 x x 0 x 1 x x x 1 1 0 1
Next state Sn +1 Q2 0 0 0 0 x x 0 x 1 x x x 1 1 1 1 Q1 0 0 1 0 x x 1 x 0 x x x 0 1 1 1 Q0 0 0 1 1 x x 0 x 0 x x x 1 1 0 0
Q3 input J3 1 0 0 0 x x 0 x x x x x x x x x K3 x x x x x x x x 0 x x x 0 0 1 0
Q2 input J2 0 0 0 0 x x x x 1 x x x x x x x K2 x x x x x x 1 x x x x x 0 0 0 0
Q1 input J1 0 0 x x x x x x 0 x x x 0 1 x x K1 x x 0 1 x x 0 x x x x x x x 0 0
Q0 input J0 0 x 1 x x x 0 x 0 x x x 1 x 0 x K0 x 1 x 0 x x x x x x x x x 0 x 1

Excitation Equations
Q 1Q 0 Q 3Q 2 00 01 11 10 1 x x x 0 x x x 0 x x x x x 0 00 01 11 10 Q 1Q 0 Q 3Q 2 00 01 11 10 x x 0 0 x x 0 x x x 0 x x x 1 x 00 01 11 10 Q 1Q 0 Q 3Q 2 00 01 11 10 0 x x 1 0 x x x 0 x x x 0 x x x 00 01 11 10 Q 1Q 0 Q 3Q 2 00 01 11 10 x x 0 x x x 0 x x x 0 x x 1 0 x 00 01 11 10
J 3 = Q1 Q0
Q1Q0 Q3Q2 00 01 11 10 0 x 0 0 0 x 1 x x x x x x x x x 00 01 11 10 Q1Q0 Q3Q2 00 01 11 10
K 3 = Q1 Q0
00 01 11 10 Q1Q0 Q3Q2 x x x x x x x x 1 x 0 x 0 0 0 x 00 01 11 10 0 x 1 0
J 2 = Q3
00 01 11 10 Q1Q0 Q3Q2 x x x x x x x x 1 0 0 x 00 01 11 10 x x x x 00
K 2 = Q3
01 11 10
1 x 0 x
0 x 1 x
x x x x
J 1 = Q3 Q0
K1 = Q3 Q0
J 0 = Q2 Q1
K 0 = Q3 Q1
58

Implementation with JK flip-flops
59
Modulo 16 Synchronous Counter using D Flip-Flops

Q3 Q2 Q1 Q0 4-Bit BINARY COUNTER CK
3
0 15 14
1
CL
5
6
7 12 11 10 9 8
CL
Q =i = 0 Qi . 2i
1
13
CK CL
0 1 0
0 1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 0 1 2 3 4 5 6

DECIMAL STATE Q 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Present STATE OF THE COUNTER Q3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The next state = FLIP FLOP INPUTS D3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D1 D0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Modulo 16 Synchronous Counter

Using D flip-flops has the distinct advantage of a straightforward definition of the flip-flop inputs: the current state of these inputs is the next state of the counter Qn +1 = Dn. The logic equations for all four flip-flop inputs D3, D2, D1, and D0 are derived from this truth table as Q3 Q2 functions of the 00 01 11 10 Q1 Q0 current states of the counters flip-flops: 00 0 4 12 8 Q3, Q2, Q1, and Q0. 01 1 5 13 9 Karnaugh maps can 11 3 7 15 11 be used to simplify 2 6 14 10 10 these equations.
Q3 Q2 Q1 Q0 00 01 11 10
Q3 Q2 Q1 Q0 00 01 11 10
D3
00 01 11 10 0 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1
Q3 Q2 Q1 Q0 00 01 11 10
D2
00 01 11 10 0 0 1 0 1 1 0 1 1 1 0 1 0 0 1 0
D1
00 01 11 10 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Q3 Q2 Q1 Q0 00 01 11 10
D0
00 01 11 10 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

Excitation Equations
Q3 Q2 Q1 Q0 00 01 11 10
Dn = Qn+1
Q3 Q2 Q1 Q0 00 01 11 10
D3
00 01 11 10 0 0 0 0 0 0 1 0 1 1 0 1 1 1 1 1
D2
00 01 11 10 0 0 1 0 1 1 0 1 1 1 0 1 0 0 1 0
D3 = Q3. Q2 + Q3. Q1 + Q3.Q0 + Q3.Q2.Q1.Q0
D2 = Q2. Q0 + Q2. Q1 + Q2. Q1. Q0
Q3 Q2 Q1 Q0 00 01 11 10
D1
00 01 11 10 D1 = Q1. Q0 + Q1. Q0
Q3 Q2 Q1 Q0 0 1 0 1
D0
00 01 11 10 D0 = Q0
0 1 0 1
0 1 0 1
0 1 0 1
00 01 11 10
1 0 0 1
1 0 0 1
1 0 0 1
1 0 0 1

CL
CK Q0
D CLK R Q Q

Implementation
Dn = Qn+1
Q0
Q1
D CLK R Q Q
Q1
Q2
D Q Q
D0 = Q0 D1 = D2 = Q1. Q0 Q2. + Q1. Q0
CLK R
Q2
Q0 + Q2. Q1 + Q2. Q1. Q0

D Q Q
Q3
CLK R
D3 = Q3. Q2 + Q3. Q1 + Q3.Q0
+ Q3.Q2.Q1.Q0
Q3

1 Digital Logic Review

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

1 Digital Logic Review

Uploaded by

Copyright:

Available Formats

Digital Logic Circuits Review

Dr. Voicu Groza

CEG 2136 Computer Architecture I

CEG 2136 Computer Architecture I

CEG 2136 Computer Architecture I

CEG 2136 Computer Architecture I

BOOLEAN ALGEBRA AXIOMS

CEG 2136 Computer Architecture I

CEG 2136 Computer Architecture I

BOOLEAN ALGEBRA continued

CEG 2136 Computer Architecture I

X.Y X+Y X+Y X.Y

CEG 2136 Computer Architecture I

Digital Logic Gates

CEG 2136 Computer Architecture I

CEG 2136 Computer Architecture I

Logic functions representation using Canonical form

(m0) (m1) (m2) (m3) (m4) (m5) (m6) (m7)

CEG 2136 Computer Architecture I

Simplifying logic functions using Boolean algebra rules

F = (ABC + ABC) + (ABC + ABC) F = A(BC + BC) + A ( BC + BC) F = AB( C + C) + AC ( B + B) 1 1

CEG 2136 Computer Architecture I

F ... ... ... ... ... ... ... ...

CEG 2136 Computer Architecture I

4 variable logic functions representation on Karnaugh maps

Recommend for functions represented by sum of minterms logic expressions

CEG 2136 Computer Architecture I

CEG 2136 Computer Architecture I

Simplifying logic functions using Karnaugh maps looping

A B (0) (1) (2) (3) (4) (5) (6) (7) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

CEG 2136 Computer Architecture I

Simplifying logic functions using Karnaugh maps more looping

CEG 2136 Computer Architecture I

Equivalent Gate Symbols

CEG 2136 Computer Architecture I

SoP & PoS implementation

CEG 2136 Computer Architecture I

TWO-LEVEL NAND gate implementation of the Sum-of-Product logic functions

CEG 2136 Computer Architecture I

Incompletely Specified Logic Functions

CEG 2136 Computer Architecture I

CEG 2136 Computer Architecture I

Combinational Circuit Design Procedure

CEG 2136 Computer Architecture I

Equations are modified as follows.

CEG 2136 Computer Architecture I

CEG 2136 Computer Architecture I

CEG 2136 Computer Architecture I

ELEMENTARY MEMORY ELEMENTS: I1 LATCHES AND FLIP-FLOPS

Weird state!! Set state Reset state Hold state HOLD

CEG 2136 Computer Architecture I

FUNCTIONAL or CHARACTERISTIC TABLE

CEG 2136 Computer Architecture I

FUNCTIONAL or CHARACTERISTIC TABLE

CEG 2136 Computer Architecture I

CEG 2136 Computer Architecture I

FUNCTIONAL or CHARACTERISTIC TABLE

CEG 2136 Computer Architecture I

Sn+1 State Register

Output Logic Zn = (Sn,Xn) Output function

CEG 2136 Computer Architecture I

Moore FSM Output based on present state only

CEG 2136 Computer Architecture I

SEQUENTIAL CIRCUITS ANALYSIS