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Vrp CN-1
Vrn
CN-2
C1
C0
C0A
Vrn
(a)
Vrp CN-1 CN-2 dN-2,d=0 Vrn C1 C0 C0A CN-2 Vrp CN-1
(c)
C1 C0 C0A dN-2,r=0
Vrn
(b)
(d)
Fig. 2: Direct switching (a), (b), and reverse switching (c), (d)
SARt vIN D
SAR0
40 30 20 10 0
SARk
D
Direct Switching Reverse Switching 0 0.1 0.2 0.3 0.4 0.5 0.6 Analog Input Signal 0.7 0.8 0.9 1
1 z 1
tdig
Fig. 3: Transfer characteristics for direct and reverse switching in radix-1.8 SAR ADC
0
Power[dBFS]
10
-50
10
P/fs[pJ]
-100
200
400
0
Power[dBFS]
1000
1200
1400
dB
60 55 50
10
SNDR=49.72dB SFDR=59.06dB
-50
45
10
FoM
=100
fJ/c-s
ISSCC VLSI This Work 30 35 SNDR[dB] 40 45 50
-100
200
400
1000
1200
1400
40
10
-1
FoM
=10fJ
20
/c-s
25
500
1000
1500 fin[MHz]
2000
2500
15
Fig. 8: Energy per conversion (ADCs with fs>1GHz published at ISSCC and VLSI from 1997 to 2011) TABLE 1: Performance Summary Sampling rate Resolution Peak SNDR SNDR SFDR ERBW Input bandwidth Input Chip area Analog core area Technology Supply voltage Power 2.8GS/s 11b (10b with <0.5dB SNDR degradation) 50.9dB >48dB (up to 1.5GHz) >55dB (up to 2GHz) 1.5GHz >3GHz 1.8Vpp-diff 1.7mm2 0.18mm2 ST 65nm 1.2 V 44.6mW
Fig. 9: Die photo Analog core area: 0.4 x 0.45mm2 Chip area: 1.03 x 1.66mm2
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