System of data recording based on FPGA and DSP

Jun Wang1, Fuyang Zhang2, Peng Wu

School of Electronic and Information Engineering, Beihang University, Beijing 100191, China Email: 1: wangjun203@gmail.com 2: ericforzj@gmail.com
AbstractData storage device system plays a very important role in data analysis and scientific research. This paper designs and implements an data storage device system based on FPGA and DSP. The device of DSP controls the transmit and storage of data in the device of Flash. The device communicates with device through the implementation of hardware and the standard protocol of HDLC is realized on FPGA. The transmission of data and command is achieved by the communication between computer and USB device on the basis of protocol of USB2.0. Keywords- data storage FPGA DSP

transformed from the 5V power supply. Function modules are shown in Figure 1.

I.

INTRODUCTION

Storaging and analyzing data is becoming an important and necessary means in a variety of testing and scientific research. Data storage devices (commonly known as black box) in real life has been applied widely already[1]. Automotive and shipbased black box are gradually applied[2]. But the data recording devices have disadvantages such as high cost and applications in harsh environmental conditions. Given these reasons, a self-designed data recording device system is introduced in this paper. The design and implementation of a high-capacity data storage system based on FPGA and DSP is introduced in this paper. To meet the requirements of the design, the system is equipped with two storage capacity of 256M of FLASH memory chips. Data communication and command transmission between the system and external devices is based on bus and the system adopts a chip with its rate up to 20Mbps. Meanwhile, the system can collect the amount of raw data from external devices. When collecting the record data, the system gets connection with the computer in the protocol of USB2.0 and it can complete the function of the package, collection and analysis of data at any time. II. OVERALL DESIGN OF THE SYSTEM HARDWARE

Figure 1 Schematic diagram of system function module Throughout the system, FPGA chip controls the module of USB communications of uploading data to computer, the cache module to communicate with DSP and the bus communication module, which is the one to send and receive data based on HDLC communication protocol. DSP chip takes charge of selfchecking of the system when in the data transmission system of self-recording mode, the module of reading and writing FLASH memory chip, the module of analog data acquisition and the module with communicate with FPGA. III. FUNCTION AND IMPLEMENTATION OF FPGA MODULE

As the core of the system of control module, FPGA chip controls system functional blocks as follows: A. USB module to communicate with computer. When the system connecting with the computer, the user can send commands to the system through the interface on the computer to complete the functions of commands binding, data stored searching, collecting and erasing. In the FPGA design, there is a computer instruction decoding module and USB data transmission control module. When the computer is connected with the system as designed, it could communicate with hardware devices through software interface. CY7C68013, EZ-USB FX2 chip produced by Cypress, is chosen to be the chip as the connection between the two devices[3]. To facilitate communication and system interoperability, USB Slave FIFO mode is used[4]. FPGA controls over reading, writing and enabling signals of data bus and control bus of the chip according to FIFO empty flag signal, realizing high-speed data transmission. Initialization program of the chip is stored in the matched firmware chip

In order to meet the function requirement of system that real-time recording data and computer collecting data, the system is designed to be mainly controlled by FPGA and DSP chip with the bus communication interface, analog data acquisition interface and computer data communication interface. The entire system is based on a variety of power supply modules. Chips operate well on a variety of level

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24LC64[5]. Figure 2 is the system function diagram when hardware platform connects computer.

transfer rate of 20Mbps. A dedicated internal register in FPGA for baud rate can be bound from computer or controlled in manual mode, which is controlled by dedicated internal clock module. Functional structure diagram of these modules is shown in Figure 4.

Figure 2 diagram of the the USB system work when connecting computer B. Handshake communication between FPGA and DSP is implemented to complete the assigned function of the command transfer in the system. Appropriate address decoding module is designed in FPGA. The DSP data and commands transmit to FPGA through the address bus whenever computer is connected or not connected and FPGA transmits package data to computer by address decoding. When the system records data, FPGA will decode and transmit the stored data DSP, which is stored in FLASH memory. To meet the design requirements, the system sends commands continuously with a fixed interval. Taking into account features that the system will take some time to read the data and FPGA is faster to process data than DSP, FPGA and DSP take ping-pong transmission mode to communicate. FPGA dsecodes and writes data from DSP to different RAMs. The size of RAM storage could be modified, and double pingpang transmission mode could be changed to muliti-ping-pang transmission mode by exchanging decoding method, which can bring an improvement of transmission quantity and transmission rate. FPGA receives data storage using multi-ram, that is the regionalization of the ram, as shown in Figure 3. This will ensure the speed and integrity of data, as well as the resource retrenchment at the same time. Figure 4 FPGA functional blocks diagram The system uses the Xc2V1000 produced by Xilinx company as FPGA chip[8]. This chip has a high-performance FPGA clock control circuit, 12 digital clock control modules has features of accurate phase compensation and highresolution phase shift. These functions of FPGA meet the needs designed with further in a further function and less waste of resources. IV. FUNCTION IMPLEMENTATION OF DSP MODULE

Besides FPGA works as part of the main control module of the system, DSP also plays an important role in implementation of the function. A. DSP works to test the communication among devices after the system is powered on, only after which the system starts normally and waits for commands to complete the appropriate functions. If self-test of the system is not successful, the system would not work normally. For the visual observation, the system includes indicator lights to monitor various functions through IO pins of FPGA and peripheral function circuits. If the system self-test is not successful, the light will not turn on. B. DSP completes the functions of reading and writing data into FLASH memory device. The module of reading and writing data of FLASH is controlled by DSP and packaged. When the system needs to read or record data, appropriate functions will be implemented with data transmission from FPGA to DSP controlling module by decoding. C. Command and data communication between FPGA and DSP is needed when system works. System work is the need to FPGA and DSP for . There are specialized modules in DSP to communicate with decoding module in FPGA, determine and receive decoding information from FPGA, and then perform the appropriate action. At the same time, commands and data needed are sent to FPGA through decoding module, in which

Figure 3 Schematic diagram of ping-pong transmission modes of communication C. The system uses the standard HDLC (High-level Data Link Control) communication protocol to communicate with external devices[6]. Frames are the basic unit of transmission in HDLC protocol, with the main transmission structure: first flag, terminal address, control, valid data, frame check sequence FCS, tail flag. HDLC protocol is implemented in the FPGA chip in the system, with the flow chart of functional implementation in Figure 4. When determining data is received, the system detects the flag of header and tail of each frame, converts the data string and stores data in RAM after CRC checking. In order to implement the system design and the connection and communication with the peripheral, we choose AMS2486 produced by Analog to complete differential level characteristics of RS-485[7]. This chip can theoretically reach a

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sending or receiving data will be implemented. D. Combined with features of high-performance capability of fixed-point and floating point in DSP and simple coding development, the system designs to finish the work of binding and comparison of the stored data and analysis and operation of receiving data in DSP. Compared with the FPGA, the DSP module makes the program more readable, the system has wider availability for changing, upgrading and application. E. In addition, DSP contains sampling circuit with AD, capturing the external signal levels. Received through the serial port, external data will be processed, operated and stored in Flash, or transmitted in FPGA. TMS320F2812 produced by TI company is chosen as DSP chip[9] according to the technical requirements for the system. Function implementation of DSP is shown in Figure 5.

Figure 6 System flow chart of work VI. TEST RESULTS The part controlled by FPGA is written in VHDL language in the system, the part by DSP in C language. In the actual test, FPGA is responsible for the functional part of the communication and controls the timing operation of the chip. We can logically analyze data communication transmission situation through third-party software Chipscope. Figure 5 DSP modules diagram The system uses FLASH chip K9F2G08U0A, a selection of storage devices manufactured by Samsung[11]. The system is equipped with two pieces of same FLASH chip. FLASH chip will be detected automatically when the system starts to work. When primary storage FLASH is detected to be damaged or unreadable, the system will automatically change the default storage space to the second chip in case of loss of data and waste of resources. V. REALIZATION OF SYSTEM FUNCTIONS The situation of testing data transmission of the USB chip controlled by FPGA is shown in Figure 7 when the system is connected with computer. The data and commands designed to send can be seen from the signal EP2_doutb in the figure. These data received will be displayed through the software on the computer. Figure 8 shows the test chart of HDLC communication protocol achieved in the FPGA, where TX_Reg is the register prepared to send data and SPI_Dat_Out_T the register for the serial data on the data line. After sending "7E", flag headerthe of HDLC protocol, the system will send data in the register. The data on the serial data line should be read inverted in the figure because data sent is designed for each byte of the starting low and then high.

The system identifies the working condition by checking whether the computer is connected. When connected with computer, the system can get the parameters from the computer, query data and save them as an EXCEL file easy to read and analyze. The system is equipped with self-test mode while connected with computer, under which functions such as data transmission and recording can be simulated; when no connection with the computer, the system will start the data transfer and record mode. In this mode, the system sends data bound in HDLC protocol and receives data under the agreement, finally stores data in FLASH under the control of FPGA and DSP. The flow of work of the system is shown in Figure 6.

Figure 7 CY7C68013 hardware test plans

Figure 8 HDLC protocol hardware test plans

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VII. CONCLUSION This system implements functions of communication and storage of data with a combination of FPGA and DSP. The whole system is based on a modular design, as such, it can easily be extended and upgraded. Taking into account the practicability, the system can be updated in real-time data communication, which is more versatile. The system designs many expansion interfaces, which is easy to expand functions with high practical value.

VIII. REFERENCES
[1] Jin Wei,Cheng Long,Chai Bo "Reliable Data Storage Technology on Data Recorder": Science Technology and Engineering 2011,pp.407409,pp.414 [2] Sun Yaojie, Zhao Zhongxiang "Design of multi-functions vehicle traveling data recorder based on GPS and GPRS": Electronic Design Engineering, 2010,pp.121-125 [3] Cypress. EZ-USB Technical Reference Manual [4] Zang Jinmei, Li Guo "The design of high-speed data transmission module based on CY7C68013": Microcomputer Information 2008,pp.110-112 [5] Cypress. CY7C68013 EZ-USB FX2 USB Microcontroller High-Speed USB Peripheral Controller Cypress Semiconductor Corporation 2000.11 [6] Chen Chen, Li Zhilai "Design of high-speed synchronous HDLC protocol controller based on FPGA", Electronic Design Engineering 2010 pp.175-178 [7] Analog Device. High Speed, Half-Duplex iCoupler Isolated RS-485 Transceiver. Analog Device. 2005 [8] XILINX. Virtex-II 1.5V Field-Programmable Gate Arrays.VC2V1000 [9] TMS320F2812 Digital Signal Processors Data Manual Texas Instruments 2007.7 [10] Principle and Application of DSP TMS320X281x Xu Kejun, Zhang Han: Beihang University Press 2006 [11] SAMSUNG ELECTRONICS. K9F2G08R0A FLASH MEMORY.

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