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Toward Intrinsic Graphene Surfaces: A Systematic Study on Thermal Annealing and Wet-Chemical Treatment of SiO2-Supported Graphene Devices
Zengguang Cheng, Qiaoyu Zhou, Chenxuan Wang, Qiang Li, Chen Wang,* and Ying Fang*
National Center for Nanoscience and Technology, 11 Beiyitiao Street, Zhongguancun, Beijing 100190, People's Republic of China
S b Supporting Information

ABSTRACT: By combining atomic force microscopy and transport measurements, we systematically investigated eects of thermal annealing on surface morphologies and electrical properties of single-layer graphene devices fabricated by electron beam lithography on silicon oxide (SiO2) substrates. Thermal treatment above 300 C in vacuum was required to eectively remove resist residues on graphene surfaces. However, annealing at high temperature was found to concomitantly bring graphene in close contact with SiO2 substrates and induce increased coupling between them, which leads to heavy hole doping and severe degradation of mobilities in graphene devices. To address this problem, a wet-chemical approach employing chloroform was developed in our study, which was shown to enable both intrinsic surfaces and enhanced electrical properties of graphene devices. Upon the recovery of intrinsic surfaces of graphene, the adsorption and assisted brillation of amyloid -peptide (A1-42) on graphene were electrically measured in real time. KEYWORDS: Graphene, electrical properties, thermal annealing, wet-chemical treatment, sensor

raphene, a distinct two-dimensional building block, has attracted enormous research interest due to its superb physical properties and future promise in nanoelectronics.1-6 Graphene is in general integrated into devices by lithography on standard SiO2 substrates, but exposure to resist polymers during fabrication processes inevitably contaminates hydrophobic graphene surfaces with resist residues which cannot be removed by standard solvents such as acetone or Remover PG.7-9 Former studies have shown that resist residues can act as external scattering centers and degrade transport properties in single-layer graphene whose atoms are all exposed directly to extrinsic impurities.8,10-12 In order to explore application potentials of graphene-based devices, facile and reliable methods for producing clean graphene surfaces are of central importance. Thermal annealing has been investigated as a common method to eliminate contamination and restore clean surfaces of graphene.7,8,13-16 Nevertheless, a wide range of annealing conditions have been reported along with diverse thermal eects on graphene devices, and a deep understanding of interaction between graphene and its local environment during processing is still lacking and highly desired. In this study, we carried out a systematic study of thermal eects on graphene devices. Although annealing above 300 C in vacuum can eliminate resist residues on graphene surfaces, it simultaneously brings graphene in close contact with corrugated SiO2 substrates and accordingly induces large perturbation to electrical properties of graphene devices. On the other hand, wet-chemical treatment with chloroform was found to be eective in both restoring intrinsic surfaces and improving electrical performances of graphene devices.
r 2011 American Chemical Society

Graphene akes were deposited through mechanical exfoliation of natural graphite on silicon substrate coated with 285 nm of SiO2.2,17 The height of freshly cleaved single-layer graphene is typically 0.6-0.8 nm on SiO2 (Figure S1, Supporting Information). E-beam lithography on poly(methyl methacrylate) (PMMA) resist and subsequent thermal evaporation were introduced to pattern 5 nm Cr/100 nm Au electrodes of graphene eld eect transistors (FETs). After lift-o, graphene devices were rst ultrasonicated in acetone for 10 min before characterization. Figure 1a shows the topographic imaging by tapping mode atomic force microscopy (AFM) on a typical single-layer graphene device. The height of the graphene sheet increased to 1.5 nm after fabrication due to a thin resist lm covering the surface of the graphene device.8 The root-mean-square (rms) surface roughness of the graphene sheet was measured to be 0.54 nm whereas the SiO2 substrate gave a much smoother surface with a rms roughness of 0.17 nm, which shows that the hydrophobic surface of graphene is more susceptible to resist contamination than SiO2 and standard acetone cleaning cannot completely remove resist residues due to their strong van der Waals interaction with graphene. We believe that the uncontrollable surface covering of resist from fabrication is partly responsible for the large variation of reported properties in graphene devices.8,12,13
Received: November 12, 2010 Revised: January 3, 2011 Published: January 10, 2011
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Figure 1. Thermal annealing eects on surface morphologes of graphene. (a) AFM topographic image of a graphene device before any thermal treatment. The height of the graphene sheet is 1.5 nm as shown in the height prole along the dashed blue line. The rms surface roughness of 0.54 nm was acquired on a 1 1 m2 scan window highlighted by the red box. The scale bar is 1 m. (b-d) AFM images of the same graphene device after thermal annealing in vacuum at 200 C (b), 300 C (c), and 400 C (d), respectively. The height (h) and rms surface roughness (Ra) of the graphene sheet were measured to be: h = 1.1 nm and Ra = 0.42 nm (200 C), h = 0.40 nm and Ra = 0.20 nm (300 C), Ra = 0.15 nm (400 C), respectively. Scale bars represent 1 m.

To examine eects of thermal treatment, graphene devices were sequentially annealed from 100 to 400 C in vacuum with each anneal being 3 h in duration. As shown in the AFM topographic image of Figure 1b, resist contamination cannot be eectively removed at 200 C although the height and the rms surface roughness of the graphene sheet decreased to 1.1 and 0.42 nm, respectively, due to the partial desorption of resist residues by annealing. After thermal treatment at 300 C for 3 h, most of the resist residues were removed from the graphene surface, which thus gave a much smoother graphene surface with a rms roughness of 0.20 nm (Figure 1c). Notably, the height of the graphene sheet after annealing at 300 C was measured to be only 0.4 nm, even lower than freshly transferred single-layer graphene before any fabrication processing (Figure S1, Supporting Information). We further increased the annealing temperature to 400 C, which resulted in complete removal of resist contamination from the graphene surface and a further reduced rms roughness of 0.15 nm (Figure 1d and Figure S2, Supporting Information). Surprisingly, the graphene sheet is now hardly discernible from the SiO2 substrate in the AFM topographic imaging, indicating that either the height of the graphene sheet is below the detection limit of our AFM equipment or their surface roughness obscures the dierence between graphene and the SiO2 substrate. We note that similar results with the height of graphene sheets below resolution were reproduced on other graphene devices after annealing at 400 C in vacuum (Figure S3, Supporting Information). The interlayer distance in bulk graphite is 0.3 nm, and the larger height of 0.6-0.8 nm measured from freshly prepared single-layer graphene has been attributed to a dead space between graphene and SiO2 substrates.2 Thus, our results show that annealing above 300 C in vacuum compresses the dead space and brings graphene to close contact with SiO2 substrates. The eects of thermal treatment on electrical properties of the same graphene device are summarized in Figure 2. The two-probe mobilities of the as-made graphene transistor gated through SiO2 were estimated based on the capacitance model,18 which resulted in
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Figure 2. Thermal annealing eects on electrical properties of graphene. (a) Annealing temperature dependence of conductance vs back gate voltage (Vg) characteristics. The source-drain voltage was biased at 0.03 V in dc mode and measurements were taken under ambient conditions right after annealing. (b) Calculated two-probe mobilities of the graphene device as a function of the annealing temperature. After annealing at 400 C, the Dirac point of the graphene device was above 65 V and out of the safe sweep range of the gate voltage applied through 285 nm of SiO2.

2000 and 1600 cm2/(V s) for holes and electrons, respectively. The Dirac point, the point of minimum conductivity, of the device settles at a back gate voltage of 48 V (Figure 2a), which is due to doping eects from both the SiO2 substrate and the PMMA surface layer. Upon annealing at medium temperatures of 100 and 200 C, the Dirac point of the graphene device shifts toward 0 V due to partly evaporated absorbents (PMMA residues and trapped absorbents by the PMMA) from the graphene surface. Further, the mobilities for both hole and electron carriers increased with annealing (Figure 2b), indicating improved electrical properties by reduced surface contamination of the graphene device.11 After annealing at 300 C, most resist residues on the graphene surface were removed as shown in Figure 1c; however, the mobilities of the graphene device started to degrade and its Dirac point shifted positively again. Heavy hole doping and seriously degraded carrier mobilities of graphene devices were observed after thermal treatment at 400 C (Figure 2 and Figure S3, Supporting Information).13,14 Thus the optimal electrical performance of graphene devices does not concur to the situation with the cleanest graphene surfaces by thermal annealing. To illustrate the degraded electrical performance in graphene devices after thermal treatment, we then carried out Raman spectroscopy to probe structural and doping characteristics of graphene. Figure 3 highlights Raman results from a graphene device before thermal treatment and after annealing at 400 C. First, the absence of any defect-related D-band at 1350 cm-1
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Figure 4. Wet-chemical treatment of resist-contaminated graphene. Conductance vs back gate voltage characteristics of a typical graphene device before (black) and after chloroform cleaning (red). The dc bias voltage was set at 0.03 V, and the measurements were carried out under ambient conditions. Inset: AFM topographic image of the graphene device after cleaning. The rms surface roughness of 0.16 nm was acquired in the area highlighted by the red box. Scale bar represents 1 m.

Figure 3. Raman characterization of graphene before and after annealing. (a) Raman spectra of a typical graphene device without any thermal treatment (black curve) and after annealing at 400 C for 3 h in vacuum (red curve). (b, c) Zoom-ins of Raman G band (b) and 2D band (c), respectively.

shows that there is no damage to the sp2 hybridized carbon structure of graphene by thermal treatment in vacuum even up to 500 C (Figure S4, Supporting Information). Second, G and 2D bands of the graphene sheet drastically blue-shifted 12 and 10 cm-1, respectively, after thermal treatment at 400 C. Blue-shifted Raman bands can be caused by either compressive strain or hole-doping in graphene.19-21 The thermal expansion induced strain to graphene in our temperature range is estimated to be 0.3%,22 which cannot account for the large Raman band shifts here. Further, former studies have shown that straininduced shift of the G band would be 2 times smaller than that of the 2D band, which is inconsistent with our results.20 We thus attribute the blue-shifted G and 2D bands in Figure 3 to a high level of hole doping in the graphene device and the corresponding hole concentration in graphene is estimated to be 1 1013/cm2 after thermal annealing at 400 C.19 From our correlated AFM, transport, and Raman results, we can conclude that (1) standard solvents such as acetone cannot eliminate PMMA resist residues from graphene surfaces, (2) no defects are introduced to activate the D band of graphene by thermal treatment in vacuum up to 500 C, (3) annealing above 300 C is required to eectively remove resist residues on graphene surfaces, and (4) annealing above 300 C in vacuum induces increased coupling between graphene and corrugated SiO2 substrates, which leads to both heavy hole doping and
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severe degradation of electrical properties in graphene devices. We note that the mechanism of heavy hole doping in annealed devices is not clear at this stage. Increased charge transfer with underlying SiO2 substrates might contribute to the hole doping in graphene,23 although former studies also indicate that high temperature annealing can assist the adsorption of H2O and O2 molecules on graphene and result in hole doping.15 To address problems associated with thermal treatment, we further investigated wet-chemical approaches based on strong solvents for PMMA to eectively clean graphene devices without compromising their electrical properties. Chloroform was chosen to treat graphene devices because, as a common solvent, chloroform has high dissolvability for PMMA and is miscible with traditional lithography solvents such as acetone and 2-propanol. AFM topographic imaging of a typical graphene device after chloroform cleaning and subsequent 2-propanol rinsing is presented as the inset in Figure 4, which shows that the surface of the graphene sheet is now clear of resist residues and its rms roughness accordingly reduces to 0.16 nm. The height of the exposed graphene sheet was measured to be 0.7 nm on SiO2 substrate, comparable to freshly cleaved single layers. Electrical measurements of the same graphene device before and after chloroform cleaning are also summarized in Figure 4. The black curve shows the conductance of the device, with only acetone cleaning, plotted against the applied back gate voltage, which gives a Dirac point at 38 V and two-probe mobilities of 1700 and 1600 cm2/(V s) for holes and electrons, respectively. After chloroform treatment, the Dirac point of the device shifted to close to 0 V as illustrated by the red curve in Figure 4, indicating substantially reduced hole doping in the graphene device. Importantly, the two-probe mobilities of the graphene device increased greatly to 3100 and 2700 cm2/(V s) for hole and electron carriers, respectively. Thus, in contrast to thermal annealing, our facile wet-chemical treatment with chloroform can render both intrinsic surfaces and improved electrical properties of graphene devices (Figure S6, Supporting Information). Self-assemblies of A peptide are of central relevance to the pathology of Alzheimers disease, and their brillation has been shown to be assisted by interaction with freshly cleaved surfaces of highly oriented pyrolytic graphite (HOPG).24,25 Graphene shares identical honeycomb crystal lattice and similar surface
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ASSOCIATED CONTENT
S b

Supporting Information. Description of methods and Supplementary Figures S1-S7. This material is available free of charge via the Internet at http://pubs.acs.org.

AUTHOR INFORMATION
Corresponding Author

*E-mail: wangch@nanoctr.cn, fangy@nanoctr.cn.

ACKNOWLEDGMENT C.W. acknowledges support of this work by the Foundation of CAS (KJCX2.YW.M15). Y.F. acknowledges support by the 973 Fund (2011CB932700) and the National Natural Science Foundation of China (20973045).
Figure 5. Peptide adsorption on clean graphene device. After chloroform cleaning, a poly(dimethylsiloxane) (PDMS) chamber was incorporated on a chip with a graphene device to conne solutions and a nonleak Ag/AgCl reference electrode was included as the electrolyte gate. Then H2O, H2O, and peptide solutions were sequentially delivered to the surface of graphene. The conductance of the graphene device was monitored in real time as shown by the black curve, and arrows mark the points when solutions were changed. Inset, AFM topographic image of the graphene device after peptide adsorption.

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properties with HOPG, thus A peptides are expected to selfassemble into nanobers on graphene with intrinsic surfaces.26 To demonstrate the capability of our wet-chemical approach, graphene FETs with recovered clean surfaces were applied to interface directly with A peptide molecules,27,28 and real-time electrical response to peptides from a typical graphene device is summarized in Figure 5. Upon switching to 2 M A1-42 solution, the conductance of the graphene device started to decrease due to the capture of peptide molecules on the graphene surface, and the positively shifted Dirac point of the device shows that A1-42 molecules act as hole-dopants for graphene (Figure S5, Supporting Information). A total conductance change as large as 40% was achieved when the interaction between A1-42 and the intrinsic surface of graphene stabilized after 100 min,29 and we note that the adsorption of A1-42 on graphene surfaces is irreversible. AFM imaging after solution measurements conrms that the brillation of A1-42 was specic on graphene surfaces and no bers were observed on SiO2 substrates (Figure 5 and Figure S7, Supporting Information). In summary, we systematically investigated eects of thermal annealing and wet-chemical cleaning on surface morphologies and electric properties of single-layer graphene devices supported by SiO2 substrates. Although annealing at high temperature in vacuum can eectively remove resist residues on graphene, it simultaneously brings graphene to close contact with corrugated SiO2 substrates and leads to severe degradation of electrical performance in graphene devices. On the other hand, chloroform was shown to be an eective solvent to dissolve resist residues on graphene and enable enhanced mobilities of graphene devices. This advance further allowed us to measure in real time the electrical response of graphene devices to the adsorption and specic brillation of A-peptide onto clean graphene surfaces, which opens up new opportunities for reliable interfaces between graphene nanoelectronics and supramolecular self-assemblies.26

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