DIGITAL SYSTEMS

Random Access Memory (RAM) 08.12.11 A.J. Han Vinck

Outline of the chapter

- We first introduce the concept of tri-state logic. purpose: - isolation of parts of the system - multiplexer functionality

Then we discuss the structure of a Random-Access Memory (RAM) address data-out

data-in write/read
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How to connect without too many wires?

Bus structure

Fully connected: n(n-1)/2 connections

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An important building block: Tri state logic gates

In bus and memory systems, tri state logic is very useful
H L

H enable

H enable

L disable

States are: High ( +5 V 1), Low ( 0 V 0 ) and Disconnected ( High impedance := Hi-Z )

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An implementation & function table

H
Enable EN

Q1 OUT

EN A C D Q2 Q1 OUT L L H H L H L H H L off off Hi-Z H L off off Hi-Z H H on off L L L off on H

Q2 L
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inverter
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Sharing a 3-state party line (bus)

1-bit party line A
high impedance out (output disconnected)

B C decoder data
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in oe
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only one of the devices may use the common bus

BUS: Paths DATA bus: for digital signals from one place to another place carries data ADDRESS bus: carries the location of data or device CONTROL bus : carries the control signals

ADDRESS bus DATA bus CONTROL bus

ROM

RAM

CPU

Input/output

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Bi-directional bus used in memories(principle)

device

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Tri-State Logic and Buses

Memory connected to bus

Memory in

Memory out

bus
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Properties of the 3-state buffer

Acts as if it is not there (high impedance Hi-Z) Allows multiple sources to share a single party line with a single active user BUS Go into Hi-Z state faster than come out of to avoid fighting = connecting L and H outputs

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Random access memory

We discuss the structure of a Random-Access Memory (RAM) A memory cell structure based on a latch

The larger RAM. - some specific constellations: - how to make a larger memory from smaller ones

At the end we show the physical structure of SRAM and DRAM

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Random Access Memory: read and write to any location specified by the address
We refer to this as a 2k x n memory. There are k address lines, which can specify one of 2k addresses. Each address contains an n-bit word. 2k x n memory
k n

ADRS DATA CS WR

OUT

For example, a 224 x 16 RAM contains 224 = 16M words, each 16 bits long. The RAM would need 24 address lines. The total storage capacity is 224 x 16 = 228 bits.
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Reading from the RAM

To

read from this RAM, the controlling circuit must:

Enable the chip by ensuring CS = 1. Select the read operation, by setting WR = 0. Send the desired address to the ADRS input. The contents of that address appear on OUT after a little while.

Notice that the DATA input is unused for read operations. 2k x n memory
k n

1 0

ADRS DATA CS WR

OUT

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Writing to the RAM

To write to this RAM, you need to: Enable the chip by setting CS = 1. Select the write operation, by setting WR = 1. Send the desired address to the ADRS input. Send the word to store to the DATA input. The output OUT is not needed for memory write operations. 2k x n memory
k n

1 1

ADRS DATA CS WR

OUT

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Summary

2k x n memory
k n

CS

WR x 0 1

Memory operation None Read selected word Write selected word

ADRS DATA CS WR

OUT

0 1 1

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Size matters!
Memory sizes are usually specified in numbers of bytes (8 bits). The 228-bit memory translates into: 228 bits / 8 bits per byte = 225 bytes With the abbreviations below, this is equivalent to 32 megabytes.
Prefix Base 2 Kilo 210 = 1,024 Mega 220 = 1,048,576 Giga 230 = 1,073,741,824 Base 10 103 = 1,000 106 = 1,000,000 109 = 1,000,000,000

K M G

RAM size is measured in base 2 units,

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A basic cell structure with a latch

We can use one latch to store each bit. A one-bit RAM cell is shown here.

Writing to the RAM cell: Make CS = 1 and WR = 1, the latch control input will be 1. Then make WR = 0. Reading from the RAM cell and maintaining the current contents: The current latch contents will appear on OUT when CS = 1 .
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a 4 x 1 RAM
Since there are four words, ADRS is two bits. Each word is only one bit, so DATA and OUT are one bit each. Word selection is done with a decoder attached to the CS inputs of the RAM cells. Only one cell can be read or written at a time. Notice that the outputs are connected together with a single line!
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EN = 0 => all Q outputs are 0

A 4 x 4 RAM
DATA and OUT are now each four bits long, so you can read and write fourbit words.

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Bigger RAMs from smaller RAMs

We can use small RAMs as building blocks for making larger memories, by following the same principles as in the previous examples. As an example, suppose we have some 64K x 8 RAMs to start with: 64K = 26 x 210 = 216, so there are 16 address lines. There are 8 data lines.

16 8

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Making a larger memory

We can put four 64K x 8 chips together to make a 256K x 8 memory. For 256K words, we need 18 address lines. The two most significant address lines go to the decoder, which selects one of the four 64K x 8 RAM chips. The other 16 address lines are shared by the 64K x 8 chips. The 64K x 8 chips also share WR and DATA inputs. This assumes the 64K x 8 chips have three-state outputs.
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8 16

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Analyzing the 256K x 8 RAM

There are 256K words of memory, spread out among the four smaller 64K x 8 RAM chips. When the two most significant bits of the address are 00, the bottom RAM chip is selected. It holds data for the first 64K addresses. The next chip up is enabled when the address starts with 01. It holds data for the second 64K addresses. The third chip up holds data for the next 64K addresses. The final chip contains the data of the final 64K addresses.
8 8 16

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Address ranges
8 16

11 1111 1111 1111 1111 (0x3ffff) to 11 0000 0000 0000 0000 (0x30000) 10 1111 1111 1111 1111 (0x2ffff) to 10 0000 0000 0000 0000 (0x20000) 01 1111 1111 1111 1111 (0x1ffff) to 01 0000 0000 0000 0000 (0x10000) 00 1111 1111 1111 1111 (0x0ffff) to 00 0000 0000 0000 0000 (0x00000)
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Making a wider memory

You can also combine smaller chips to make wider memories, with the same number of addresses but more bits per word. Here is a 64K x 16 RAM, created from two 64K x 8 chips. The left chip contains the most significant 8 bits of the data. The right chip contains the lower 8 bits of the data.

8 16

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Connected to bus
19 address bits = 512 x 1024 addresses A.J. Han Vinck
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Truth table for the control circuit

Not selected

Data in Data out

to tri-state logic

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Physical structure of Static RAM

Word Line

6 MOSFETS low density higher cost/bit, but fast

!Bit

Bit

Read: Make word line H + sense value on bit lines Write: Make word line H + put values to Bit and !Bit flip-flop stays in stable state when word line L

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Layout of a single SRAM cell.

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Physical structure of Dynamic RAM

W o r d L in e

Word line HIGH enables the bitline to write in or read from the capacitor.

B it L i n e

Refresh cycles are needed for the whole memory to restore the content! (do dummy read) Small cell high density lower speed (refresh) more difficult to produce

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Summary
A RAM looks like a bunch of registers connected together, allowing users to select a particular address to read or write.

Much of the hardware in memory chips supports this selection process: Chip select inputs Decoders Tri-state buffers
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memory access, size, cost, speed

speed cost/b

size
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