1

Control and Implementation of a New Modular Matrix Converter

S. Angkititrakul and R. W. Erickson
Colorado Power Electronics Center University of Colorado, Boulder Boulder, CO 80309-0425, USA angkitis@colorado.edu

I. INTRODUCTION Multilevel conversion has attracted signicant attention, as a way to construct a relatively high-power converter using many relatively-small power-semiconductor devices [13]. This approach has the advantages of reduced switching loss and reduced harmonic content of output AC waveforms. The peak voltages applied to the semiconductor devices are clamped to capacitors whose DC voltages can be controlled via feedback, and total switching loss is reduced. When the input and output voltage magnitudes differ signicantly, it is also possible to reduce the conduction losses using multilevel techniques; this property can improve the energy capture of variable-speed wind power systems. Although multilevel conversion requires a larger packaging and parts count, the total silicon area can in principle be reduced because of the reduced device voltage ratings. Thus, higher performance is attained at the expense of increased control and complexity. As the number of levels is increased, the bus bar structures of multilevel DC-link converter systems can become quite complex and difcult to fabricate. Several authors have suggested a solution to this problem through the use of voltageclamped switch cells [4, 5], in which the voltages applied to the semiconductor devices are locally clamped to voltage sources. The difculty with this approach is that the voltage sources of each switch cell must generate the average power supplied by the inverter, and hence oating sources of DC power are required. To address these issues, a new family of modular matrix converters was proposed in [6]. Voltage-clamped switch cells
This work was supported in part by the DOE National Renewable Energy Laboratory under contract no. XCX-9-29204-01.

iA

iB

iC Three-phase ac system 2
+

+ +

Fig. 1: New modular matrix converter.

Q1

Q3

Fig. 2: H-bridge switch cell with capacitor. The new modular converter is fundamentally different from the conventional matrix converter [7, 8], as well as from the multilevel DC-link converter, in several respects. It is capable of both increasing and decreasing the voltage magnitude and frequency, while operating with arbitrary power factors. The peak semiconductor device voltages are locally clamped to a DC capacitor voltage, whose magnitude can be regulated. The semiconductor devices are effectively utilized. Multilevel switching can be used to synthesize the voltage waveforms

Abstract Implementation of a new modular AC-AC matrix converter and its control system are described. The converter consists of a matrix connection of capacitor-clamped H-bridge switch cells. The AC output of each switch cell can assume three voltage levels during conduction. Input and output three-phase AC waveforms are synthesized from pulse-width modulation of the DC clamp capacitor voltages. The space-vector modulation approach can be adapted to control this converter. A control algorithm is described that can be reduced to an equivalent DC-link converter. This controller is implemented using programmable logic devices and a ashmemory look-up table. Operational waveforms are presented.

are connected in a matrix conguration as illustrated in Fig. 1. Each switch cell consists of an H-bridge with a DC capacitor whose voltage is controllable. The bus bar structures of this modular approach are relatively easy to construct. The use of a matrix conguration eliminates the need for DC voltage sources that supply average power, and hence the voltage sources are replaced by simple DC capacitors.

n Three-phase ac system 1

a b c

ia ib ic

D1

D2

Q2

D3

D4

Q4

TABLE I: Comparison of conventional matrix converter with new modular matrix converter.
Voltage conversion ratio Vout /Vin Switch commutation Bus bar structure Multilevel operation Filter elements Conventional matrix converter Buck: Vout 0.866Vin Coordination of 4quadrant switches Complex No AC capacitors and inductors Proposed new modular matrix converter Buck-Boost: 0 Vout < Simple transistor plus freewheeling diode Modular and simple Possible Inductors

TABLE II: Nineteen combinations of line-to-line voltage, for the basic converter conguration.
Three-phase variables Vab Vbc Vca Vcap 0 Vcap Vcap 0 Vcap 2Vcap Vcap Vcap 2Vcap Vcap Vcap 2Vcap 0 2Vcap 2Vcap 0 2Vcap 0 0 Vcap Vcap 0 Vcap Vcap Vcap Vcap 2Vcap Vcap Vcap 2Vcap 0 2Vcap 2Vcap 0 2Vcap 2Vcap 0 Vcap Vcap 0 Vcap Vcap 0 Vcap 2Vcap Vcap Vcap 2Vcap Vcap 2Vcap 2Vcap 0 2Vcap 2Vcap 0 0 D-Q variables Vd Vcap 0 Vcap Vcap 0 Vcap 2Vcap Vcap Vcap 2Vcap Vcap Vcap 2Vcap 0 2Vcap 2Vcap 0 2Vcap 0 Vq 3 3 Vcap 2 3 3 Vcap 3 3 Vcap 33 Vcap
2 3 3 Vcap 33 Vcap

at both the input and output ports of the converter; switch cells can be connected in series in each branch of the matrix to increase the voltage rating of the converter. Switch commutation is simpler than in the conventional matrix converter. The new modular matrix converter and the conventional matrix converter are compared in Table I. The converter is capable of increasing the number of level of operation by connecting more than one switch cell in series. For example, when two switch cells are series-connected in each branch as in Fig. 3. The converter can operate with threeand four-level switching.
n
+ + +

2 3 3 Vcap 4 3 3 Vcap 2 3 3 Vcap 2 3 3 Vcap 4 3 3 Vcap 2 3 3 Vcap

0 3Vcap 3Vcap 0 3Vcap 3Vcap

Three-phase ac system 1

iA A

iB B

iC C a b c ia ib N Three-phase ac system 2
+

proach can be adapted for control of the proposed new modular matrix converters. For the basic conguration of Fig. 1, the instantaneous line-to-line voltages +2V cap , +Vcap , 0, Vcap or 2Vcap can be produced, where V cap is the DC capacitor voltage of the switch cells. This leads to nineteen combinations of valid balanced three-phase line-to-line voltages, as shown in Table II. The line-to-line voltages are transformed into d-q variables by the following equation.
vd (t) vq (t) 2 = 3 cos(0) sin(0) cos(120 ) sin(120 ) cos(240 ) sin(240 ) vx (t) vy (t) (1) vz (t)

q-axis

ic
+
(0,4Vcap/3) (-Vcap, 3Vcap) (-2Vcap, 2Vcap/3)
(0,2Vcap/3)

Fig. 3: Converter containing two switch cells in each branch of the switch matrix. This paper documents a laboratory prototype converter, along with measured waveforms and data. A control algorithm is described that is based on an equivalent DC-link converter. Pulse-width modulated line-to-line voltages are synthesized by switching the DC capacitor voltages of the switch cells. This algorithm is implemented using programmable logic devices and a ash-memory lookup table. The prototype switches at 50 kHz, using hard-switched 600 V IGBTs. The switch modules are assembled on printed circuit boards. II. PROPOSED CONTROL STRATEGY A. Space Vector Modulation The space vector modulation approach is a well-known technique for control of three-phase converters [7]. This ap-

(Vcap,3Vcap) (2Vcap, 2Vcap/3)

(-Vcap, Vcap/3) (-2Vcap, 0) (-Vcap, -Vcap/3)

(Vcap, Vcap/3) (2Vcap, 0) d-axis (Vcap, -Vcap/3)

(-2Vcap, -2Vcap/3)

(0,-2Vcap/3)

(2Vcap, -2Vcap/3) (Vcap, -3Vcap)

(-Vcap, -3Vcap)

(0,-4Vcap/3)

Fig. 4: Nineteen-space vector generated by proposed converter

Figure 4 shows the corresponding space vectors of all nineteen combinations in the d-q plane. These space vectors have four different magnitudes: 0, 2V cap / 3, 2Vcap and 4Vcap / 3. The inner ring of six low-magnitude vectors, the rst group in Table II, and the null space vector can be employed for twolevel switching. The outer ring of medium and high magnitude vectors can be used for three-level switching; however, in the basic converter conguration three-level switching is restricted to voltage conversion ratios less than 57% or greater than 173%. This occurs because generation of a medium- or highmagnitude space vector on one side of the converter forces the other side to the null space vector [6]. Additional space vectors are possible when multiple modules are placed in each branch of the matrix.
Vk dkVk V0 dlVl Vl f vref 60
o

TS
Input side Output side

d0_in

max(dk_in,dl_in)

min(dk_in,dl_in)

d0_out

max(dm_out,dn_out)

min(dm_out,dn_out)

Subinterval

Fig. 6: The ordering pattern of input and output space vector for two-level operation.

Fig. 5: Space vector modulation. The reference space vector can be expressed as a linear combination of three adjacent space vectors, two low magnitude space vectors and the null space vector, as illustrated in Fig. 5. It can also be described by the following equation:
vref (t) = dk Vk + dl Vl + d0 V0 (2)

where dk , dl and d0 are duty cycles of V k , Vl and V0 , respectively, and

dk + dl + d0 = 1 (3)

By solving Eq. (2) and (3), we obtain

Vref 2 Vref sin sin = Vk sin60 3 Vk Vref = sin = M sin Vcap Vref 2 Vref dl = sin(60 ) sin(60 ) = Vl sin 60 3 Vl Vref sin(60 ) = M sin(60 ) = Vcap d0 = 1 dk dl = 1 M sin(60 + ) Vref M = Vcap dk =

(4)

scheme, the pattern of Fig. 6 has been used. Consider the case where the input reference space vector lies between space vectors Vk in and Vl in , and the output reference space vector lies between space vectors V m out and Vn out . The space vector modulation technique involves modulation among input-side space vectors V k in , Vl in and V0 in , with duty cycles of dk in , dl in and d0 in respectively. Likewise, the output-side involves modulation among output space vectors Vm out , Vn out and V0 out with duty cycles of d m out , dn out and d0 out respectively. In each switching period, for both the input- and output-sides, the pattern starts with the null space vector then follows with the active space vector that has maximum duty cycle, and then ends with the active space vector that has less duty cycle. This space vector modulation control requires that the switching period be divided into ve subintervals. For each combination of input space vector and output space vector, different set of capacitors can be employed. With the ordering pattern of input and output space vector, as in Fig. 6, there exists one capacitor that can be employed to synthesize terminal voltages throughout the switching period. Consider the example in which the input reference space vector lies between space vectors V 3 in and V4 in and the output reference space vector lies between space vectors V1 out and V6 out , as shown in Fig. 7. The pattern of input and output space vectors in one switching period is shown in Fig. 8, and the sets of capacitors that can be employed for each subinterval are also shown. Notice that capacitor CAa , from the switch cell that is connected between input phase A and output phase a, can be employed throughout the switching period. Figure 9(a) summarizes how the converter
Input-Side Space Vector Diagram q-axis V2 (-Vcap, Vcap/3) V3 fin
Input reference voltage space vector

Output-Side Space Vector Diagram q-axis V2

B. Single-Capacitor Control Scheme When the converter synthesizes the input- and output-side voltages, there exist additional degrees of freedom that can be used to control the DC capacitor voltages. when the converter operates with two-level switching, only one capacitor is needed in each switching period. This approach is optimized in sense of minimizing circulating current among capacitors. An extra degree of freedom that can be used to control the capacitor voltage is the pattern of space vectors in each modulation period. To achieve the single-capacitor control

V1 V0 d-axis V6 V5

V3

(Vcap, Vcap/3) V1
Output reference voltage space vector

V0 V4 V5

fout

d-axis

V4 (-Vcap, -Vcap/3)

V6 (Vcap, -Vcap/3)

Fig. 7: Control example, at an instant when the input and output side reference space vectors lie as shown.

Single capacitor control

INPUT SIDE
Phase A
VAB = 0V VCA = 0V

Equivalent DC link
00
A B C

Line-to-line voltages
01 41 46 36

OUTPUT SIDE
Phase a
Vab = 0V

Phase B
VBC = 0V

Phase b
Vbc = 0V

Vca = 0V

+ -

a b c

Ts vAB 0 Vcap t

Phase C Phase A
VAB = 0V VCA = 0V

Phase c -Vcap+ Branch Aa Phase a

Vab = Vcap

Phase B
VBC = 0V

Phase b
Vbc = 0V

Vca = -Vcap

A B C

+ -

a b c

vBC

+ Vcap

Phase C Phase A
VAB = -Vcap VCA = Vcap Phase B VBC = 0V

Phase c -Vcap+ Phase a

Vab = Vcap

Phase b
Vbc = 0V

Vca = -Vcap

A B C

+ -

vCA
a b c

+ Vcap

Phase C Phase A
VAB = -Vcap VCA = Vcap Phase B VBC = 0V

Phase c -Vcap+ Phase a

Vab = Vcap

vab
Vca = 0V

+ Vcap

Phase b
Vbc = -Vcap

A B C

+ -

a b c

vbc

Phase C Phase A
VAB = -Vcap VCA = 0V Phase B VBC = Vcap

Phase c -Vcap+ Phase a

Vab = Vcap

0 Vcap

Phase b
Vbc = -Vcap

Vca = 0V

A B C

+ -

a b c

vca

0 Vcap

Phase C

Phase c

(a)

(b)

(c)

Fig. 9: Single capacitor control technique (a) switch combinations of each subinterval, (b) equivalent DC-link circuit, (c) the resulting input and output waveforms.
TS
Input side Output side Input V0_in d0Ts Output V0_out d0Ts
1 2

Input V4_in d4Ts Output V1_out d1Ts

3 4

Input V3_in d3Ts Output V6_out d6Ts

5

V2

C_c

CBc V3 C_b CAb CCc

CAc V1 CCa CAa CBa C_a

Subinterval Possible capacitors that can be used

CAa CBa CCa

CAa CBb CBc CCb CCc

CAa CAc CBb CCb

CAa CAc CBb CCa CCc

CCb CBb

Fig. 8: Ordering pattern of input and output space vectors with switch cell capacitors that can be used in each subinterval.
V4 C_a

CBa CCa

CAa

CBb CCc CAc CBc CCb

CAb V6 C_b

is congured for each subinterval. Figure 9(b) illustrates the connections in an equivalent DC link converter that generates identical space vectors. The instantaneous input and output line-to-line voltages for both converters are illustrated in Fig. 9(c). Selection of the switch-cell capacitor to be employed during a given switching period is based on the directions of the reference space vectors, as well as relative values of the duty cycles for the input- and output-side null space vectors. Figure 10 summaries the result, for the case d 0 out < d0 in . A different switch-cell capacitor is selected for every 60 of the output-side line cycle, and for every 120 of the input-side line cycle. The situation is reversed when d 0 out > d0 in . It should be noted that, when the reference vector coincides with

V5

C_c

Fig. 10: Summary of switch-cell capacitor choice, for the case of d0 out < d0 in . The large (outer) space vector diagram represents the output side, with 60 segments. When the 60 segment is shaded, then the positive side of Vcap is applied to the respective output terminal. The smaller superimposed space vector diagrams represent the input side, with 120 segments. The case d0 out > d0 in is symmetrical, with the input and output sides interchanged.

one of the converter space vectors V 1 , V2 ,..., V6 , then the corresponding line-to-neutral voltage v an , vcn , vbn , van , vcn , vbn , attain their peak values. Thus the single-capacitor control scheme employs the capacitor from the switch cell that is connected between the input phase and output phase that have the largest opposite polarity line-to-neutral voltages. For example, suppose that d 0 out is less than d0 in . If vref out (t) lies within 30 of the converter space vector V3 , and hence the output-side line-to-neutral voltage v bn (t) is within 30 of its peak positive value for the output AC line cycle. Therefore we choose one of the three capacitors connected to the output phase b: either C Ab , CBb or CCb . Next, the input side is examined. To narrow the choice to a single capacitor, we select the phase having the largest negative value, of opposite polarity to output side. Three of the six converter space vectors lead to a negative-polarity input space vector: V2 , V4 and V6 correspond to negative v CN , vAN and vBN , respectively. The converter space vector that lies closest to (within 60 ) of the input reference space vector is selected. For instance, if the input-side reference space vector lies between converter space vectors V 4 and V5 , then it is closest to converter negative space vector V 4 , and so input phase A exhibits the most negative line-to-neutral voltage. Therefore, capacitor C Ab is employed. C. Eight-Capacitor Control Scheme For comparison, the eight-capacitor control scheme is also described. In this control scheme, all nine branches conduct currents at any given time and capacitors are allowed to be
Phase A
VAB = 0V VCA = 0V

connected in parallel during each subinterval of Fig. 6. The redundant switch combinations are employed in such a way that the number of conducting capacitors is maximized. In one switching period, the converter employs eight of nine capacitors (three, four or ve capacitors are employed in each subinterval). This modulation scheme is related to the single-capacitor control scheme of Figs. 8 and 9 in that the subintervals, space vectors, and instantaneous line-to-line voltage waveforms, are identical. The voltages across the nonconducting branches of Fig. 9(a) are determined; those branches blocking zero volts are switched to the shorting state, while those branches that block voltage V cap are turned on with their capacitors connected with the correct polarity. The switching pattern of Fig. 11 is obtained. Close examination of Fig. 11 reveals that the capacitor of branch Ab is never employed. With this modulation approach, exactly eight of the nine capacitors participates during each complete switching period. To the extent that the capacitor voltages remain balanced, this scheme can improve efciency by distributing the currents over all nine branches. It also has the advantage that the effective capacitance is increased, and hence capacitor voltage ripple is reduced, and also that the capacitor voltage control is reduced to a single control loop. The disadvantage is that high peak currents can occur if the capacitor voltages are unbalanced. Efcient operation of this scheme requires that the mechanisms that drive capacitor voltage imbalances (primarily from the energy stored in stray inductances of the interconnections between switch cells) be minimized. III. IMPLEMENTATION

Phase a
Vab = 0V

Phase B
VBC = 0V

Phase b
Vbc = 0V

Vca = 0V

Phase C Phase A
VAB = 0 V VCA = 0V

Phase c -Vcap+

ap+ -Vc

Phase a
Vab = Vcap

Phase B

Phase b

Vca = -Vcap

-V ca p+

VBC = 0 V

Vbc = 0 V

Phase C Phase A
VAB = -Vcap VCA = Vcap

Phase c -Vcap+ Phase a

Vab = Vcap

Phase B
VBC = 0V

+Vcap+V +V

cap

Phase b
Vbc = 0V

Vca = -Vcap

Phase C Phase A

+Vcap-Vcap+

cap

Phase c Phase a
Vab = Vcap

VAB = -Vcap VCA = Vcap

Phase B
VBC = 0V

+Vcapcap -

Phase b
Vbc = -Vcap

Vca = 0V

Phase C Phase A

+V

Phase c Phase a
Vab = Vcap

-Vcap+

VAB = -Vcap VCA = 0V

Phase B
VBC = Vcap

+Vcap-

Phase b
Vbc = -Vcap

Vca = 0V

Phase C

-Vcap+

Phase c

Fig. 11: Conguration that used multiple capacitor connected in parallel.

A block diagram of the control system is shown in Fig. 12. The input and output voltages and currents are sensed by Hall effect devices, and are digitized using analog-to-digital converters (ADC). The microcontroller transforms these into d-q coordinates, as in Eq. (1). The DC capacitor voltages of the nine switch cells are also measured using differential amplier circuits, and digitized using ADCs. The microcontroller performs the space vector modulation, Eq. (4), and chooses the capacitor for the single-capacitor control scheme. The microcontroller is interfaced to the switch cells through complex programmable logic devices (CPLDs). The CPLDs are addressable by the microcontroller, and store the current states of all switches. In addition, the states of all switches during the next sub-interval can be loaded into the CPLDs. The CPLDs implement the functions of timing and pulse-width modulation. The capacitor and space vector data are decoded by lookup table to generate the state of each switch cell. These data are further decoded by other CPLDs into the gate signals for the IGBTs. To avoid cross-conduction of the IGBTs during their switching transitions, which would lead to momentary shorting of the DC bus voltages through the IGBTs, the turnoff transitions of the IGBTs occurs rst. In other words, those IGBTs that were previously on, but will be turned off, are switched rst. After a controllable delay, the turn-on transitions are triggered (i.e., the IGBTs that were previously

-V ca p+

c -V ap + -V ca p+

Voltage and current sense circuits

A/C Converters 40 MHz Microproceesor Load values of space vectors for each of 5 intervals Capacitor # Load values of four duty cycles per sw period

Clock 25 MHz Compensates for latency of flash memory Timer (CPLD) 40 ns resolution for each interval Code representing present interval Data buffer (CPLD) Delay
Turn off

Sets dead time to ensure non-overlapping conduction Delays implemented within timer CPLD Delay
Turn on

update data every 100 msec

Lookup table (Flash memory) Converters space vectors to switch states Lookup table (Flash memory) Converters space vectors to switch states Lookup table (Flash memory) Converters space vectors to switch states

Switch cell control (CPLD)

To opto-isolated gate driver Phase A

Switch cell control (CPLD)

To opto-isolated gate driver Phase B

off, but will be turned on, are switched). The gate signals from the CPLDs are sent through opto-isolated gate driver circuits to the IGBTs in power stage. IV. EXPERIMENTAL RESULTS A prototype was constructed to demonstrate the validity of the control strategy. The prototype was connected to the 60 Hz utility, and transferred power to resistive load. The input line-to-line voltages are sensed and used as the reference input space vector. The output space vector was programmed in the microcontroller. The converter operated at a switching frequency of 50 kHz. Figures 13 to 15 show the waveforms for operation with the single-capacitor control scheme. The converter was programmed to produce an output frequency of 30 Hz, with

Fig. 13: Input and output waveforms for the single-capacitor control scheme. Trace 1: 60 Hz line-to-line voltage at input terminal. Trace 2: 60 Hz input current. Trace 3: 30 Hz line-to-line output voltage. Trace 4: 30 Hz output current.

High-level control algorithm Space-vector control of converter currents Field-oriented control of generator

19 bit data bus representing present input and output space vectors and capacitor #

Switch cell control (CPLD)

To opto-isolated gate driver Phase C

Fig. 12: Block diagram of the control system.

Fig. 14: Waveforms from single-capacitor control scheme: capacitor voltage and 30 Hz output voltage

Fig. 15: Waveforms from single-capacitor control scheme: capacitor voltage and ltered 30 Hz output voltage.

Decoding logic Break before make logic Alternating conduction logic

input modulation index, M in = Vref in /Vcap , of 0.94 and output modulation index, M out = Vref out /Vcap , of 0.87. Figures 16 to 18 show the waveforms when the converter operated with the eight-capacitor control scheme. The converter was also programmed to produce the same operating point as in the single-capacitor control scheme case. V. CONCLUSION The laboratory experiment proves that the proposed new modular matrix converter is valid and operates as claimed. Space vector control of both the input and output side has been implemented, to convert a given three-phase input into a three-phase output of given desired frequency, magnitude, and phase. With both the single-capacitor control scheme and the multiple-capacitor control scheme, it was observed that the capacitor voltages naturally remained balanced and stable. The converter operated with an IGBT switching frequency of 50 kHz. R EFERENCES
[1] A. Nabae, I. Takahashi, and H. Akagi, A New Neutral-Point Clamped PWM Inverter, IEEE Trans. on Industry Applications, vol. IA-17, pp. 518523, Sep./Oct. 1981. [2] P. Bhagwat and V. Stefanovi , Generalized Structure of a Multilevel c PWM Inverter, IEEE Trans. on Industry Applications, vol. IA-19, pp. 10571069, Nov./Dec. 1983. [3] L. M. Tolbert and F. Z. Peng, Multilevel Converter for Large Electric Drives, IEEE Applied Power Electronics Conference, vol. 2, pp. 530 536, 1998. [4] B. Lin, Y. Chien, and H. Lu, Multilevel Inverter with Series Connection of H-Bridge Cells, IEEE International Conference on Power Electronics and Drive Systems, pp. 859864, Jul. 1999. [5] F. Z. Peng, J. S. Lai, J. McKeever, and J. VanCoevering, A Multilevel Voltage-Source Inverter with Separate DC Sources for Static VAR Generation, Conf. Rec. of IEEE IAS Annual Meeting, vol. 3, pp. 25412548, Oct. 1995. [6] R. W. Erickson and O. A. Al-Naseem, A New Family of Matrix Converters, IEEE Industrial Electronics Society Annual Conference (IECON01), vol. 2, pp. 15151520, Nov./Dec. 2001. [7] L. Huber and D. Borojevi , Space Vector Modulation Three-Phase to c Three-Phase Matrix Converter with Input Power Factor Correction, IEEE Trans. on Industry Applications, vol. 31, Nov./Dec. 1995. [8] J. Oyama, T. Higuchi, E. Yamada, T. Koga, and T. Lipo, New Control strategy for Matrix Converter, IEEE Power Electronics Specialists Conference, pp. 360367, 1989.

Fig. 16: Input and output waveforms for the eight-capacitor control scheme. Trace 1: 60 Hz line-to-line voltage at input terminal. Trace 2: 60 Hz input current. Trace 3: 30 Hz line-to-line output voltage. Trace 4: 30 Hz output current.

Fig. 17: Waveforms from multiple-capacitor control scheme: capacitor voltage and 30 Hz output voltage

Fig. 18: Waveforms from multiple-capacitor control scheme: capacitor voltage and ltered 30 Hz output voltage.