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Chopper: The variable dc voltage is controlled by varying the on- and off-times of a converter. Fig. 4.1 is a schematic diagram of the chopper.
The duty cycle d can be changed in two ways: (i) varying the on-time (constant switching frequency). (ii) varying the chopping frequency. Constant switching frequency has many advantages in practice.
Fig. 4.4 is first-quadrant operation with zero voltage across the load.
where Kr = Vs/Vcm, Vs is the source voltage, and Vcm is the maximum control voltage. Increasing the chopping frequency decreases the delay time, and its becomes a simple gain.
Its disadvantage: it cannot transfer power from dc link into ac mains. Fig. 4.12 Chopper with regeneration capability
The generating converter has to be operated at triggering angles greater that 90.
where 4.9.2 Instantaneous steady-state computation (including harmonics) The equations of the motor for on and off times (continuous current conduction)
dia Vs = E + R a ia + La , 0 t dT dt dia 0 = E + R a i a + La , dT t T dt
IbR a , p.u. R an = Vb
V Vn = s , p.u. Vb
m mn = , p.u. b
) + I a 0e
t Ta
, 0 < t < dT
E ia ( t ) = (1 e Ra
t1 Ta
) + Ia1e
t1 Ta
, dT t dT
Ia 0 =
Vs (edT / Ta 1) R a (eT / Ta 1)
E Ra
The critical duty cycle: the limiting or minimum value of duty cycle for continuous current; Ia0 equates to zero. The relevant equations for discontinuous current-conduction mode
dia Vs = E + R a ia + La , 0 t dT dt
dia 0 = E + R a ia + La , dT t t x + dT dt
Hence,
V E Ia1 = s (1 e dT / Ta ) Ra
E (1 e ia ( t x + dT ) = Ra
tx Ta tx Ta
) + Ia1e
), 0 < t < dT
( t dT ) Ta
ia ( t ) = Ia1e
( t dT ) Ta
E (1 e Ra
), dT t t x - dT
ia ( t ) = 0,
(t x + dT ) < t < T
Transistor and diode currents for motoring operation in the continuous-conduction mode.
where
Va =
An =
dT Vs = dVs T
2 Vs n dT sin c n 2
c = 2fc =
2 T n dT n = c 2 2
where
V E Iav = a Ra
n = cos1{
Z n = R a + jnc La
Ra }
2 2 R a + n 2c L2 a
The current controller can be (i) Pulse-Width-Modulation (PWM) controller (ii) Hysteresis controller Fig. 4.21 shows on- and off-time for PWM
ia i* + i, reset v a = 0 a
Fig. 4.23