Pg. No. 9 11.

The initial output of the following circuit is 1, if we apply 010101 at input a (first bit is zero) then what is the bit pattern generated at the output Y a) 010101 b) 101010 c) remains at 0 d) remains at 1

12. The circuit shown below is.

a b) 3 input XOR gate c) Half adder. d) 3 input XNOR gate

) Full adder.

13. consider the follwing logic circuit consisting of 2 x 4 line decoders, for each of the decoder F0 = 1 when i1 = 0, i2 = 0 ; F1 = 1 when i1 = 0, i2 = 1 and so on. Then what is g(x, y, z) ? a)xy +xyz b) xyz c) (xy+xy)z d)1

14. Identify the output equations for the following circuit

a) P(A,B,C) = m (1,2,4,7) Q(A,B,C) = m (2,3,4,7) b) P(A,B,C) = m (1,2,4,7) Q(A,B,C) = m (1,2,3,7) c) P(A,B,C) = m (1,2,4,7) Q(A,B,C) = m (3,5,6,7) d) P(A,B,C) = m (3,5,6,7) Q(A,B,C) = m (1,2,4,7) 15. In a digital Computer Binary subtraction is performed a) In the same way we perform subtraction in decimal number system b) using two;s complement method c) Using 9s complement method. d) using 10s complement. Pg.No. 10 16. The logic expression Y = m ( 0,3,6,7,10,12,15) is equivalent to a) Y = (pie)M ( 0,3,6,7,10,12,15) b) Y = (pie) M (1,2,4,5,8,9,11,13,14) c) Y = m (1,2,4,5,8,9,11,13,14) d) Y = m ( 3,0,10,12)

7. The output Boolean equations of the circuit below are

a) X = ab + a b Y = ab b) X = ab + ab Y = ab c) X = ab + ab Y = ab d) X = ab + ab Y = ab

18. The circuit shown in the below fig. represents a) half adder / subtractor X = Sum / difference, Y = carry, Z = Borrew. b) half adder / subtractor X = Carry, Y = Borrow, Z = Sum/difference c) half adder / subtractor X = Sum/difference, Y = borrow, Z = carry d) none of the above

19.What is the output code generated by the following circuit ?

a) Decimal Code b) Octal Code c) One Hot code d) Hexadecimal Code Pg.No. 11

Page11 20. A system which accepts am M-bit and established the stated 1 on one only one of 2^m output is calleda) Decoder b) demultiplexer c) multiplexer d) encoder

21. In a half-adder having two inputs A and B and two outputs S(sum) C (Carry) , the Boolean expressions for S and C in terms of A and B is a) S = A\B + AB\ ; C = AB b) S = AB + A\B ; C = A + B c) S = A\B\+ AV ; C = A+ B\ D) S = A\B + AB\ ; C = A\+B

22. The logic circuit shown in thr figure represents a a) Full adder b) Half adder c) Half subtractor d) Boolean multiplexer 23. Which one of the following can be used as a parallel to series converter ? a) Decoder b) Digital Counter c) multiplexer d) Demultiplexer 24) The number of 4-line to 16 line decoders required to make an 8 line to 256 decoder is a) 16 b) 17 c) 32 d) 64 24. The number of 4-line-to-16-line decoders required to make am 8-line-to-256-line decoder is

a)A b)B c)AB d) AB + AB 26. Consider the following statements: A multiplexer 1.Selets one of the several inputs ant transmits it to a single output 2. Routs the data from a single input and transmits it to a single output 3.converts parallel data into serial data 4. Is a combinational circuit

27. Choose the universal element from the following: a) digital Magnitude comparator b) multiplexer c) encoder d) Binary parallel adder. 28. the minimum number of 2-to-1 multiplexer required to realize a 4-to-1 multiplexer is a) a b) 2 c) 3 4) 4 29. Full adder can be converted into full subtractor by using which of the following gate..? a) NAND b)NOR c) XOR d) Any of the given gates

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0. A 3-to-8 decoder is shown beow:

All the output lines of the chip will be high, when all the inputs 1,2 and 3. a) are x ; G1 low, G2 low b) are x ; G1 high, G2 low c) are 000 ; G1 high, G2 low d) are high ; G1 high, G2 low

31. To realize the given truth table from the circuit shown in the figure, the input to j in terms of A and B would have to be. a)(AB) b) A b) B D) AB

34.The circuit shown in the figure is

a) an adder circuit. b) an subtractor circuit. c) one bit comparator circuit d) parity generator circuit

20. A system which accepts an M-bit and established the stated 1 on one only one of 2^m output is calleda) Decoder b) demultiplexer c) multiplexer d) encoder 23. Which one of the following can be used as a parallel to series converter ? a) Decoder b) Digital Counter c) multiplexer d) Demultiplexer 24) The number of 4-line to 16 line decoders required to make an 8 line to 256 decoder is a) 16 b) 17 c) 32 d) 64 25) The function F implemented by the multiplexer chip shown in fig. is

a)A b)B c)AB d) AB + AB 28. the minimum number of 2-to-1 multiplexer required to realize a 4-to-1 multiplexer is a) a b) 2 c) 3 4) 4

Pg. No.13 36. The logic circuit realized by the circuit shown in the given figure will be

1 2 3 4

F F = B (EXOR) C F = A (EXNOR) C F = A (EXOR) C

= B (EXNOR) C

3 the output code is in BCD. a) BCD code b) Gray code c) one hot code d) excess 3 code.

7. Identify input code of the following circuit, if

38. Design clocked J-K , T & D flip flops. 39. Convert S-R F.F.into J-K , T & D flip flops.

Pg. No 17 A 4 bit module 16 ripple counter uses JK filp flop. If the propogation delay of each flipflop is 50ns, the max clock frequency that can be used is. a) 20Mhz b) 10 Mhz c) 5 Mhz d) 4 Mhz 2 A SR flip flop can be converted into a T flip flop. If the connecting--to Q and -- to Q a) Qn +1 = Q b) S = Q, R = Q c) S = Q, R = Q d) S = Q, R = Q 04. A twisted ring counter is made by using a single D flip-Flop. The resulting Circuit a ) SR Filp-Flop b) JK Filp-Flop c) D Filp-Flop d) T Filp-Flop
1

06. The counter shown in the figure has initially Q2 Q1 Q0 = 000. The status of Q2 Q1 Q0 after the first pulse is a) 001 b) 010 c) 100 d)101

11 .figure shows Mod k counter here K is equal to a) 1 b) 2 c) 3 d) 4

Page 18,19

12. The correct cyclic sequens of the outputs (Qo, Q1) for the JK flip flop circuit shown in the fig. when sequens of clock pulses are applied

a) 00, 10, 01, 00, 10, 01 b) 00, 01, 10,00,01, 10.. c) 00, 11, 00, 11, 00. d) ? 13. The digital block in figure is realized using two positive edge triggred D-flip flop .Assume that for t < t0, Q1 = Q2 = 0. The circuit in the digital block is given by a) fig. a b) fig. b c) fig.c d) fig d

14. What is the output signal frequency of the following counter if the clock frequency is 16 Khz ? All J and K Inputs are connected to 1. a) 4 Khz b) 8 Khz c) 10 khz d) 16 Khz

1 Arrangement of J-K flip flop a) Shift registor b) Mod 3 counter c) Mod 2 Counter d) None of the above

5.The function performed by the following