Sana'a University Faculty of Engineering Communications Department

NMOS IN FLASH MEMORY

Keywords :
NOR, NAND, MOS, CELL,WRITE, READ, EEPROM

Abstract :
Flash Memory A type of EEPROM (Electrically-Erasable Programmable Read-Only Memory). Non-volatile, solid state technology, Relatively limited lifespan Information is stored in an array of memory cells made from MOSFET transistors . NOR, NAND, DINOR, and AND are the main architectures developed for flash memories. One of the most popular alternatives for portable device storage Continues to be among the most aggressively scaled electronic technologies Definition for operations in memory by using MOS transistor as Programming, Erasing and Writing.

Introduction
Flash Memory History
Flash memory (both NOR and NAND types) was invented by Dr. Fujio Masuoka while working for Toshiba circa 1980.According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera. Dr. Masuoka presented the invention at the IEEE 1984 International Electron Devices Meeting (IEDM) held in San Francisco. Intel Corporation saw the massive potential of the invention and introduced the first commercial NOR type flash chip in 1988. NOR-based flash has long erase and write times, but provides full address and data buses, allowing random access to any memory location. NOR-based flash was the basis of early flash-based removable media; CompactFlash was originally based on it, though later cards moved to less expensive NAND flash.

Technical Overview of Flash Memory

Flash memory is non-volatile, that no power needed to maintain the information stored in the chip. In addition, flash memory offers fast read access times (though not as fast as volatile DRAM memory used for main memory in PCs) and flash memory is better shock resistance than other hard disks. These characteristics explain the popularity of flash memory for applications such as storage on battery-powered devices. Flash memory is a type of EEPROM chip, which stands for Electronically Erasable Programmable Read Only Memory. It has a grid of columns and rows with a cell that has two transistors at each intersection Here are a few examples of flash memory using NAND and NOR circuits: Your computer's BIOS chip CompactFlash (most often found in digital cameras) SmartMedia (most often found in digital cameras) Memory Stick (most often found in digital cameras) PCMCIA Type I and Type II memory cards (used as solid-state disks in laptops) Memory cards for video game consoles

ARCHITECTURE Flash Memory :

NOR flash

NOR flash memory wiring and structure on silicon In NOR gate flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a NOR gate: when one of the word lines (connected to the cell's CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR Flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device. The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in a single memory product.

Programming
A single-level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate. A NOR flash cell can be programmed, or set to a binary "0" value, by the following procedure: an elevated on-voltage (typically >5 V) is applied to the CG. the channel is now turned on, so electrons can flow from the source to the drain (assuming an NMOS transistor) the source-drain current is sufficiently high to cause some high energy electrons to jump through the insulating layer onto the FG, via a process called hot-electron injection.

Programming a NOR memory cell (setting it to logical 0), via hot-electron injection.

Erasing
To erase a NOR flash cell (resetting it to the "1" state), a large voltage of the opposite polarity is applied between the CG and source terminal, pulling the electrons off the FG through quantum tunneling. Modern NOR flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can only be performed on a block-wise basis; all the cells in an erase segment must be erased together. Programming of NOR cells, however, can generally be performed one byte or word at a time

Erasing a NOR memory cell (setting it to logical 1), via quantum tunneling.

NAND FLASH

NAND flash memory wiring and structure on silicon NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and only if all word lines are pulled high (above the transistors' V T) is the bit line pulled low. These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR flash. Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. Whereas NOR flash might address memory by page then word, NAND flash might address it by page, word and bit. Bit-level addressing suits bit-serial applications (such as hard disk emulation), which access only 1 bit at a time. Execute-In-Place applications, on the other hand, require every bit in a word to be accessed simultaneously. This requires word-level addressing. In any case, both bit and word addressing modes are possible with either NOR or NAND flash. To read, first the desired group is selected (in the same way that a single transistor is selected from a NOR array). Next, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the V T of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed. Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. (The ground wires and bit lines are actually much wider than the lines in the diagrams.) In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistor below the size where they can be made reliably, to the size where further reductions would increase the number of faults faster than it would increase the total storage available.

Writing and erasing

NAND flash uses tunnel injection for writing and tunnel release for erasing. NAND flash memory forms the core of the removable USB storage devices known as USB flash drives, as well as most memory card formats and solid-state drives available today.

NAND architecture is based upon independent blocks Blocks are the smallest erasable units Pages are the smallest programmable units Partial pages can be programmed in some devices

DINOR Cell
DINOR (divided bit-line NOR) and AND architectures are two other flash architectures that attempt to reduce die area compared to the conventional NOR configuration. Both architectures were co developed by Hitachi and Mitsubishi.

The DINOR design uses sub-bit lines in polysilicon. Mitsubishi states that its device shows low power dissipation, sector erase, fast access time, high data transfer rate, and 3V operation. Its device uses a complex manufacturing process involving a 0.5m CMOS triple well, triple-level polysilicon, tungsten plugs, and two layers of metal.

AND Cell
With AND architecture, the metal bit line is replaced by an embedded diffusion line. This provides a reduction in cell size. The 32Mbit AND-based flash memory device proposed by Hitachi needs a single 3V power supply. In random access mode, the device is slower than a NOR-based device. Hitachis device is specified to operate with a 50ns high-speed serial access time.

Structure and Operation of Flash Memory

Device Structure
Similar to MOSFET Structure Added Floating Gate (FG) between Control Gate (CG) and inversion layer FG surrounded by insulators

FG traps electrons (~50 years) CG is same as MOSFET gate Charged FG disrupts / affects inversion layer Current flows from the drain to source via inversion layer Flash memorys radical approach to storage technology dispenses with mechanical components and represents information with the electron. To harness those electrons, solid state disks begin with the flash memory cell. Each cell is composed of nine major components: the word line, bit line, control gate, floating gate, oxide layer, drain, source, ground, and substrate. These unbelievably tiny cells millions of which are arranged in an electrically-connected grid serve as the building block of todays flash devices.

The structure of NAND flash cell. The black lines represent current paths with or without wires. All solid-state memory is designed to record states, or the strength of an electric current which represents a binary digit. Technologies like RAM lose their programmed information when the current is severed as they have no method to retain the electrons that represented information. Conversely, NAND can preserve its states by trapping the electrons with a process known as Fowler-Nordheim Tunneling. The process begins by applying a positive current of approximately twelve volts to the word line and bit line. The positive charge on the bit line pulls a rush of electrons from the source to the drain as the current flows to ground. On the word line, the charge is sufficiently strong to tug a few electrons away from their race to the drain. While the oxide layers are typically a powerful insulator, the excited electrons are able to surmount this barrier and become trapped within the floating gate. These trapped electrons are how flash memory is able to remember the electrons that represent information.

The induction of an electric field (blue outline) along the lines excites electrons and forces them through the oxide layer to become trapped in the floating gate.. Reading information back out of a flash cell is done by a sensor that compares the charge of the trapped electrons against a steady current. If the charge in the gate exceeds fifty percent of the currents strength, the cell is considered to be closed and represents a zero. If the current can move through the floating gate without being impeded by captured electrons, the gate is considered open and represents a binary one.

Flash memory employs blocks composed of thousands of NAND cells . Each block uses a common word and bit line .

Read Function
Logic state determined by current flow amount. Let ID be the current flow in a normal MOSFET. Let IDF be the current flow in a flash transistor. If IDF ID LOGIC 1. If IDF < ID (significantly less than) LOGIC 0 . Flash Memory senses the amount of current flowing through its inversion layer as a means of logic state determination.

Write Function Logic 0

Electrons are injected into the FG via hot-electron injection. Charged FG partially cancels the CGs E-field. Vt is modified, changing current flow (less). Reduced current flow in inversion layer - logic 0.

Write Function Logic 1

Electrons are tunneled out of the FG. FG no longer partially cancels the CGs E-field. Vt is back to default. Current flow in inversion layer returns to normal - logic 1.

Flash Memory Interfacing:

Flash memory interface is same as SRAM interface, except that the flash memory requires a 12V/5V programming voltage to erase and write new data.

The above figure is the schematic circuit diagram of a NOR flash IC 28F400 from Intel interfaced to a 16-bit (data) processor or a microcontroller. The 28F400 can be configured as 512K x 8 memory device or as a 256K x 16 memory device. Here in the above case its 512K x 8 configuration. The control connections pins CE, OE & WE are similar to SRAM interface. The A0 - A17 are address pins and DQ0 to DQ15 are data pins.The function of each control pins are, OE (OUTPUT ENABLE): Enables the device's outputs through the data buffers during a read cycle. OE is active low. WE (WRITE ENABLE): Controls writes to the command register and array blocks. WE is active low. Addresses and data are latched on the rising edge of the WE pulse. CE (CHIP ENABLE): Activates the device's control logic, input buffers, decoders and sense amplifiers. CE is active low. CE high de-selects the memory device and reduces power consumption to standby levels. If CE and RP are high, but not at a CMOS high level, the standby current will increase due to current flow through the CE and RP input stages. BYTE: Configures whether the device operates in byte-wide mode (x8) or word-wide mode (x16). This pin must be set at powerup or return from deep power-down and not changed during device operation. BYTE pin must be controlled at CMOS levels to meet the CMOS current specification in standby mode. When BYTE is at logic low, the byte-wide mode is enabled, where data is read and programmed on DQ0-DQ7 and DQ15/A-1 becomes the lowest order address that decodes between the upper and lower byte. DQ8-DQ14 are tri-stated during the byte-wide mode. When BYTE is at logic high, the word-wide mode is enabled, where data is read and programmed on DQ0-DQ15. Vpp (PROGRAM/ERASE POWER SUPPLY): For erasing memory array blocks or programming data in each block, a voltage either of 5 V 10% or 12 V 5% must be applied to this pin. When VPP < VPPLK all blocks are locked and protected against Program and Erase commands. RP/PWD (RESET/DEEP POWER-DOWN): Uses three voltage levels (VIL, VIH, and VHH) to control two different functions: reset/deep power-down mode and boot block unlocking. It is backward compatible with the BX/BL/BV products. When RP is at logic low, the device is in reset/deep power-down mode, which puts the outputs at High-Z, resets the Write State Machine, and draws minimum current. When RP is at logic high, the device is in standard operation. When RP transitions from logic-low to logic-high, the device defaults to the read array mode. When RP is at VHH, the boot block is unlocked and can be programmed or erased. This overrides any control from the WP input. The decoder IC 74LS139 is employed in the above circuit for selecting the flash memory through A19 and IO/M as inputs.

Advantages of Flash Memory

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Easy and fast transfer of data is possible The device is completely electronic rather than mechanical. So there are no moving parts in the device. This device is erased as well as re-programmed in large blocks. This mechanism is different from the typical EEPROM chip where erasing is doe in small blocks. So, it has an advantage of speed when writing large blocks of data into the device. As the device is extremely compact and packaged, it is completely water proof, pressure proof, and also has a high degree of durability. There are flash memories with a memory capacity of almost 16GB available. Distinction between NOR and NAND flash Two major types, NOR flash and NAND flash are dominant in the market. The characteristics of NOR flash are lower density, but a random-access interface, while NAND flash has higher density and interface access through command sequence. Timing differences: NAND has higher program and erase speed than NOR. Application: NOR flash is better suited for storing boot or application code. NAND flash is for large data storage, like digital cameras, MP3 players. Differential between NOR and NAND flash NOR and NAND flash differ in two important ways: the connections of the individual memory cells are different the interface provided for reading and writing the memory is different (NOR allows randomaccess for reading, NAND allows only page access)

Applications of Flash Memory

Flash memory is the most widely used device in the field of home video game consoles. It has clearly replaced EEPROM chips and SRAMs for saving data in video games. Flash memory is also used in personal digital assistants (PDAs), digicams, mobile phones, laptops and so on. The device is used for firmware storage. In modern computers, the speed of the system is a very important factor. There is a speed difference between the memory bus of the computer and the parallel flash device. The access times of all the modern SRAMs are below 10 nano seconds. This has urged companies to make shadow code stored in flash and into the RAM. This means that the code is first sent to the flash and then to the RAM for execution. This enables faster response from the CPU as well. Usually a serial flash drive is used for this purpose. As soon as the firmware is decided to be read, a compression is also added so that a smaller chip can be used. Some applications of serial flash include storing firmware for hard drives, DSL modems, wireless network devices, Ethernet controllers and so on.

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Conclusion
As flash devices are completely electronic and not mechanical, it can be a great innovation if it can be used for a hard disk. It will surely be a good replacement as it is advantageous in the field of speed, access, power consumption and so on. But this technology is only being advancing and right now the cost factor is a huge perspective to be looked out for. The production of a flash based hard disk is higher than that of a normal one. Another problem is regarding the support for the operating system. The finite number of erase/write cycles will make it unable to achieve. Although the flash memory technology has been highly advanced, experts still believe that the device can replace all the major type of storage devices being used today. Many companies have started using serial flash device for sequential data accessing. Since the device has lesser pins than the parallel flash memory it can be easily embedded onto a printed circuit board. Although it transmits and recieves only 1 bit at a time, the smaller size, lesser cost and low power consumption factors make this device more suitable. Since the number of pins are less, the size of the device less, causing a reduction in area of the PCB. This also helps in PCB routing.

References
http://www.lascon.co.uk/ for Flash Memory Diagram on slide 4 http://bigtech.blogs.fortune.cnn.com/2008/06/09/intel-faces-volatile-flash-memory-market/ http://www.interfacebus.com/IC_Flash_Memory_Manufacturers.html http://electronics.howstuffworks.com/flash-memory.htm Fundamentals of Modern VLSI Devices. TUAR, Yuan. NING H., Tak pg. 96-97, pg. 85 http://news.cnet.com/Bye-bye-hard-drive,-hello-flash/2100-1006_3-6005849.html Wikipedia - Flash Memory How Stuff Works - Flash Memory http://smithsonianchips.si.edu

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