Weinstein Jason 200911 MASc Thesis

PLUG-AND-PLAY DIGITAL CONTROLLERS FOR SCALABLE LOW-POWER
SWITCH-MODE POWER SUPPLIES

by

Jason Weinstein

A thesis submitted in conformity with the requirements for the degree of
Master of Applied Science
Graduate Department of Electrical and Computer Engineering
University of Toronto

Copyright by Jason Weinstein, 2009
ii

ABSTRACT
Plug-and-Play Digital Controllers for Scalable Low-Power Switch-Mode Power Supplies
by
Jason Weinstein
Master of Applied Science
Graduate Department of Electrical and Computer Engineering
University of Toronto
2009

The purpose of this thesis is to present a novel controller structure for scalable switch-mode
power supplies targeting low power applications. The design employs masterless control,
where each phase is responsible for its own control in a multiphase system. The controller is
capable of automatically configuring itself to work with a single phase system or a
multiphase system. The configuration process allows each controller to determine the
number of phases in the system, as well as to synchronize and sequence the phases. With
this architecture, the same controller design can be used in many types of applications
requiring different numbers of phases, resulting in a decrease in cost and design effort. The
proposed design has been verified experimentally on FPGA and IC implementations.

iii

DEDICATION

Dedicated in memory of my mother, Livia Singer.
iv

Acknowledgements
I could not have completed this work without the help of others. First, I would like to thank
my supervisor, Prof. Aleksandar Prodi, for providing me with this opportunity. His
guidance, knowledge, and support have truly gone above and beyond my expectations.
I would also like to thank my friends in the Laboratory for Low-Power Management and
Integrated Switch-Mode Power Supplies. In particular I would like to acknowledge Zdravko
Lukic, Amir Parayandeh, and Massimo Tarulli for their invaluable assistance with
completing this work.
Finally, I would like to thank the Department of Electrical and Computer Engineering as well
as Toshiba Corporation for sponsoring this project.

v

TABLE OF CONTENTS
1. Introduction ....................................................................................................................... 1
1.1 Thesis Objectives ................................................................................................... 1
1.2 Thesis Overview .................................................................................................... 2
2. Prior Art and Motivation ................................................................................................. 3
2.1 Multiphase SMPS Systems .................................................................................... 3
2.2 Scalable SMPS Systems ......................................................................................... 8
2.3 Modular DC-DC Converters for Medium to High Power Applications ................ 9
2.4 Scalable Low-Power SMPS Systems ................................................................... 10
2.5 Auto-Tuning Controllers for SMPS ..................................................................... 13
3. System Description .......................................................................................................... 15
3.1 System Overview ................................................................................................. 15
3.2 System Benefits .................................................................................................... 19
3.3 Component Descriptions ...................................................................................... 20
3.3.1 Communication Block .............................................................................. 20
3.3.1.1 Communication Protocol ............................................................. 22
3.3.1.2 Transmitter and Receiver ............................................................. 24
3.3.1.3 Transmission Gate ....................................................................... 26
3.3.2 Phase Detector .......................................................................................... 29
3.3.2.1 Phase Detection Process .............................................................. 29
3.3.2.2 Starting Phase Identification ........................................................ 31
vi

3.3.3 LC Estimator and Sequencer .................................................................... 36
3.3.3.1 Charged-Based Inductance Estimation Method ........................... 37
3.3.3.2 LC Estimator and Sequencer Architecture .................................. 41
3.3.4 Digitally-Controlled DLL ......................................................................... 46
3.3.4.1 Selection of the Timing Phase ..................................................... 47
3.3.4.2 Clock Generation Architecture .................................................... 48
3.3.5 Regular Operation .................................................................................... 53
4. Experimental Verification and Results ......................................................................... 56
4.1 Experimental Systems .......................................................................................... 56
4.1.1 FPGA-Based Implementation .................................................................. 56
4.1.2 IC Implementation .................................................................................... 57
4.1.2.1 Chip Overview ............................................................................. 57
4.1.2.2 On-Chip Components .................................................................. 60
4.2 Experimental Results ........................................................................................... 62
4.2.1 Single Phase Operation ............................................................................ 63
4.2.2 Multiphase Operation ............................................................................... 65
4.2.3 Phase Sequencing ..................................................................................... 69
4.2.4 Communication Protocol .......................................................................... 74
5. Conclusion ....................................................................................................................... 76
5.1 Thesis Summary and Contributions ..................................................................... 76
5.2 Future Work ......................................................................................................... 77

vii

Appendix A: Verilog HDL for Digital Blocks ............................................................... 80
Appendix B: Gate-Level Netlist for Communication Block ...................................... 128
Appendix C: PCB Board and Schematics ................................................................... 135
References ............................................................................................................................ 140
viii

LIST OF TABLES
Table 3.1: Communication block inputs and outputs ................................................................... 27
Table 3.2: An example of phase reordering based on charge times with 4 phases. ...................... 46
Table 3.3: Required output frequencies and periods for a system operating at a switching
frequency of 1 MHz for various numbers of phases. .................................................................... 48
Table 4.1: Chip area required by each component ....................................................................... 60

ix

LIST OF FIGURES
Figure 2.1: Multiphase buck converter with n phases .............................................................. 4
Figure 2.2: A comparison of interleaved and non-interleaved switching ................................. 6
Figure 2.3: Centrally controlled scalable SMPS system ......................................................... 11
Figure 3.1: System overview .................................................................................................. 16
Figure 3.2: Block diagram of the plug-and-play controller .................................................... 17
Figure 3.3: Flowchart showing the general operation of each plug-and-play controller ........ 18
Figure 3.4: Communication block diagram ............................................................................ 21
Figure 3.5: Example of a data transmission of the value 4b1010 .......................................... 24
Figure 3.6: A comparison of series mode and bus mode with four phases ............................ 28
Figure 3.7: The phase detection process with four phases ...................................................... 31
Figure 3.8: PCB routing for starting phase identification ....................................................... 33
Figure 3.9: PCB routing for starting phase detection using a RC filter .................................. 34
Figure 3.10: Starting phase detection done with an RC filter ................................................. 35
Figure 3.11: Ripple cancelation for a 6-phase system with identical inductances ................. 39
Figure 3.12: Combined ripple for a 6-phase system where 2 consecutive phases have
different inductance values ..................................................................................................... 40
Figure 3.13: Ripple cancelation in a 6-phase system with optimized phase sequencing ....... 40
Figure 3.14: The charging and discharging process for estimating the LC products ............. 43
Figure 3.15: Flowchart for the phase sequencing algorithm ................................................... 45
Figure 3.16: Digitally-Controlled DLL block diagram ........................................................... 49
Figure 3.17: Flowchart of the operation of the Digital Frequency Compensator .................. 52
x

Figure 3.18: Waveforms during regular operation in steady-state ......................................... 55
Figure 4.1: FPGA-based prototype ......................................................................................... 57
Figure 4.2: Die photograph of the fabricated IC ..................................................................... 59
Figure 4.3: Chip layout diagram ............................................................................................. 61
Figure 4.4: Start-up procedure for single phase operation using an IC controller .................. 64
Figure 4.5: Closed-loop steady-state single phase operation with an IC controller ............... 64
Figure 4.6: Configuration and regular operation with 4 phases with the FPGA-based
controller ................................................................................................................................. 66
Figure 4.7: Open-loop operation with 2 phases using IC controllers ..................................... 67
Figure 4.8: Closed-loop steady-state operation with 2 phases using the FPGA-based system
................................................................................................................................................. 67
................................................................................................................................................. 68
................................................................................................................................................. 68
Figure 4.11: One phase completes the charge process to estimate its LC product ................. 69
Figure 4.12: The charge process for two phases with different inductance values ................ 70
Figure 4.13: The steady-state AC current ripple of the phase with a 0.5H inductor ............ 71
Figure 4.14: The steady-state AC current ripple of the phase with a 1.0H inductor ............ 71
Figure 4.15: The steady-state total AC current ripple with unoptimized phase sequencing .. 73
Figure 4.16: The steady-state total AC current ripple with optimized phase sequencing ...... 73
Figure 4.17: Simulation of 8 communication blocks arranged in a ring configuration .......... 75
Figure 5.1: Current measurements being shared on the communication bus in CPM mode .. 78
CHAPTER 1: INTRODUCTION 1

Chapter 1
Introduction
The topic of this thesis is the design and practical implementation of plug-and-play digital
controllers for scalable low-power switch-mode power supplies (SMPS). The objective is to
produce a controller capable of operating both in single phase mode as well as multiphase
mode, with a variable number of phases. As a result, the same controller design can be
reused in applications requiring one or only a few phases in addition to those requiring many
phases.
1.1 Thesis Objectives
The aim of this thesis is to develop a scalable architecture for low-power applications.
Scalable controllers have been adopted for medium to high power applications, but have not
yet been widely employed for low-power SMPS (applications consuming between several
watts and several hundred watts of power) partly due to the challenges relating to auto-
configuration and synchronization of power modules. The goal of this work is to introduce a
CHAPTER 1: INTRODUCTION 2

solution to these challenges that is cost-effective for a wide range of low-power applications.
Another objective is to allow the design to be easily modified to work with other features in
the future, such as current-programmed mode control and auto-tuning compensation.
1.2 Thesis Overview
The thesis proceeds in Chapter 2 with an overview of multiphase systems and existing
solutions for scalable power systems. Motivation for the masterless approach for scalable
low-power SMPS controllers is provided. Chapter 3 proposes a novel design for a scalable
controller. An overview of the system is provided, as well as descriptions of its key
components. In Chapter 4 FPGA and IC prototype systems are presented and experimental
results are demonstrated, verifying the functionality of the proposed system. Finally, Chapter
5 highlights the major elements of this thesis and recommends potential related work for the
future.

CHAPTER 2: PRIOR ART AND MOTIVATION 3

Chapter 2
Prior Art and Motivation
In this chapter, the goals of multiphase SMPS are explained. The tradeoffs between
multiphase and single phase systems lead to the desire for scalable solutions. Existing
solutions for scalable converters have allowed flexibility in terms of the number of phases in
a converter, but have several drawbacks that limit their use in a wide range of practical low-
power applications.
2.1 Multiphase SMPS Systems
A popular practice in the implementation of SMPS systems is to place two or more power
stages, or phases, in parallel to form a multiphase system, as shown in Figure 2.1.

Figure 2.1: Multiphase buck converter with n phases
In a multiphase system, two or more power stages are arranged such that they share a
common input voltage source and a common output load. This is in contrast to a single
phase system, which contains only one filter and requires only one switching signal (or one
set of switching signals in the case of a synchronous rectified single phase system). The
phases are connected in parallel and have separate switching networks and LC filters. This
paralleling results in many important advantages compared to a single phase system [1]:
The output voltage ripple is reduced through the interleaving of the phases.
Interleaving denotes that the switching sequences of the phases are evenly spaced
from each other over the course of one switching cycle. As an example, Figure 2.2
illustrates interleaving with 3 phases, where the switching signals of the phases are

placed 120 apart from each other. This advantage has an important implication: the
value of the output filter can be reduced while still satisfying the maximum ripple
requirement, resulting in a reduction in cost and size.
The dynamic response of the system can be improved. For a multiphase system with
n phases each with an inductance L, the total equivalent inductance is L/n, which
enables the system to respond faster to load changes. Also, with interleaved
switching signals, oversampling (sampling more than once per switching cycle) can
allow a faster system response since the duty ratio can be effectively updated more
than once per switching cycle.
The input filter requirements are minimized through interleaving. In Figure 2.2, the
current drawn from the input source is shown for the case with 3 phases where an
interleaved switching pattern is used and for the case where all phases are switched
simultaneously, in phase with each other. In the case where interleaving is employed,
the peak magnitude of the current is 3 times smaller compared to the non-interleaved
case. Also, the frequency is 3 times larger. As a result, the size of the input filter
capacitor can be reduced. The purpose of this filter is to minimize noise as well as to
ensure that the input voltage remains stable.
Power efficiency can be improved by dynamically adding or dropping phases. For
applications with widely varying load conditions, high efficiency can be achieved
over the full operating range by turning phases on or off depending on the output
current, resulting in a higher and flatter efficiency curve. For example, at light loads,
running a SMPS with fewer phases will generally result in better efficiency.

Multiphase systems can provide redundancy. With an intelligent controller, if one or
more phases fail, the remaining phases can continue to deliver the required power.
Heat distribution is improved in multiphase systems. Since the current is shared
among a number of phases, heat dissipates across a larger area, often eliminating the
need for a heat sink. Further, the need for expensive semiconductor switching
devices with very high current ratings is eliminated.
Due to improved heat distribution, for a given area multiphase systems have higher
current ratings.

Figure 2.2: A comparison of interleaved and non-interleaved switching

The above advantages apply when comparing multiphase systems to single phase systems, as
well as when comparing a multiphase system with a large number of phases to another with
fewer phases.
The advantages of multiphase operation, however, come at a cost. Multiphase systems have
the following drawbacks compared to their single phase counterparts:
A larger number of components is required as each phase is added. Specifically,
additional power switches, gate drivers, and LC filter components are needed for each
additional phase (although the total size of the components does not necessarily grow
linearly with the number of phases).
The control of multiphase systems is more challenging, resulting in higher complexity
and cost in the controller. This is due mainly to the presence of multiple switching
networks.
Due to the many tradeoffs between single phase and multiphase systems of various sizes,
there is no single optimal number of phases for all SMPS applications. The number of
phases should be chosen only after carefully considering the requirements of each particular
application.
For example, a desktop computer would likely employ a multiphase SMPS to deliver power
to its state-of-the-art multicore processor. Modern processors can draw peak currents of 70
A or more [2]. In this type of application, the high current rating of the load would likely
outweigh the extra cost and space requirements of the multiphase converter. A cellular
phone, on the other hand, would most likely use a single phase power supply to deliver
power to its components. This type of application would have a relatively small current

requirement. Furthermore, the size restriction due to portability combined with the
downward pressure on price would make a single phase system the better choice.
2.2 Scalable SMPS Systems
The advantages and disadvantages between multiphase and single phase systems (or between
multiphase systems with larger and smaller numbers of phases) bring about the appeal for
scalable SMPS systems. The idea is to allow a controller to be used in a system with a
number of phases that can vary within a specified range. This results in two significant
advantages.
Firstly, the same controller can be used for many different kinds of applications. If the
controller is capable of operating with, for example, anywhere from 1 to 10 phases, it can be
used in both low current and high current applications. The controller could be used in single
phase mode for powering a cellular phone. On the other hand, the controller could
alternatively be configured with more phases to deliver the necessary current to a computer
processor. In these cases, multiple unique, non-scalable controller designs could be replaced
with one scalable controller design. The advantage in this is the design re-use of the
controller. A single scalable controller design can be used in many different applications,
whereas a non-scalable controller with a fixed number of phases would need to be designed
with a specific number of phases for each new kind of application. A scalable design could
result in a significant savings in cost and time with the design and verification process.
Secondly, with a scalable controller, the number of phases can be changed as the power
requirements of an application vary. With a traditional non-scalable controller, when the

current requirements of the load exceed the rated maximum value, the entire power supply
needs to be replaced. In contrast, with a scalable system, phases can be added or removed as
needed. For example, in the past it has often been the case that a new generation of computer
processors has a larger current requirement compared to the previous generation. If a
processor is upgraded to the latest generation, the new current requirements may exceed the
power supplys rating. With a non-scalable system, the entire power supply would need to
be replaced as well. On the other hand, with a scalable system, one or more phases could be
added, with the original hardware remaining intact. This could result in a considerable
savings in cost compared to a non-scalable system. There could also be a decrease in the
environmental impact over the life cycle of the computer. With a non-scalable system, the
hassle of needing to replace the power supply in the future could be avoided by
overdesigning the system to have a power rating exceeding the present requirements,
however, this would result in an increase in cost.
2.3 Modular DC-DC Converters for Medium to High
Power Applications
Modular solutions have been developed for dc-dc conversion suitable for medium to high
power applications [3,4,5,6,7]. These solutions offer the advantage of allowing the user to
plug in additional modules to deliver the necessary power for a specific application. This
allows the same design to be reused in different kinds of applications and for the power
system to be easily changed as the applications power requirements vary over time.
However, the previously presented architectures are only suitable for medium to high power

loads, such as automotive and telecommunications applications. They cannot be used
directly for portable or low-power applications such as cellular phones or laptop computers
due to their size, cost, losses, and voltage capabilities. [3] offers a scalable DC-DC solution,
but only provides output voltages of 24V, 28V, and 48V, making it unsuitable for portable
applications. A dynamic response of 1ms is achieved, which is poor compared to existing
state-of-the-art low-power switch-mode power supplies. [4] provides an output voltage of
46-52V, also too high for portable applications. Its dimensions (112mm x 44mm x 282mm)
and weight (1.1kg) also make it unsuitable for the applications of interest. In [5], the system
is designed for higher voltage and higher power automotive applications. The semiconductor
components of the power stage are unsuitable for low-voltage applications. [6] presents
another modular dc-dc converter targeted for automotive applications that would require
overly complex hardware and would be too large for portable applications. It would also not
be suitable for producing the low output voltages required in many of todays portable
applications.
2.4 Scalable Low-Power SMPS Systems
Solutions for scalable low-power SMPS controllers have been recently developed
[8,9,10,11,12,13]. These systems employ centralized control, meaning that one chip is
responsible for controlling all phases present in the system. This type of system is depicted
in Figure 2.3.

Figure 2.3: Centrally controlled scalable SMPS system
In this system, a central controller capable of operating with a variable number of phases is
employed. The key outputs of the controller are the pulse-width modulated switching signals
transmitted to each of the power stages (MS
1
, SR
1
, ..., MS
n
, SR
n
). These signals would be
connected directed to the gate drivers of the phases in Figure 2.1. The central controller is
responsible for compensating the pulse-width modulated switching signals for all phases in
order to achieve the desired output voltage. Ideally, the central controller should produce
interleaved switching signals in order to realize many of the advantages of multiphase
systems discussed in 2.1.
The central controller in Figure 2.3 can be made scalable, meaning that it can be capable of
operating with any number of phases from 1 to n, where n is the maximum number of phases
supported. The centrally controlled SMPS system of Figure 2.3 achieves the advantages of
scalability described in 2.2. The same controller can be used for different applications where
the number of phases ranges from 1 to n. Also, if the power requirements vary over time,
power stages can be added or removed and the controller can be reprogrammed to support
the new number of phases.

However, the centrally controlled method results in a major drawback. In order to support a
large number of phases, the pin count of the controller must be sufficiently large. For a
multiphase synchronous buck converter system, there must usually be at least 2 pins
dedicated on the controller chip for each phase supported (one pin for each of the switching
signals). In practice, each supported phase would likely require more than 2 pins. To
measure the current of each phase, 2 additional pins would most likely be required, for a total
of at least 4 pins per phase. Measuring phase currents might be required for current-
programmed mode control, for achieving even current distribution among all phases, and for
over-current protection. This means that the pin requirements of the chip grow
proportionally with the maximum number of phases supported. As the pin count of the
controller grows, the chip area will become pad-limited, meaning that extra silicon area
would be required, even if the additional area is not required for the controllers circuitry.
This extra silicon would result in a higher cost for each controller produced. As a result, a
scalable central controller that supports many phases would not be economically feasible for
applications requiring only a few phases. In addition, the power consumption of such a large
chip would be too high to achieve adequate efficiency for a single phase low power SMPS.
A centrally controlled scalable system would only be cost effective if it were scalable over
only a small range of phases, which would partially negate the advantages of scalable
systems.
Also, it is not be feasible to integrate gate drivers and MOSFETs into a centralized controller
that is scalable to support a large number of phases. The integration of gate drivers and
MOSFETs is a desirable feature because it reduces the component count of the power supply.
To support, for example, up to 10 phases, the controller would require 10 gate drivers and 10

MOSFETs. If these components were integrated with the controller, this would result in an
extremely large chip area requirement, which would make the chip too costly for operation
with a single phase or only a few phases. Also, this solution would result in poor heat
distribution.
2.5 Auto-Tuning Controllers for SMPS
In recent years, auto-tuning algorithms have been developed for digital SMPS controllers
[14,15,16,17,18]. These auto-tuning algorithms allow the operation of the controller to be
tuned dynamically, such that near optimal performance can be achieved even if the power
stage parameters vary. In [18], for example, information about the power stage is extracted
by intentionally introducing oscillations through limit cycling. This information is
subsequently used to adjust the compensator. In [15] the compensator is adjusted using
information obtained through relay operation of the system.
Auto-tuning is a desirable feature because the parameters of a power stage can vary greatly
from their nominal values. For example, if the capacitor or inductor values differ from their
nominal values, the power stage will have a different corner frequency, which would affect
the dynamic performance of the power supply. As a result, systems without auto-tuning
usually need to be designed with the worst case scenario in mind to ensure stability, resulting
in sub-optimal dynamic response and efficiency. An alternative to auto-tuning could be to
use power stage components with very tight tolerances. However, this would lead to an
increase in cost and may not necessarily mitigate fluctuations due to temperature and aging.

In the context of scalable multiphase systems, these auto-tuning algorithms can be valuable
since the dynamic characteristics of the system can vary not only due to component
tolerances but also due to the number of phases present in the system. The addition or
removal of phases results in different plant characteristics due to the interleaving switching
pattern in a multiphase converter as well as the parallel placement of multiple output filters.
Auto-tuning controllers could potentially be used to re-tune the systems compensation as
phases are added or removed from a multiphase system, resulting in optimized performance
over a wide phase count range.
Auto-tuning can also be used to configure the phases in a multiphase system in such a way
that the output ripple is reduced. In [19] a method is presented to minimize the ripple by
sequencing the phases in a manner that ensures that the output ripple is minimized.
These auto-tuning controllers, however, can potentially provide only a part of the solution for
the realization of plug-and-play scalable controllers. They do not address other practical
issues such as phase counting, phase synchronization, and inter-phase communication, which
are the main focus of this thesis.
The design of plug-and-play digital controllers can be divided into two challenges:
communication/system management and system control. The problem of system control is
being investigated by other members of our lab and does not fall within the scope of this
thesis. The thesis will investigate the communication and system management for plug-and-
play digital controllers for scalable converters.

CHAPTER 3: SYSTEM DESCRIPTION 15

Chapter 3
System Description
3.1 System Overview
In this chapter, an overview of the systems design and operation is provided. The system,
shown in Figure 3.1, consists of one or more phases operating in an interleaved fashion.
Each phase comprises a power stage and a controller. The power stage includes a pair of
switches and a filter. The controllers of each phase are identical. The system operates
masterlessly, such that each phase is responsible for the control of its own switching pulses.
In order to synchronize the operation and provide a means for sharing information, the
controllers are linked through a one-wire communication line.
The design is a plug-and-play system, meaning that any number of phases can be
configured and the system will operate appropriately. It should be noted that the system does
not support hot-swapping, where phases can be added or removed while the system is
operating and supplying power.

L
n
L
1
L
5
Phase 5
L
2
Phase 2
v
out
(t)
L
3 L
4
Phase 1
Phase 4 Phase 3
Sync/ comm.
line
Phase n
Plug & play
controller
line
1
line
2
v
out
(t)
V
g
Out
Out
1
Out
2
Out
3
L
o
a
d
+
V
g
Out
4
Out
5
Out
n

Figure 3.1: System overview
Figure 3.2 illustrates the structure of each phase. It is a modification of a conventional
single-phase voltage mode controller. Since all controllers are identical, they each contain
the same components depicted in Figure 3.2. Data is transmitted and received using the dual-
mode Communication Block. The Communication Block is responsible for both transmitting
and receiving data. It is capable of operating in two modes: bus mode and series mode. The
communication mode in use at any point in time depends on the state of the switch S
1
.
During initialization, the Phase Detector sets the scalable controllers into a ring
configuration in order to determine the number of phases present in the system. Once the
phase detection process has been completed, the Phase Detector closes the switch S
1
to allow

bus communication. Next, the LC Estimator and Sequencer Block uses a charge-based
algorithm to detect the relative ratios of the phase inductor values. Based on this
measurement and those of the other phases, which are shared on the bus, each phase
independently determines its own unique position in the switching sequence of the entire
structure. The goal of reordering the phases is to minimize the total output ripple of the
converter.

Figure 3.2: Block diagram of the plug-and-play controller
Next, one of the phases is selected as the timing phase. The timing phase uses its Digitally-
Controller DLL to produce a clock signal with a frequency of nf
s
, where n is the number of
phases in the system and f
s
is the switching frequency. This clock signal is used to time when
data is transmitted onto the bus. The timing of the data transmissions is important in order to
achieve interleaved operation. After the Digitally-Controlled DLL has locked to the correct
frequency, regular operation of the system begins. At this point, all phases constantly
monitor the bus to determine when they should begin their respective switching periods. The

error signal, e[n], is also transmitted across the bus. As is the case in a conventional single-
phase voltage mode controller, e[n] is sent to the compensator, which produces a control
signal for the digital pulse-width modulator (DPWM). The DPWM outputs a pulse-width
modulated signal for regulating the duty ratio of the power stage. The flowchart in Figure
3.3 illustrates the procedure performed by each plug-and-play controller, from start up until
regular operation.

Figure 3.3: Flowchart showing the general operation of each plug-and-play controller

3.2 System Benefits
The system described in 3.1 provides several advantages compared to existing solutions. The
architecture is scalable, supporting both single phase and multiphase configurations.
Consequently, the controller can be used in a wide variety of applications and can support
future adjustments in the number of phases.
The architecture achieves the advantages of existing systems described in 2.4, and the
masterless control procedure allows scalability in a more cost effective manner. The silicon
area required for the controllers is always proportional to the number of phases. Since the
number of pins required per phase is fixed and no central controller is required, the system
can be used as a cost effective solution for supplying a functional block of a miniature battery
powered device in a single phase configuration. The design can also be used for a
multiphase setup, allowing for a high current rating, reduced ripple, improved dynamic
response, and superior heat distribution.
To further minimize the pin count, the gate drivers of power MOSFET switches could be
integrated directly with each phases controller. This would not be feasible in a system with
a centralized controller that supports many phases as the required area would be too large.
The gate drivers and power MOSFETs for each phase usually need to be on separate chips
due to heat distribution requirements. If the digital controller of the proposed system could
be integrated with each gate driver and MOSFET, the cost would be minimized if the area
required for the controller is small in comparison to the gate driver and MOSFET.
Furthermore, if a smaller CMOS technology is used for the digital controller, the space

required is reduced in proportion to the technology. However, the area requirements for the
gate driver of MOSFET will remain relatively constant, since these devices must to sized to
meet the current requirements.
With a plug-and-play scalable system, higher efficiency can be achieved since the number of
phases can be adjusted according to the load requirements. Switch-mode power supplies can
achieve very high efficiencies, but the peak efficiency occurs only for a certain range of loads
for a given configuration. With a scalable design, the number of phases can be configured to
ensure that a high efficiency is achieved for the specified load, even if the load varies from
application to application or over time.
3.3 Component Descriptions
3.3.1 Communication Block
The Communication Block of Figure 3.4, present in each phases controller, receives and
transmits data among the phases. The Communication Block is necessary for both the start-
up configuration procedure as well as the regular operation of the system. It operates in two
modes: bus mode and series mode. In bus mode, the communication lines of all phases are
connected to each other. When one phase transmits data, the transmission is read by all other
phases. In series mode, on the other hand, the communication lines are not all connected to
each other. For a system with n phases, there are n communication lines, where each phases
communication line is connected only to the next phase in the ring. As a result, a
transmission from one phase can only be read by the very next phase in the ring. For

example, if the phases are arranged as in Figure 3.1, a transmission from Phase 1 is only seen
by Phase 2, a transmission from Phase 2 is only seen by Phase 3, and so on.

Figure 3.4: Communication block diagram
Different communication modes are used at different steps of operation. During the phase
detection stage, series mode is employed to count the phases. During the remaining stages,
bus mode is enabled to allow information to be shared among all the phases. Communication
is performed using a single line in bus mode. This type of protocol has been selected in order
to minimize the pin count. Each controller only requires two pins for communication, no
matter how many phases are present. An alternative parallel communication protocol would
require more pins. Also, if bus mode were not available, each controller would need to be

directly connected to all other controllers, meaning that the pin requirements would grow
significantly with the number of phases. Furthermore, a plug-and-play controller supporting
a large number of phases would have many unused pins in applications with one or only a
few phases.
The communication line of each controller is connected to a pull-up network, meaning that it
is connected to VDD through a resistor. When the communication block is not transmitting,
it outputs a weak high signal or a high-impedance (Z). If no other phase is transmitting, the
output will remain in a high-impedance state. On the other hand, if another phase transmits
onto that node, the value is pulled to either a strong low (0) or a strong high (1).
The details of the Communication Block are shown in Figure 3.4. It consists of three main
components: a transmitter, a receiver, and a transmission gate. The communication protocol
is described in the following section, followed by explanations of each of the components.
3.3.1.1 Communication Protocol
A single-wire communication protocol has been used in order to minimize the pin count of
the controllers. With this protocol, only two pins on each controller are required for
communication, regardless of the number of phases present. The communication block uses
a serial timing-based protocol to transmit and receive data. Serial single-wire
communication protocols, such as [20], have been proven to be efficient, reliable choices.
The number of bits has been selected based on the minimum amount required to transmit
most packets of information. In this application, only four bits of data are required for

transmitting most of the necessary information, such as the phase count and the ADC error
value. For the few cases where more than four bits are required, multiple transmissions are
performed.
Each phase is responsible for either transmitting or receiving data, depending on the stage of
operation. At the beginning of a transmission, the transmitting phase pulls its
comm_out_internal port low (see Figure 3.4). The receiving phase or phases observe this
transition and prepare to receive the data. After a certain delay, the transmitting phase
outputs the value of the first bit of data. This value is held, and after another short period of
time, the transmitting phase outputs the value of the second bit, and so on. Shortly after the
fourth bit is sent, the transmitting phase releases the output into a high-impedance state, and
the transmission is complete. Meanwhile, the receiving phase or phases sample the output at
specific times to read the data, one bit at a time.
A data transmission is shown in Figure 3.5. In this example, the transmitting phase sends a
value of 4b1010 (an arbitrary value in this example). The receiving phase or phases sample
their respective comm_in ports at the appropriate times, based on the clock signals, to read
the value of the transmission. The signal names correspond to the ports found in Figure 3.4.

Figure 3.5: Example of a data transmission of the value 4b1010
3.3.1.2 Transmitter and Receiver
As described in the previous section, the transmitter uses a timing-based protocol to send 4
bits of data at a time. Both the transmitter and receiver use a series of delay cells to produce
clock signals indicating when the data should be changed to the next bit value (in the case of
the transmitter) and when the communication line should be sampled (in the case of the
receiver). These delay cells are illustrated in Figure 3.4. The first cell of the transmitter has
half the delay of the first delay cell of the receiver. The purpose of this is so that the delay of

the receiver lags behind the transmitter, so that the sampling can occur at approximately the
midway point of each bit.
The example of Figure 3.5 demonstrates how the receivers clock lags behind the
transmitters clock. This mitigates any issues related to metastability and delay variations
between chips. If the communication line were sampled by the receiver at approximately the
same time as the transmitter changes the value, this could lead to metastability problems,
where the register outputs to not settle within the expected time and possibly record incorrect
values. Also, process variations may lead to slightly different delays among different phases.
Sampling at the midpoint allows for a margin of error in the delay. The transmissions have
been limited to only 4 bits at a time to allow for a large margin of error. If a large number of
bits where sent during each transmission, an error in delay time could accumulate after each
sampling point, eventually resulting in an incorrect reading.
If a very large number of phases were needed, further efforts could be put in place to improve
the robustness of the communication. First, the line could be oversampled to compensate for
mismatches in delay. Secondly, programmable delay cells could be used for producing the
clock signals. The cells could be dynamically adjusted such that their delays match those of
other phases.
The receiver indicates when it begins and finishes receiving data through the signals RXStart
and RXEnd. This serves two purposes. Firstly, the RXEnd signal indicates when the
controller may read RXData, the data received during the transmission. Secondly, these
signals are used for timing purposes. During regular operation of the system, these signals

are used to specify when each phase should begin its switching cycle. The timing of the
starting point of each phases switching cycle is vital for proper interleaved operation.
3.3.1.3 Transmission Gate
The transmission gate, shown in Figure 3.4, allows the communication block to operate in
two modes: bus mode and series mode. The purpose of the transmission gate is to function
as an ideal switch, linking the communication input and output ports. When the mode is set
to series mode, comm_in for a given phase depends only on the comm_out signal from the
previous phase in the ring. For the example in Figure 3.1, this means that during series
mode, the output of Phase 1 is only seen by Phase 2. Similarly, the comm_in signal of the
next phase in the ring depends only on the comm_out signal of the given phase. When bus
mode is active, comm_in is shorted to comm_out in all phases. This allows data sent from
any phase to be received by all the other phases in the ring. At any given time, all phases
operate in either bus mode or series mode. During transitions between series mode and bus
mode, the controllers do not transmit data for a certain period of time, to allow other phases
to complete their mode transitions. Table 3.1 summarizes all the possible scenarios for
different port values for each mode of operation. It shows the corresponding input and
output values for different values of comm_in, comm_out_internal, bus_mode, and
comm_out. A value of Z indicates high impedance and a value of X indicates an arbitrary
value. Cases which would require multiple phases to be transmitting data at the same time
are omitted, as this does not occur due to the design of the controllers.

comm_in comm_out_internal bus_mode comm_out
X Z 0 (series) Z
Z 0 0 (series) 0
Z 1 0 (series) 1
Z Z 1 (bus) Z
0 0 1 (bus) 0
1 1 1 (bus) 1
Table 3.1: Communication block inputs and outputs
The transmission gate is made up of two transistors in parallel: one NMOS transistor and one
PMOS transistor. In series mode, the bus_mode signal is set such that both transistors are in
their off states. When comm_in is driven to a certain value, it will have no effect on
comm_out, and vice-versa. On the other hand, in bus mode, the bus_mode signal is set to
turn on both transistors. In this case when comm_in is driven to a certain value, comm_out
will be driven to that value, and vice-versa. This occurs because these ports behave as if they
are shorted together during bus mode, which is the desired behaviour. In bus mode, a logic
value of 1 is sent to the gate of the NMOS transistor and a logic value of 0 is sent to the gate
of the PMOS transistor. The controllers have been designed such that multiple phases will
never attempt to transmit data simultaneously. As a result, during bus mode, there is no
concern with two phases fighting with each other to pull the bus to opposite strong values. In
bus mode, the transmission gate is capable of relaying high, low, and high-impedance
signals. Since PMOS transistors pass high values well but low values poorly, and NMOS
transistors pass high values poorly but low values well, a parallel combination of both is
used.
A tri-state buffer would not be an appropriate choice for replacing the transmission gate
because it is not capable of passing a high impedance signal. A tri-state buffer can output a
high impedance signal based on its control signal, but not based solely on its input signal.

Figure 3.6 compares series mode and bus mode operation. In this example there are four
phases, and thus four nodes (one node between phases 1 and 2, another between phases 2 and
3, and so on). In series mode, the transmission gate is turned off and signals do not pass from
one side to the other. In the example, Phase 1 sends a transmission, and Phase 2, the very
next phase in the ring, is the only phase that receives the transmission. In bus mode, the
transmission gates are turned on and the phases behave as if comm_in is shorted to comm_out
in each phase. In this case when Phase 1 transmits data, all other phases in the system
receive the transmission.

Figure 3.6: A comparison of series mode and bus mode with four phases

3.3.2 Phase Detector
The Phase Detector, present in each phases controller, is responsible for determining the
number of phases in the system. For multiphase operation, knowledge about the number of
phases is necessary for the timing required for interleaved operation, and to ensure that
proper communication occurs. The controller must also be capable of establishing whether
single phase operation should occur, if only one phase is present. The phase detection step is
the first process of the initialization procedure, occurring shortly after start-up.
During start-up, one of the phases is uniquely identified as the starting phase. The starting
phase is responsible for initializing the phase detection process. The other phases then
perform their respective tasks and the number of phases is determined.
3.3.2.1 Phase Detection Process
At the beginning of the phase detection process, the communication mode of all phases is set
to series mode. This is done so that each phase in the system can be uniquely counted, one
phase at a time. The phase detection process begins when the starting phase (identified using
one of the methods proposed in 3.3.2.2) transmits a value of 1 to the next phase in the ring.
Since series mode is used for communication at this point, only the next phase in the ring
receives this value. The next phase receives a value of 1, stores it in a register, increments it
to 2 and transmits this new value to the following phase. This process continues until the
starting phase receives a transmission from the final phase in the ring. The value received by
the starting phase corresponds to the total number of phases present in the system. After a

sufficient period of time, all phases switch the communication method into bus mode and the
initial phase transmits the number of phases across the bus. At this point, each phase reads
the number of phases and has previously recorded its own unique position in the ring. The
next segment in the initialization procedure, the LC Estimation and Sequencing step, may
now begin.
Note that the limitation of the communication block sending 4 bits of data during each
transmission restricts multiphase operation to 2
4
1 = 15 phases. However, the controllers
could be designed such that the Phase Detector sends and receives two or more transmissions
at each step, supporting a much greater number of phases. For example, with two data
transmissions, the maximum number of phases would be 2
8
1 = 255 (although practical
considerations, such as the physical area required for the power stages, would likely limit the
number of phases to a number far less than 255).
An example of the phase detection process is shown in Figure 3.7, for the case with four
phases. For the case where there is only one phase, that phases comm_in port is directly
connected to its own comm_out port. In this case, the phase will transmit a value of 1 and
will immediately receive this transmission through its comm_in port, indicating that no other
phases are present in the system. With only one phase the LC Estimation and Sequencing
and Digitally-Controlled DLL steps are unnecessary and therefore omitted. Regular
operation begins immediately after the Phase Detector recognizes that only a single phase is
present.

Figure 3.7: The phase detection process with four phases
3.3.2.2 Starting Phase Identification
A major challenge with this design is to ensure that exactly one phase begins the phase
counting procedure during start-up. If no phases begin the process, the system will fail to
start. On the other hand, if more than one phase begins, erroneous operation can occur. This
problem stems from the fact that all controllers are identical and are therefore expected to
behave in the exact same way. A solution is necessary that uniquely identifies one phase,
and only one phase, as the starting phase. One possible solution is to program one of the
phases as the starting phase. However, the process of programming all chips will result in an
increase in cost and extra pins may be required. Another solution would be to provide
unique master and slave controllers. In this case, each application would require one master
controller and as many slave controllers as necessary. However, this would require the
design of two distinct controllers. Also, the system would not be able to continue to operate

if the master chip were to fail. These drawbacks may be unacceptable for high volume
applications. Another approach is to rely on random behaviour to select one phase as the
initial phase. However, random behaviour may not be a desirable solution since there may
be a risk of a conflict, where two phases select themselves as the initial phase. These
conflicts must either be avoided or handled appropriately, which presents a further challenge.
Two solutions which address these issues are proposed.
The first solution is illustrated in Figure 3.8. The controllers and power stages are connected
and routed on a printed circuit board (PCB). One of the phases has its comm_in pin
connected to the output of a tri-state buffer. The tri-state buffer is enabled only when reset is
active. When the reset signal is activated, each phase immediately reads the value of its
comm_in port. The one phase that sees its comm_in port pulled low at the instant that reset is
activated will designate itself as the starting phase. Since only one phase has its comm_in
port connected to the reset signal as a result of the PCB layout, only that one phase will
designate itself as the starting phase. This allows the initial phase to be uniquely identified in
a simple fashion, based on its arrangement on the PCB. This method does not rely on
random behaviour or programmability, yet the goal of using identical controllers is achieved.

Figure 3.8: PCB routing for starting phase identification
An alternative solution is presented in Figure 3.9. In this case, the reset signal is connected
through a RC filter to one phase, and directly connected to the other phases. When the reset
signal is activated, the signal change propagates almost immediately to the phases with direct
connections to reset. However, for the phase connected to reset through the RC filter, the
signal change is delayed due to the time required to discharge the capacitance.

Figure 3.9: PCB routing for starting phase detection using a RC filter
As soon as a phase receives a reset signal, it checks whether its comm_in port has been pulled
low. If so, it designates itself as the starting phase. Otherwise, it is not the starting phase and
pulls its comm_out port low. In the example in Figure 3.9, the reset signal for the initial
phase (Phase 1) passes through a RC filter, causing a delay. The reset signal immediately
passes to the other phases, which pull down their respective comm_out ports. As a result, by
the time the reset signal reaches Phase 1, Phase 4 has already received the reset signal and
has pulled its comm_out port low. Phase 1 sees that its comm_in port (connected to the
comm_out port of Phase 4) has been pulled low and designates itself as the initial phase. An
example of waveforms for the reset procedure is shown in Figure 3.10 for a case with 4

phases. In this case Phase 1 is the starting phase. The RC filter produces a delay of t
d
in the
reset signal, causing Phase 1 to sample comm_out
4
after it has been pulled down.

Figure 3.10: Starting phase detection done with an RC filter
Either of these methods results in one phase being uniquely identified as the starting phase.
In both cases, the controllers of all phases are identical, but one phase has a slightly different
arrangement on the PCB. The advantage of the first method is that an RC filter is not
required, although it requires an external tri-state buffer. The tri-state buffer method would
be suitable for cases where external digital hardware already exists, such as in cases where a
supervising FPGA or microprocessor is employed. In cases where no digital hardware exists,
the simplicity of an RC filter would be advantageous.

3.3.3 LC Estimator and Sequencer
One of the primary advantages of multiphase operation in switch-mode power supplies is
ripple cancelation. In order to achieve this advantage, the phases must be interleaved,
meaning that the starting positions of the switching signals are evenly spaced over the course
of each switching cycle. By interleaving the phases, the rising slope of one inductors
current can coincide with the falling slope of another inductors current, thus reducing the
total ripple. However, variances in the inductance values among the phases can greatly
mitigate the effects of ripple cancelation, due to differences in the current slope. Due to non-
idealities in production, an inductance may vary from its nominal value [21]. The work
presented in [19] introduces a method of measuring the inductor current ripple in each
individual phase during start-up, and re-ordering the phases in such a way that the ripple is
minimized even in the presence of inductor non-idealities. The idea is to re-order the phases
such that phases with similar current ripples are switched 180 apart from each other. In this
way, similar variances in ripple between pairs of phases can cancel each other out, which
results in a reduction in total current ripple.
Reducing the output ripple in this manner introduces two requirements: the controller must
be able to place phases into an arbitrary sequence and it must be able to estimate and
compare the values of the inductors in all phases. The design of the Communication Block
allows the phases to be sequenced in any order because bus mode is employed after the phase
detection process is complete. During bus mode, the arrangement of the phases on the PCB
is no longer relevant and, as a result, the phases can be sequenced in any order. The

introduction of the LC Estimator and Sequencer allows the inductances to be estimated and
the phases to be placed in an arrangement that mitigates the total output ripple.
3.3.3.1 Charged-Based Inductance Estimation Method
The method presented in [19] allows the inductances of all phases in a multiphase converter
to be estimated. The method employs current sensors to measure the steady-state current
ripple contribution of each of the phases. The steady-state peak-to-peak current ripple
contribution from one phase can be found to be the following, using a low voltage ripple
approximation [22]:
i
pk-pk
=
1
s
(v
g
-v
cut
)
L
Equation 1
The steady-state peak-to-peak current ripple is defined as the difference between the
maximum and minimum values of a current waveform over the course of a switching period
during steady-state operation, when the input voltage source and output load have remained
constant for a sufficient period of time. Equation 1 indicates that the peak-to-peak current
ripple contribution of a phase is inversely proportional to its inductance. The method of [19]
measures the current ripple of each phase directly using current sensors during a start-up
procedure and places phases with similar inductance values 180 apart from each other. The
specification that is most important is the peak-to-peak output voltage ripple. However, the
voltage ripple directly depends on the current ripple, since the current ripple from the
inductors flows into the output capacitor, causing a proportional fluctuation in output voltage.

The size of the total output current ripple directly depends on the following conditions: the
number of phases, the inductance of each phase, the duty ratio, and the order of the phases.
Uneven current sharing among phases in a multiphase system does not affect the ripple. The
phase shift of each current waveform also affects the total current ripple, however, for this
analysis it is assumed that the phases are evenly shifted over the course of a switching cycle
(with n phases the phase shift is equal to 360/n). Uniform phase shifting is achieved with
the Digitally-Controlled DLL, described in 3.3.4.
Of the parameters that affect the total output current ripple, the order of the phases is the one
which is most feasible to vary. It would be possible to alter the ripple by varying the duty
ratio; however, the duty ratio is set by the compensator in order to achieve the desired output
voltage. The number of phases is selected for various reasons including cost and dc current
requirements. The inductances of all phases may not be equal due to manufacturing
dissimilarities, temperature, and aging. On the other hand, the design of the dual-mode
Communication Block allows the phases in a multiphase setup to be placed into any
sequence, thus making it feasible to vary the phase order dynamically.
An example showing the current ripple of a system with 6 phases is found in Figure 3.11. In
this case, all phases have the same inductance, and hence have identical steady-state current
ripples (1.0 A). The total or combined current ripple is the sum of the instantaneous
individual ripples since the inductors are connected in parallel. The ripples of all phases
nearly cancel each other out, resulting in a combined total ripple of only 0.33 A. This
demonstrates how multiphase operation can result in reduced output ripple. Figure 3.12, on
the other hand illustrates the case where 2 phases have different inductances than the other 4
phases. These 2 phases have smaller inductances, resulting in a larger phase current ripple of

2.0 A, compared to 1.0 A in the other phases. When these phases are placed adjacent to each
other in the switching sequence, a total current ripple of 3.22 A occurs. In Figure 3.13, the
phases have the same inductances and current ripples as in the case of Figure 3.12. However,
the 2 phases with smaller inductances have been placed 180 apart from each other in the
switching sequence. This results in a large reduction in total current ripple; the total current
ripple is now only 1.00 A. This illustrates how reordering the phases can result in a
significant improvement in the output ripple. Note that other factors also affect the size and
shape of the output ripple. For example, when the product of the duty ratio and the number
of phases is an integer and the inductances are equal, the ripple is completely eliminated
through cancellations.

Figure 3.11: Ripple cancelation for a 6-phase system with identical inductances
0 0.5 1 1.5 2
x 10
-6
-2
0
2
A
m
p
l
i
t
u
d
e

[
A
]
Time [s]
Individual Phase Waveforms

Phases with 1.0 A ripple
0 0.5 1 1.5 2
x 10
-6
-2
0
2
A
m
p
l
i
t
u
d
e

[
A
]
Time [s]
Waveform Sum

Total current ripple: 0.33 A

Figure 3.12: Combined ripple for a 6-phase system where 2 consecutive phases have similar inductance values,
mismatched with the other phases

Figure 3.13: Ripple cancelation in a 6-phase system with optimized phase sequencing
0 0.5 1 1.5 2
x 10
-6
-2
0
2
A
m
p
l
i
t
u
d
e

[
A
]
Time [s]

0 0.5 1 1.5 2
x 10
-6
-2
0
2
A
m
p
l
i
t
u
d
e

[
A
]
Time [s]
Waveform Sum

0 0.5 1 1.5 2
x 10
-6
-2
0
2
A
m
p
l
i
t
u
d
e

[
A
]
Time [s]

0 0.5 1 1.5 2
x 10
-6
-2
0
2
A
m
p
l
i
t
u
d
e

[
A
]
Time [s]
Waveform Sum


3.3.3.2 LC Estimator and Sequencer Architecture
The proposed method for mitigating the systems output ripple involves estimating the
inductance of each phase and subsequently reordering the phases to achieve a reduced ripple.
An algorithm for reordering phases similar to the one presented in [19] is employed here.
However, the method for estimating the inductance in each phase has been modified to work
without current sensors. The process involves each phase charging and discharging the
output capacitance before regular operation begins. During this process the charge times of
the phases are recorded and compared.
The load should not be connected during the LC product estimation process because the
output voltage is lower than the rated value. As a result, this process works under the
assumption that a Power-Good signal is present. This feature is quite common in many
practical applications, such as CPUs. For example, [2,23] employ a Power-Good signal.
During initialization, the phases each take turns independently charging the output capacitor,
while the switching signals of the other phases are disabled and the load is disconnected.
The phase that is currently active switches at a low duty ratio value and charges the output to
a value well below the rated value. This is accomplished by setting the switch S
2
such that
the ADC reference is set to V
ref1
, which is lower than the steady-state output voltage, V
ref2
, as
shown in Figure 3.2. A low duty ratio is used to avoid a large inrush current that could
potentially damage the power stage components. Once the specified output voltage is
reached, the output capacitor is discharged until no energy remains in the inductor and
capacitor. The time taken to charge the output capacitor to the specified value is measured,

and transmitted to the other phases, using the communication bus. The remaining phases
repeat this process one at a time, such that in the end, the charge times of all phases are
known. The phases perform this task in the order they were counted during the phase
detection process. Consequently, all phases implicitly know when they should begin the
process.
The corner frequency of the power stage of a single phase buck converter is defined as
follows:
c
=
1
LC
Equation 2
This frequency determines the system response speed of each phase operating individually.
For a given capacitance, a larger inductance will result in a larger charge time. In a
multiphase converter where only one phase is active, the corner frequency can be defined as
the following:
c
i
=
1
L
i
C
Equation 3
In this case, L
i
is the inductance of phase i. The output capacitance is shared and therefore
the same for all phases. For a fixed capacitance, the charge time depends only on the
inductance. As a result, a phase with a large inductance will result in a long charge time, and
this corresponds to a small steady-state current ripple contribution for that phase.
The LC estimation process is illustrated in Figure 3.14. Before beginning the LC Estimation
and Sequencing step, all controllers switch into bus mode to allow information to be shared
among all phases. Switch S
2
in each phase is set such that the ADC reference is set to V
ref1
,
which is below the rated output voltage reference, V
ref2
, as illustrated in Figure 3.2. The

starting phase begins the procedure by switching at a fixed duty ratio in open-loop while the
other phases wait. As soon as an output voltage of V
ref1
is reached, the starting phase stops
and discharges the output. The time taken to charge the output, in units of switching periods,
is recorded. The initial phase transmits this charge time to all other phases in the system, and
the other phases store the value in registers. Since only 4 bits of data are sent during each
transmission, multiple data transmissions are used in case the charge time may exceed 2
4

switching cycles. At this point the second phase repeats this process, and so on. When all
phases have finished, each phase has knowledge of its own charge time and the charge times
of all other phases. These charge times are now used to order the phases, minimizing the
total ripple.

Figure 3.14: The charging and discharging process for estimating the LC products
The phases each independently determine their order in the switching cycle. A flowchart of
the algorithm is shown in Figure 3.15. Each phase compares its own charge time to those of
the other phases, and counts the number of phases with small charge times, or larger
estimated inductances. To avoid a conflict arising from multiple phases having identical

estimated inductances, the ring order of each phase, found during the Phase Detection
process, is appended onto the charge times. This avoids the problem where multiple phases
place themselves in the same location of the switching sequence, which would lead to poor
interleaving, contradicting the purpose of the phase sequencing procedure. Each phase takes
the binary value corresponding to the number of phases with larger estimated inductances
appended with its ring order, and performs a circular bit shift on this value. The result of this
operation is a number ranging from 0 to (n 1), where n is the number of phases in the
system. This number corresponds to each phases order in the switching sequence. This has
the effect of placing phases with similar estimated inductance values 180 apart from each
other in the switching sequence. Note that if the number of phases is odd, two phases cannot
be placed 180 apart from each other; however, they will be placed approximately 180 apart.

Figure 3.15: Flowchart of the phase sequencing algorithm

Table 3.2 provides an example of phase reordering based on measured charge times. In this
example the first 2 phases in the ring have charge times of 10 switching cycles, the third
phase has a charge time of 5 cycles and the fourth phase has a charge time of 6 cycles.
Therefore, the first two phases have inductances that are larger than those of the last two
phases. Each phase counts the number of phases with smaller charge times compared to its
own charge time. In this example the first two phases would place themselves into the same
order. To resolve this issue, the charge times are appended with each phases position in the

ring (found during the Phase Detection process), and these values are used during the
comparisons. The charge time appended with the ring position is unique for all phases since
the ring positions are unique and, as a result, the resulting phase orders are unique. Each
phase then performs a circular bit shift operation on this value to determine its switching
sequence order. The circular bit shift operation was chosen because its digital hardware
implementation is very simple. This has the effect of placing phases with similar values
calculated in column 4 of
Table 3.2 opposite each other in the switching sequence. The result of this operation will be
unique for each phase and the values will range from 0 to (n 1). This operation also works
properly with an odd number of phases; unique phase orders ranging from 0 to (n 1) will
still be produced in these cases. Once the LC Estimation and Sequencing procedure is
complete, the Digitally-Controlled DLL step begins.
1. Phase ID 2. Charge Time
3. Charge
Time
Appended
with
Phase ID
4. Number of
Phases with
Smaller Charge
Times
5. Switching
Sequence Order
Decimal Binary Decimal Binary Binary Decimal Binary Decimal Binary
0 00 10 1010 1010-00 2 10 1 01
1 01 10 1010 1010-01 3 11 3 11
2 10 5 0101 0101-10 0 00 0 00
3 11 6 0110 0110-11 1 01 2 10

Table 3.2: An example of phase reordering based on charge times with 4 phases.
3.3.4 Digitally-Controlled DLL
The Digitally-Controlled DLL is used for timing the switching signals of the phases for
interleaved operation. In the proposed design, one of the phases is selected as the Timing

Phase. This phase is responsible for dictating the timing of the beginning of the switching
cycles of all other phases, such that the switching pulses of all phases are evenly spaced.
3.3.4.1 Selection of the Timing Phase
The timing operations for interleaved operation are centralized in one of the phases in order
to ensure that the switching signals are evenly spaced. If the timing procedure were to be
distributed among all phases, there could be small discrepancies in timing due to process
variation among the controllers. In other words, the switching signals would not necessarily
be evenly spaced over the course of a switching period. Although this would still result in
approximate ripple cancelation, undesirable harmonic noise could be produced.
Another advantage of using only one phase for timing is that an external reference clock is
not required. This reduces the pin requirements of the controllers. The only requirement is
an internally generated clock signal with a frequency equal to the desired switching
frequency.
In the proposed design, all controllers are identical and they are therefore all capable of
producing the timing signals necessary for interleaved operation. The selection of the Timing
Phase could be arbitrary; it does not matter which phase is selected as long as exactly one
phase is designated as the Timing Phase. In the proposed design, the first phase in the
switching sequence is selected.

3.3.4.2 Clock Generation Architecture
The purpose of the Digitally-Controlled DLL is to produce a clock signal with a frequency of
nf
s
for a system having n phases and a switching frequency of f
s
. A clock with a frequency of
nf
s
is required to evenly space the switching signals of all phases for interleaved operation.
Since the plug-and-play controllers are designed to function with an arbitrary number of
phases, the Digitally-Controlled DLL must be capable of producing clock signals of different
frequencies.
Table 3.3 lists the required output clock frequencies and periods of the Digitally-Controlled
DLL for a system operating at a switching frequency of 1 MHz (corresponding to a switching
period of 1s) with different quantities of phases.
n (number of phases) nf
s
(output frequency)[MHz] 1/(nf
s
) (output period) [ns]
2 2 500.00
3 3 333.33
4 4 250.00
5 5 200.00
6 6 166.67
7 7 142.86
8 8 125.00
9 9 111.11
10 10 100.00

Table 3.3: Required output frequencies and periods for a system operating at a switching frequency of 1 MHz
for various phase counts
The Digitally-Controlled DLL, shown in Figure 3.16, has two main components: a
Programmable Ring Oscillator and a Digital Frequency Compensator. The Digital
Frequency Compensator adjusts the inputs to the Programmable Ring Oscillator such that
the desired output clock frequency is achieved. The inputs to this module are n, a digital
value corresponding to the number of phases, and a clock with a frequency of f
s
. the

switching frequency. The outputs are a clock with a frequency of nf
s
and a signal indicating
when the correct output frequency has been achieved.

Figure 3.16: Digitally-Controlled DLL block diagram
The Programmable Ring Oscillator of Figure 3.16 consists of number of digitally
programmable delay cells arranged in a ring configuration and connected through 2-to-1
multiplexors. The delay cells are similar to the current-starved delay cells presented in [24].
A NAND-gate is also included in the ring for the inversion required to produce an oscillating
clock signal. The NAND-gate also allows the ring oscillator to be disabled, conserving
power when not needed. There are two methods of changing the output clock frequency: the
programmable delay cell control signals and the multiplexor inputs. Each programmable
delay cell has a digital control input that varies the propagation delay through the cell. The
multiplexors allow the number of programmable delay cells in the ring to be varied.
Depending on the multiplexor control signal, the previous delay cell can either be omitted or
included in the ring.

The Digital Frequency Compensator is responsible for adjusting the delay cell and
multiplexor control signals in order to achieve the desired output clock frequency. The
module compares the frequency of the output to that of the input by measuring the number of
output clock cycles over the course of a large number of input clock cycles. Using this
feedback, it iteratively adjusts the Programmable Ring Oscillator control signals to produce
an output clock with a frequency as close as possible to nf
s
. Although the controller cannot
lock to a frequency of exactly nf
s
due to the quantization of the control signals, it behaves in a
similar fashion to a standard analog delay-locked loop. However, its control is performed in
a completely digital fashion.
A flowchart presenting the operation of the Digital Frequency Compensator is shown in
Figure 3.17. The delay cell and multiplexor control signals are first set to a starting value.
Next, a counter is enabled that counts the number of cycles of the output clock, clk_out.
Simultaneously, a counter is enabled that counts the number of cycles of the input clock,
which has a frequency of f
s
. After a period of M input clock cycles, the counters are disabled
and there outputs are compared. If the output clock counter is greater than nM, where n is the
number of phases, the ring oscillator is too fast. In this case, the control signals are adjusted
such that the delay of the ring oscillator is increased. The counting process repeats itself
until the output clock counter is less than nM. The reverse occurs for the latter case. In this
way, the control signals are adjusted in an iterative manner until an output frequency close to
the desired value is achieved. At this point, the Locked output of the Digitally-Controlled
DLL is raised and regular operation of the system may now begin.
The range and resolution of the Digitally-Controlled DLL depend on a number of factors. A
larger number of multiplexors and Programmable Delay Cells with shorter delays will result

in a wider range of possible output frequencies. Also, adjusting the number of control
signals for the Programmable Delay Cells can increase the delay resolution and therefore can
allow the output frequency to be more closely matched to a frequency of nf
s
. It should be
noted that changing the specifications can result in different chip area and power
requirements, so a reasonable compromise should be chosen. Also, the Digitally-Controlled
DLL only needs to be capable of generating frequencies larger than 2f
s
since the input clock
is used for timing with a single phase.
In the prototype design, the Digitally-Controlled DLL begins locking the output clock signal
only after the LC Product Estimation and Sequencing step is complete. However, in order to
reduce the time required for the initialization process, the Digitally-Controlled DLL could be
activated simultaneously with the LC Product Estimation and Sequencing block, directly
after the Phase Detection process is complete (the correct frequency can only be produced
once the number of phases is known).

Figure 3.17: Flowchart of the operation of the Digital Frequency Compensator

3.3.5 Regular Operation
Once the phases have been counted and ordered, and the output of the Digitally-Controlled
DLL has locked to the correct frequency, regular operation begins. The regular operation of
the system involves two concurrent functions. The timing phase measures the output voltage
using its ADC and transmits the error signal across the bus at the appropriate instances. At
the same time, all the phases continuously monitor the bus to determine when they should
begin their switching actions. They read the error signals from the bus in order to calculate
and produce the correct duty ratios.
Shortly after the Digitally-Controlled DLL has locked to the correct frequency for clk_out,
the timing phase begins measuring the output voltage with its ADC. Then, it transmits this
error across the bus at the positive edge of the first clk_out cycle. At the next (n 1) positive
edges of clk_out, the timing phase transmits the same error. After n cycles, one switching
period has taken place, and the timing phase samples the error signal once again, and
transmits the new value onto the bus, and the process repeats. Since the error signal is
generated by the ADC of only one phase, mismatches in the ADCs among different phases
are not a concern. In the design, it is assumed that the error signals is 4 bits, so only one data
transmission is necessary.
After the LC Estimation and Sequencing step, all phases (including the timing phase) monitor
the bus to detect when regular operation should begin. It starts after the timing phase
executes its first data transmission, at which point the first phase in the series reads the error
value. The first phase sends this data to its compensator to produce the desired value for the

duty ratio sent to the DPWM, and first switching cycle begins. After the second data
transmission, the second phase does the same, and so on. After n transmissions, the first
phase begins its second switching cycle and this process repeats itself indefinitely. All
phases constantly monitor the bus, keeping count of the number of transmissions. Since each
phase has a unique order in the switching cycle, each transmission corresponds to the
beginning of only one phases switching cycle.
Figure 3.18 illustrates an example of regular operation with four phases. The output of the
Digitally-Controlled DLL for the timing phase is shown as clk_out(t). This clock has a
frequency of approximately 4f
s
. At each positive edge of this clock, the timing phase
transmits the error signal onto the bus, comm_out(t). Over the course of four transmissions,
all phases begin a new switching cycle. The switching signals of the four phases (outputted
by their corresponding DPWMs) are shown as c
i
(t). The period of each of these signals is f
s
,
the desired switching frequency of the system. Also, due to the timing of the data
transmissions, the switching signals are properly interleaved; they are evenly spaced apart
from each other by a time period of T
s
/4. From the time that the timing phase begins
transmitting an error signal until the corresponding phase begins its next switching cycle,
there is a small delay, t
d
. This delay is due to the fact that the data transmission and
computation takes a finite period of time. However, this delay is nearly the same for all
phases, so it does not affect the interleaving.

Figure 3.18: Waveforms during regular operation in steady-state

CHAPTER 4: EXPERIMENTAL VERIFICATION 56

Chapter 4
Experimental Verification and Results
4.1 Experimental Systems
Two experimental controllers were used to verify the functionality of the proposed design: a
large-scale FPGA-based prototype and a custom-built IC implementation. The systems are
described in the following sections.
4.1.1 FPGA-Based Implementation
The FPGA-based implementation consists of an Altera DE2 development board linked to a
PCB, with a plug-in interface allowing power stages to be easily added and removed, as
shown in Figure 4.1. All the controllers have been synthesized on a single FPGA chip.
However, each controller is identical and implemented in a separate module, ensuring that
masterless behaviour occurs. The Digitally-Controlled DLL (3.3.4) could not be fully
implemented on the FPGA system due to its need for analog hardware. In its place, a dual-

output DPWM was employed. In addition to producing standard PWM signals for the gate
drivers, the dual-output DPWM also supplies timing signals for dictating when the phases
should begin their switching cycles. These timing signals are set based on the number of
phases in the system, allowing for interleaved operation at a nearly constant frequency. The
FPGA-based system allowed quick synthesis of the system, such that the controller
prototypes could be tested.

Figure 4.1: FPGA-based prototype
4.1.2 IC Implementation
4.1.2.1 Chip Overview
The controller was implemented and fabricated on an integrated circuit (IC) using a 0.18m
CMOS process. This chip functions as a plug-and-play controller for one phase; in the case

of a multiphase system, multiple chips are placed into the ring configuration of Figure 3.1.
The IC demonstrates the feasibility of a practical implementation of the system.
Furthermore, several components were implemented on the IC that could not be easily
realized on a FPGA-based system. In Figure 4.2, a photograph of the die of the fabricated IC
is shown. Note that a portion of the chip area was used for another unrelated design. The
controller has been implemented within an area of approximately 1.2 mm
2
including its pads.
The specifications of the chip are summarized in Table 4.1. The PCB board layout and
schematic diagrams are provided in Appendix C.
A total of 27 pins were used in the IC implementation. However, most of these were used for
the purpose of programming and debugging, and thus would not be required for an industrial
implementation of the chip. Without the programming and debugging pins, and assuming
only one VDD and one VSS pin are required, the IC could potentially be implemented with
as few as 8 pins (VDD, VSS, reset, comm_in, comm_out, v_out, switch_HS, and
switch_LS), or even fewer if the power switches and gate drivers were to be integrated onto
the chip.
Certain functions on the chip were unfortunately not fully functional. Specifically, the
transmission gate failed to adequately pass the necessary current, resulting in slow rise and
fall times during communication in bus mode. As a result, the chip failed to function
properly with more than two phases. The chip does, however, demonstrate basic
functionality with one or two phases.

Figure 4.2: Die photograph of the fabricated IC
Specification Value
CMOS Technology 0.18 m
Chip Area (excluding pins) 0.35 mm
2

Pin Count (actively used) 27
Switching Frequency (f
s
) 500 kHz
DPWM Resolution 8 bits
Communication delay per bit 20 ns

Table 4.1: Chip specifications
4.1.2.2 On-Chip Components
A diagram of the chips layout and its main components is shown in Figure 4.3. The main
components are the Digital Controller, the Communication Block and Transmission Gate,
the DAC and ADC, and the Digitally-Controlled DLL. The chip area required for each of
these components is listed in
Table 4.2.
Component Chip Area [mm
2
]
Digital Controller 0.194
Communication Block and Transmission Gate 0.018
DAC and ADC 0.093
Digitally-Controlled DLL 0.041

Table 4.2: Chip area required by each component

Figure 4.3: Chip layout diagram
The Digital Controller was synthesized from Verilog HDL and the layout was realized using
a standard digital cell library. The Verilog HDL code is included in Appendix A. The
Digital Controller includes the Phase Detector (3.3.2), the LC Estimator and Sequencer
(3.3.3), the Digital Frequency Compensator for the Digitally-Controlled DLL block (3.3.4),
and the controller for regular operation (3.3.5). Also included is a Programmable Unit,
which allows various parameters, such as the compensator coefficients, to be programmed

onto each chip. In addition, the Programmable Unit allows information on the status of each
chip to be monitored. While not necessary for basic functionality, the Programmable Unit
was useful for analyzing and debugging the prototype chip. As a result, the chip has not been
optimized in order to reduce its area. On a commercial version of the chip, the area could be
reduced significantly by removing the unnecessary components and/or using a smaller
CMOS technology.
The Communication Block was implemented using a gate-level netlist of digital cells from a
standard cell library. The gate-level netlist is included in Appendix B. The transmitter and
receiver were implemented as shown in Figure 3.4 using delay cells.
The DAC and ADC from [25] are used on the chip. The purpose of the DAC is to supply a
reference voltage for the ADC. The reference voltage can be varied based on a digital input.
A programmable DAC was chosen because different voltage references are needed
depending on the stage of operation. During the LC estimation and sequencing stage, the
reference needs to be lower than the steady-state reference so that the output voltage is
charged to only a low value.
4.2 Experimental Results
The proposed system was verified using an experimental setup consisting of a PCB
supporting up to four power stages. The PCB was designed such that phases can be easily
added or removed from the system using a plug-in interface. Certain functions of the
controller have been verified with the IC implementation while others have been verified
with the FPGA-based implementation.

4.2.1 Single Phase Operation
Single phase operation with a plug-and-play controller is similar to operation with a non-
scalable single phase system, except that the controller must recognize that only a single
phase is present and respond appropriately.
Figure 4.4 shows the start-up procedure with a single phase using the IC. The input
communication signal, the output voltage, and the output PWM switching signal are shown.
With single phase operation, the communication signal sent from the controller is directly
linked to its communication input port, since only one controller is present in the ring
configuration.
The auto-configuration process begins with a reset signal being sent to the controller. The
reset signal is also connected to the controllers communication input through a tri-state
buffer. As a result, the controller is able to identify itself as the initial phase, using the first
starting phase detection procedure described in 3.3.2.2. Next the Phase Detection Process
begins (3.3.2.1), where a value of 1 is sent to the next phase in the ring. Since only one
phase exists, the value is immediately received at the communication input port of the
controller. As a result, the controller recognizes that it is the only phase in the system and
thus single phase operation should be performed, and the LC Product Estimation and
Sequencing and Digitally-Controlled DLL processes are omitted.
Single-phase, closed-loop operation begins immediately after the controller recognizes itself
as the only phase. An enlarged view of the steady-state closed-loop operation with a single
phase is shown in Figure 4.5.

Figure 4.4: Start-up procedure for single phase operation using the IC controller
Output voltage
PWM signal

Figure 4.5: Closed-loop steady-state single phase operation with the IC controller

4.2.2 Multiphase Operation
Operation with multiple phases has been fully verified using the FPGA-based system and
partially demonstrated using the IC-based controllers. In multiphase operation, the
controllers must identify the number of phases, optimize the phase sequence, and share
timing and error information for interleaving and voltage regulation.
Figure 4.6 presents the entire auto-configuration process with 4 phases using the FPGA
setup. First, the Phase Detection Process occurs, where the phases communicate with each
other as described in 3.3.2.1 to determine that 4 phases exist. Next, the LC Product
Estimation and Sequencing is performed, where each phase charges the output to a value
below the reference value. This information is used to sequence the phases in the optimal
order to minimize the output voltage ripple, as described in 3.3.3. The details and effect of
the sequencing process will be discussed in 4.2.3. Next, regular operation of the system
begins, where the controllers regulate the output voltage to the reference value and
sequenced, interleaved operation occurs.

Figure 4.6: Configuration and regular operation with 4 phases with the FPGA-based controller
The interleaved switching sequences in steady-state for various numbers of phases are shown
in Figure 4.7, Figure 4.8, Figure 4.9, and Figure 4.10. Open-loop operation with 2 phases
using the IC controller is shown in Figure 4.7. In this case, the switching signals of the 2
phases are interleaved approximately 180 apart from each other. In Figure 4.8, Figure 4.9,
and Figure 4.10, steady-state closed-loop operation is demonstrated with the FPGA-based
system for 2, 3, and 4 phases, respectively. Even interleaved operation is achieved, where
the switching signals are spaced 180, 120, and 90 apart from each other, respectively. In
each of these cases, approximately the same switching frequency is maintained.

Figure 4.7: Open-loop operation with 2 phases using IC controllers




4.2.3 Phase Sequencing
In this section the phase sequencing procedure is demonstrated and the effect of the
procedure is compared to the case where the phases are not optimally sequenced. As
described in 3.3.3, the order that the phases are sequenced in a multiphase system can have
an impact on the total output ripple due to mismatches in the inductor values.

Figure 4.11: One phase completes the charge process to estimate its LC product
The charge process for one phase is illustrated with the FPGA-based system in Figure 4.11.
In this figure, the phase enables its power stage with a fixed duty cycle and measures the time
it takes to charge the output to 0.4V, while the other phases are disabled. After this occurs,
the output voltage is discharged. The output is charged to a voltage well below the rated
output of 1.5V, such that the load does not enable itself.

Figure 4.12: The charge process for two phases with different inductance values
Figure 4.12 demonstrates the charge process for two phases having different inductance
values: one phase has an inductance of 0.5H and the other phase has an inductance of
1.0H. It can be seen that a significant difference in charge times exists, allowing for proper
phase sequencing to occur. As expected, a larger charge time corresponds to a larger
inductance. Also, the phases are charged one at a time so that the inductance of each phase
can be estimated individually. Figure 4.13 and Figure 4.14 show the steady-state AC current
ripples corresponding to these two phases. The phase with the 0.5H inductance has a
steady-state peak-to-peak current ripple contribution of 2.20A while the phase with the
1.0H inductance has a steady-state peak-to-peak current ripple contribution of 1.19A.
These current ripples were measured in a four phase system; however, they are the individual
current contributions for these phases. As expected, the phase with the larger inductance has
a larger charge time and a smaller peak-to-peak current ripple contribution.

Figure 4.13: The steady-state AC current ripple of the phase with a 0.5H inductor

Figure 4.14: The steady-state AC current ripple of the phase with a 1.0H inductor
The effect of using the information extracted during the LC product estimation procedure is
demonstrated for a four phase system in Figure 4.15 and Figure 4.16. In both cases, two of

the four phases have inductances of 0.5H while the other two phases have inductance of
1.0H. In Figure 4.15 and Figure 4.16, the total output current ripple is shown, whereas
Figure 4.13 and Figure 4.14 each show the ripple contribution from only a single phase.
Both cases result in a reduction in total current ripple, demonstrating one of the key
advantages of a multiphase system.
In Figure 4.15, the LC product estimation and phase sequencing algorithm has been disabled.
In this case, the phases are sequenced in their default order, which corresponds to the worst
case scenario where phases with similar inductance values are placed adjacent to each other
in the switching sequence. In this case, the magnitude of the total peak-to-peak current ripple
is 1.14A. This is only a minor improvement compared to the single phase case of Figure
4.14 due to the mismatch in inductor values.
In Figure 4.16, the phase order optimization has been implemented. In this case, phases with
similar inductance values are placed 180 apart from each other in the switching sequence.
This results in a total peak-to-peak current ripple of 0.69A, which represents a 39% reduction
compared to the case where the phase order optimization is disabled. This could allow for a
proportional reduction in the size of the output filter capacitor.
The shape of the voltage waveforms in Figure 4.12 does not have a perfectly quadratic shape,
as would be expected for a second-order system. The waveform appears to have a large
slope at the beginning of the charge process, followed by a reduced slope. This is likely
caused by non-linear behaviour of the output capacitor. The output capacitor may exhibit
different capacitance values at difference voltages, causing the waveform to be slightly
misshapen.

Figure 4.15: The steady-state total AC current ripple with unoptimized phase sequencing

Figure 4.16: The steady-state total AC current ripple with optimized phase sequencing


4.2.4 Communication Protocol
The communication block could not be fully implemented on the FPGA-based controller
because the FPGA only supports purely digital hardware. Also, it was not fully functional on
the IC-based controller due to problems related to the transmission gate and driving power.
As a result, simulations are provided illustrating the desired behaviour of the communication
block.
A simulation showing the functionality of the communication block is provided in Figure
4.17. The simulation was performed with a SPICE net list consisting of 8 communication
blocks in a ring configuration. The output of block 0 is connected to the input of block 1, the
output of block 1 is connected to the input of block 2, and so on. To complete the ring, the
output of block 7 is connected to the input of block 0. The simulation does not show realistic
behaviour with respect to the rest of the controller, but is rather meant to demonstrate the
general functionality of the communication block.
In the simulation of Figure 4.17, the 8 communication blocks take turns transmitting data.
From 0 ns to 900 ns, the communication protocol operates in series mode (since the BusMode
signal is low). During this period, data sent from each phase is only received by the very
next phase in the ring (only one comm_out signal is active at any time between 0 ns and 900
ns). Also, the data received (RXData) matches the data transmitted (TXData). The positive
edges of the ReceiveEnd signals indicate when each communication block has finished
receiving a transmission. At 900 ns, the communication blocks switch into bus mode, when
the BusMode signal becomes high. After 900 ns, data sent from any of the communication

blocks is received by all the other blocks. This is verified since all comm_out signals are
equal during this period, since the transmission gates have been closed. Also, all phases
receive the same data while in bus mode.

Figure 4.17: Simulation of 8 communication blocks arranged in a ring configuration
CHAPTER 5: CONCLUSIONS AND FUTURE WORK 76

Chapter 5

Conclusion
5.1 Thesis Summary and Contributions
A new architecture for plug-and-play controllers for scalable low-power SMPS has been
proposed in this work. The controllers operate in both single phase mode and multiphase
mode, with a variable number of phases. No central control is required for multiphase
operation as the control is performed masterlessly. The controllers are able to identify the
number of phases using an auto-configuration process during start-up. They are also capable
of sequencing themselves in an order that reduces the output ripple during interleaved
operation.
This auto-configuration allows the same controller design to be used in a wide variety of
applications requiring different quantities of phases. The simple communication interface

among the phases leads to a low pin count, allowing the architecture to be used as a cost-
effective solution in both single phase and multiphase applications.
The proposed design was verified using FPGA- and IC-based prototype systems. The
experimental systems successfully perform the auto-configuration process where the number
of phases is identified and the phases are placed into a sequence that minimizes the ripple.
Also, closed-loop, interleaved operation is achieved using the proposed communication
protocol. The system is also capable of operating at a fixed frequency with even interleaving
with various phase counts.
5.2 Future Work
The prototype system has been implemented and tested using voltage mode control.
However, its structure has been designed in such a way that it can be adapted for current-
programmed mode (CPM) control. CPM control can offer numerous advantages such as
simpler dynamics, inherent over-current protection, and equal current sharing in multiphase
converters.
In order to realize CPM control in multiphase systems, each controller must measure the
current contribution of its phase using a current sensor. CPM control can then be
implemented based on these measurements in addition to the output voltage measurement.
The information could be further used to achieve equal current sharing among the phases. In
a practical system without current feedback, the inductor currents among the phases will not
be equal due to parasitic elements and timing (i.e., one phase begins before the others during

start-up, resulting in a higher dc current in that phase). Also, equal current sharing prevents
phases from sinking current, which could severely degrade the systems overall efficiency.
In the described system, each plug-and-play controller could measure its current and share
the information with other phases in order to achieve CPM control, equal current sharing, and
over-current protection. The necessary modifications for each plug-and-play controller
would be the addition of a current sensor, the adaption of the compensator to support CPM
control, and modifying the controller to read and transmit current measurements over the bus,
in addition to output voltage measurements. An example of the data transmissions on the bus
with corresponding switching signals is shown in Figure 5.1 during steady-state for the case
of a multiphase system with 4 phases.

Figure 5.1: Current measurements being shared on the communication bus in CPM mode
Another possible extension to this work is the integration of an auto-tuning design into the
compensator for true plug-and-play support. These auto-tuning systems, described in 2.5,
could be used to dynamically adjust the compensators to achieve optimized dynamic
performance for power stages with varying parameters. This would achieve some of the
same advantages encountered with single phase auto-tuning controllers: power stage

parameters could be allowed to vary without requiring the compensator to be re-designed. In
a multiphase system, an auto-tuning controller could further compensate for variations in the
number of power stages. Without an auto-tuning controller, the compensators would likely
need to be reprogrammed for each different application. This process would lead to an
increase in cost. Also, pins would be required so that each controller could be programmed,
increasing the pin count of the controller.

APPENDIX A: VERILOG HDL FOR DIGITAL BLOCKS 80

Appendix A: Verilog HDL for Digital
Blocks
/*******************************************************************************************
/ Module: pap_digital_low
/ Written by: Jason Weinstein
/
/ Combines all modules operating at the low frequency clock
*******************************************************************************************/
module pap_digital_low (Reset, clk, ReceiveEnd, RXData, BusMode, BusModeNot,
is_initial_phase, ADCIn, MuxControl, DelayControl, ClkDLL, Error, VrefOut, EnableDPWM,
PhaseCount, PhaseOrder, DonePhaseSequence, DonePhaseCount, DPID, DLast, OpenLoop, DOpenLoop,
Discharge, ClkProgram, DataBus, DCharge, DebugRail, RingOscFreq, DeadTime, Transmit, TXData,
D, ADCSamplePhaseTimer, DAC_enable, DAC_freq, Prog_select, ADC_enable, Ring_osc_enable,
DLL_enable);

input Reset;
input clk;
input [3:0] RXData;
output BusMode;
output BusModeNot;
input is_initial_phase;
input [3:0] ADCIn;
output [6:0] MuxControl;
output [2:0] DelayControl;
input ClkDLL;
input [3:0] Error;
output [9:0] VrefOut;
output EnableDPWM;
output [3:0] PhaseCount;
output [3:0] PhaseOrder;
output DonePhaseCount;
output DonePhaseSequence;
output [15:0] DPID;
input [15:0] DLast;
output OpenLoop;
output [7:0] DOpenLoop;
output Discharge;
input ClkProgram;
input [7:0] DataBus;
output [7:0] DCharge;
output [3:0] DebugRail;
output [7:0] RingOscFreq;
output [7:0] DeadTime;
output Transmit;
output [3:0] TXData;
input [7:0] D;
output ADCSamplePhaseTimer;
input ReceiveEnd;
output DAC_enable;
output [2:0] DAC_freq;
input Prog_select;
output ADC_enable;
output Ring_osc_enable;
output DLL_enable;

assign BusModeNot = !BusMode;

wire PhaseEnabled;

wire InitialPhaseOverride;
wire InitialPhaseOverrideValue;
wire Start;
wire [3:0] TXDataPhaseCounter;
wire TransmitPhaseCounter;
wire EnableDPWMPhaseSequencer;
wire VoltageLevel;
wire ReOrderPhases;
wire [15:0] PhaseTimer;
wire PhaseOrderOverride;
wire [3:0] PhaseOrderOverrideValue;
wire TransmitPhaseSequencer;
wire [3:0] TXDataPhaseSequencer;
wire Locked;
wire MuxControlOverride;
wire DelayControlOverride;
wire [6:0] MuxControlOverrideValue;
wire [2:0] DelayControlOverrideValue;
wire [7:0] DeadTime;
wire [9:0] Vref0;
wire [9:0] Vref1;
wire HalfClock;
wire [15:0] LUT8; // These 9 entries are the values
for the PI look-up table
wire [15:0] LUT7; // There is a different value for
each error value:
wire [15:0] LUT6; // -4, -3, -2, -1, 0, +1, +2, +3,
+4
wire [15:0] LUT5;
wire [15:0] LUT4;
wire [15:0] LUT3;
wire [15:0] LUT2;
wire [15:0] LUT1;
wire [15:0] LUT0;
wire [3:0] TXDataPhaseTimer;
wire TransmitPhaseTimer;
wire ReceiveSync;
wire [3:0] SmallerPhases;
wire [3:0] PhaseID;

reg [9:0] VrefOutReg;
assign VrefOut = VrefOutReg;
reg EnableDPWMReg;
assign EnableDPWM = EnableDPWMReg;
reg TransmitReg;
assign Transmit = TransmitReg;
reg [3:0] TXDataReg;
assign TXData = TXDataReg;

// Phase counter
phase_counter PC (Reset, clk, ReceiveSync, RXData, TransmitPhaseCounter,
TXDataPhaseCounter, BusMode, is_initial_phase, PhaseID, PhaseCount, DonePhaseCount,
PhaseEnabled, InitialPhaseOverride, InitialPhaseOverrideValue, Start);
// Phase sequencer
phase_sequencer PS (Reset, clk, ReceiveSync, RXData, TransmitPhaseSequencer,
TXDataPhaseSequencer, PhaseID, PhaseCount, DonePhaseCount, EnableDPWMPhaseSequencer,
DonePhaseSequence, PhaseOrder, Discharge, VoltageLevel, ADCIn[3], ReOrderPhases, PhaseTimer,
PhaseOrderOverride, PhaseOrderOverrideValue, SmallerPhases);
// Digital DLL controller
digital_dll_controller DDC (Reset, clk, PhaseCount, Locked, MuxControl, DelayControl,
ClkDLL, DonePhaseSequence, PhaseOrder, MuxControlOverride, DelayControlOverride,
MuxControlOverrideValue, DelayControlOverrideValue);
// Phase timer
phase_timer PT (Reset, ClkDLL, PhaseCount, TXDataPhaseTimer, TransmitPhaseTimer,
Locked, ADCSamplePhaseTimer, ADCIn);
// PI compensator
pi_compensator PIC (DPID, DLast, Error, LUT0, LUT1, LUT2, LUT3, LUT4, LUT5, LUT6,
LUT7, LUT8, DeadTime);

// Programmable unit

programmable_unit PU (Reset, ClkProgram, DataBus, PhaseEnabled, ReOrderPhases,
InitialPhaseOverride, InitialPhaseOverrideValue, Start, Vref0, Vref1, OpenLoop,
PhaseOrderOverride, DOpenLoop, DeadTime, DCharge, LUT0, LUT1, LUT2, LUT3, LUT4, LUT5, LUT6,
LUT7, LUT8, PhaseOrderOverrideValue, MuxControlOverride, DelayControlOverride,
MuxControlOverrideValue, DelayControlOverrideValue, DebugRail, DonePhaseCount,
DonePhaseSequence, Locked, PhaseID, PhaseOrder, PhaseCount, PhaseTimer, is_initial_phase,
RingOscFreq, D, Error, DelayControl, DAC_enable, DAC_freq, SmallerPhases, Prog_select,
ADC_enable, Ring_osc_enable, DLL_enable);

// Voltage level sent to DAC
always @(VoltageLevel or Vref0 or Vref1)
begin
if (VoltageLevel == 1'b0)
begin
VrefOutReg = Vref0;
end
else
begin
VrefOutReg = Vref1;
end
end

// DPWM enable register
always @(DonePhaseSequence or DonePhaseCount or PhaseCount or
EnableDPWMPhaseSequencer)
begin
if ((DonePhaseSequence == 1'b1 | (DonePhaseCount == 1'b1 & PhaseCount ==
4'b1)))
begin
EnableDPWMReg = 1'b1;
end
else
begin
EnableDPWMReg = EnableDPWMPhaseSequencer;
end
end

// Transmitter registers
always @(DonePhaseSequence or TransmitPhaseTimer or DonePhaseCount or
TransmitPhaseSequencer or TransmitPhaseCounter or TXDataPhaseTimer or TXDataPhaseSequencer or
TXDataPhaseCounter)
begin
if (DonePhaseSequence == 1'b1)
begin
TransmitReg = TransmitPhaseTimer;
TXDataReg = TXDataPhaseTimer;
end
else if (DonePhaseCount == 1'b1)
begin
TransmitReg = TransmitPhaseSequencer;
TXDataReg = TXDataPhaseSequencer;
end
else
begin
TransmitReg = TransmitPhaseCounter;
TXDataReg = TXDataPhaseCounter;
end
end

// Receive synchronization

reg Q1;
reg Q2;
reg Q3;
wire Q3_and_Q1;

assign ReceiveSync = Q2;

always @(negedge Reset or posedge ReceiveEnd or posedge Q3_and_Q1)
begin
if (Reset == 1'b0)

begin
Q1 <= 1'b0;
end
else if (Q3_and_Q1 == 1'b1)
begin
Q1 <= 1'b0;
end
else
begin
Q1 <= 1'b1;
end
end

always @(negedge Reset or posedge clk)
begin
if (Reset == 1'b0)
begin
Q2 <= 1'b0;
end
else
begin
Q2 <= Q1;
end
end

begin
if (Reset == 1'b0)
begin
Q3 <= 1'b0;
end
else
begin
Q3 <= Q2;
end
end

assign Q3_and_Q1 = Q3 & Q1;

endmodule

/*******************************************************************************************
/ Module: pap_digital_high
/
/ Combines all modules operating at the high frequency clock
*******************************************************************************************/
module pap_digital_high (Reset, clk_256, clk, HSSwitch, LSSwitch, DeadTime, EnableDPWM,
Discharge, DonePhaseSequence, DonePhaseCount, PhaseCount, PhaseOrder, ReceiveEnd, RXData,
DPID, DLast, Error, ADCIn, OpenLoop, DOpenLoop, ADCSample, DCharge, DALow,
ADCSamplePhaseTimer);

input Reset;
input clk_256;
input clk;
output HSSwitch;
output LSSwitch;
input [7:0] DeadTime;
input EnableDPWM;
input Discharge;
input DonePhaseSequence;
input DonePhaseCount;
input [3:0] PhaseCount;
input [3:0] PhaseOrder;
input ReceiveEnd;
input [3:0] RXData;
input [15:0] DPID;
output [15:0] DLast;
output [3:0] Error;
input [3:0] ADCIn;
input OpenLoop;

input [7:0] DOpenLoop;
output ADCSample;
input [7:0] DCharge;
output [7:0] DALow;
input ADCSamplePhaseTimer;

wire [7:0] DOut;
wire DPWMStartRO;

reg [7:0] D;
assign DALow = D;
reg DPWMStartReg;
reg ADCSampleReg;
reg DPWMStartFinal;
reg ADCSampleFinal;
assign ADCSample = ADCSampleFinal;

// DPWM
dpwm DPWM (Reset, clk_256, DPWMStartFinal, HSSwitch, LSSwitch, DeadTime, D,
EnableDPWM, Discharge);
// Regular operation controller
reg_operation RO (Reset, clk_256, clk, DOut, DonePhaseSequence, DonePhaseCount,
PhaseCount, PhaseOrder, DPWMStartRO, ReceiveEnd, RXData, DPID, DLast, Error, ADCIn, OpenLoop,
DOpenLoop);

// Duty ratio register
always @(DonePhaseSequence or DonePhaseCount or PhaseCount or DOut or DCharge)
begin
if ((DonePhaseSequence == 1'b1 | (DonePhaseCount == 1'b1 & PhaseCount ==
4'b1)))
begin
D = DOut;
end
else
begin
D = DCharge;
end
end

// Synchronization across clock domains
always @(negedge Reset or posedge clk_256)
begin
if (Reset == 1'b0)
begin
ADCSampleReg <= 1'b0;
DPWMStartReg <= 1'b0;
end
else
begin
if (DonePhaseSequence == 1'b1)
begin
ADCSampleReg <= ADCSamplePhaseTimer;
DPWMStartReg <= DPWMStartRO;
end
else if ((DonePhaseCount == 1'b1 & PhaseCount == 4'b1))
begin
ADCSampleReg <= clk;
DPWMStartReg <= DPWMStartRO;
end
else
begin
ADCSampleReg <= clk;
DPWMStartReg <= clk;
end
end
end
begin
if (Reset == 1'b0)
begin
ADCSampleFinal <= 1'b0;

DPWMStartFinal <= 1'b0;
end
else
begin
ADCSampleFinal <= ADCSampleReg;
DPWMStartFinal <= DPWMStartReg;
end
end

endmodule

/*******************************************************************************************
/ Module: digital_dll_controller
/
/ This module adjusts the number of delay cells in the ring oscillator as well as the
/ programmable delay such that the output clock has a frequency of N x f_s, where N is
/ the number of phases.
*******************************************************************************************/
module digital_dll_controller(Reset, clk, PhaseCount, Locked, MuxControl, DelayControl,
ClkOut, DonePhaseSequence, PhaseOrder, MuxControlOverride, DelayControlOverride,
MuxControlOverrideValue, DelayControlOverrideValue);

input Reset; // Reset signal - active LO
input clk; // Main clock (1 MHz =
f_s)
input [3:0] PhaseCount; // The total number of phases
present in the system - can be sampled
//
once the phase count is complete
output Locked; // Indicates that the DLL has
"locked" at the appropriate frequency
output [6:0] MuxControl; // Indicates which delay cells should be
in the ring - used for coarse
//
frequency adjustments
output [2:0] DelayControl; // Input to all the programmable delay
cells - used for fine frequency
//
adjustments
input ClkOut; // DLL clock output
input DonePhaseSequence; // Goes high once the phase ordering
precedure is complete
input [3:0] PhaseOrder; // The order in the switching
sequence of this phase
input MuxControlOverride;
input DelayControlOverride;
input [6:0] MuxControlOverrideValue;
input [2:0] DelayControlOverrideValue;

reg [9:0] DLLState; // State variable for the main
DLL controller FSM
reg [6:0] MuxControlReg; // Register for storing MuxControl output
reg LockedReg; // Register for storing Locked
output
reg [2:0] DelayControlReg; // Register for storing DelayControl
output
reg [9:0] AuxCounter; // Auxiliary counter used for various
purposes
reg EnableCounter; // Used for enabling the counter
for measuring frequency
reg [9:0] Target; // Target number of oscillations
per 100 oscillations of clk
reg [9:0] TargetCounter; // For counting number of DLL output
oscillations
reg [3:0] TargetCounterState; // State variable for this counter
reg EnableCounterNoGlitch; // Glitch-free version of EnableCounter
reg EnableCounterInter; //
reg [2:0] DelayControlTemp; //

// Assign outputs to various registers

// More proper than using "output reg"
assign MuxControl = MuxControlReg;
assign Locked = LockedReg;

//
always @(DelayControlReg or DelayControlOverride or DelayControlOverrideValue)
begin
if (DelayControlOverride == 1'b1)
begin
DelayControlTemp = DelayControlOverrideValue;
end
else
begin
DelayControlTemp = DelayControlReg;
end
end
assign DelayControl = DelayControlTemp;

// Main digital DLL controller FSM
begin
if (Reset == 1'b0)
begin
DLLState <= 10'b0000000000;
LockedReg <= 1'b0;
DelayControlReg <= 3'b100;
AuxCounter <= 10'b0;
EnableCounter <= 1'b0;
end
else
begin
case (DLLState)
//////////////////////
// Initial state
//////////////////////
// Wait for phase sequencing to be done
// Also, only proceed if this is the first phase
10'b0000000000:
begin
LockedReg <= 1'b0;
if (DonePhaseSequence == 1'b1 & PhaseOrder == 4'b0000)
begin
DLLState <= 10'b0000000001;
end
else
begin
DLLState <= 10'b0000000000;
end
end
////////////////////////////////
// Do initial comparison
////////////////////////////////
// Wait 100 cycles
// Start with delay cell control variables in the middle
10'b0000000001:
begin
LockedReg <= 1'b0;
AuxCounter <= AuxCounter + 10'b1;
if (AuxCounter > 10'd100)
begin
DLLState <= 10'b0000000010;
end
else if (DelayControlOverride == 1'b1)
begin
DLLState <= 10'b1110000111;
end

else
begin
DLLState <= 10'b0000000001;
end
end
// Wait another cycle
10'b0000000010:
begin
LockedReg <= 1'b0;
DLLState <= 10'b0000000011;
end
// And another
10'b0000000011:
begin
LockedReg <= 1'b0;
DLLState <= 10'b0000000100;
end
// Check if target is too large or too small
10'b0000000100:
begin
LockedReg <= 1'b0;
if (TargetCounter >= Target)
begin
DLLState <= 10'b1000000000;
end
else
begin
DLLState <= 10'b1100000000;
end
end
////////////////////////
// Too fast
////////////////////////
// Reduce delay cell control variable by 1'b1
10'b1000000000:
begin
LockedReg <= 1'b0;
DelayControlReg <= DelayControlReg - 3'b1;
DLLState <= 10'b1000000001;
end
// Wait 100 cycles
10'b1000000001:
begin
LockedReg <= 1'b0;
DelayControlReg <= DelayControlReg;
begin
DLLState <= 10'b1000000010;
end
else
begin
DLLState <= 10'b1000000001;
end
end
// Wait one more cycle
10'b1000000010:
begin
LockedReg <= 1'b0;

DLLState <= 10'b1000000011;
end
// And another
10'b1000000011:
begin
LockedReg <= 1'b0;
DLLState <= 10'b1000000100;
end
// Check if target is met - if so we are done
// If control variable is 4'b0000, we are done - can't reduce
any more
// Otherwise, reduce by 1'b1 and go again
10'b1000000100:
begin
LockedReg <= 1'b0;
if (DelayControlReg == 3'b000 | TargetCounter < Target)
begin
DLLState <= 10'b1110000000;
end
else
begin
DLLState <= 10'b1000000000;
end
end
///////////////////////
// Too slow
///////////////////////
// Increase delay cell control variable by 1'b1
10'b1100000000:
begin
LockedReg <= 1'b0;
DelayControlReg <= DelayControlReg + 3'b1;
DLLState <= 10'b1100000001;
end
// Wait 100 cycles
10'b1100000001:
begin
LockedReg <= 1'b0;
begin
DLLState <= 10'b1100000010;
end
else
begin
DLLState <= 10'b1100000001;
end
end
10'b1100000010:
begin
LockedReg <= 1'b0;
DLLState <= 10'b1100000011;
end
// And another

10'b1100000011:
begin
LockedReg <= 1'b0;
DLLState <= 10'b1100000100;
end
// Check if target is met - if so we are done
// If control variable is 4'b1111, we are done - can't increase
any more
// Otherwise, increase by 1'b1 and go again
10'b1100000100:
begin
LockedReg <= 1'b0;
if (DelayControlReg == 3'b111 | TargetCounter >= Target)
begin
DLLState <= 10'b1110000000;
end
else
begin
DLLState <= 10'b1100000000;
end
end
//////////////////////
// All done
//////////////////////
//
10'b1110000111:
begin
LockedReg <= 1'b0;
begin
DLLState <= 10'b1110000000;
end
else
begin
DLLState <= 10'b1110000111;
end
end
// DLL output is "locked"
10'b1110000000:
begin
LockedReg <= 1'b1;
DLLState <= 10'b1110000000;
end
endcase
end
end

// Remove any glitches from counter enable register
// Used because we are dealing with two separate clock domains
begin
if (Reset == 1'b0)
begin
EnableCounterNoGlitch <= 1'b0;
EnableCounterInter <= 1'b0;
end
else
begin
EnableCounterNoGlitch <= EnableCounterInter;

EnableCounterInter <= EnableCounter;
end
end

// Coarse adjustments of DLL frequency and counter targets
// Depends on # of phases in the system
always @(PhaseCount or MuxControlOverride or MuxControlOverrideValue)
begin
if (MuxControlOverride == 1'b1)
begin
MuxControlReg = MuxControlOverrideValue;
Target = 10'd400;
end
else if (PhaseCount == 4'b0010)
begin
MuxControlReg = 7'b0000000;
Target = 10'd200;
end
begin
Target = 10'd300;
end
begin
Target = 10'd400;
end
begin
Target = 10'd500;
end
begin
Target = 10'd600;
end
begin
Target = 10'd700;
end
begin
Target = 10'd800;
end
else if (PhaseCount == 4'b1111) // Special
begin
Target = 10'd200;
end
else
begin
Target = 10'd200;
end
end

// Counter used for measuring oscillations at DLL output
always @(negedge Reset or posedge ClkOut)
begin
if (Reset == 1'b0)
begin
TargetCounterState <= 4'b0000;
TargetCounter <= 10'b0;
end
else
begin
case (TargetCounterState)

4'b0000:
begin
if (EnableCounterNoGlitch == 1'b1)
begin
TargetCounter <= 10'b0;
end
else
begin
TargetCounter <= TargetCounter;
end
end
4'b0001:
begin
TargetCounter <= TargetCounter + 10'b1;
if (EnableCounterNoGlitch == 1'b0)
begin
end
else
begin
end
end
endcase
end
end

endmodule

/*******************************************************************************************
/ Module: dpwm
/
/ Digital counter-based DPWM.
*******************************************************************************************/
module dpwm(Reset, clk_256, Start, HSSwitch, LSSwitch, DeadTime, D, Enable, Discharge);

input clk_256; // Input clock (256 MHz = 256f_s)
input Start; // Pulse indicating the start of
each switching cycle
output HSSwitch; // High-side switch
output LSSwitch; // Low-side switch
input [7:0] DeadTime; // Dead-time input
input [7:0] D; // Duty ratio
input Enable; // Indicates whether the DPWM is
enabled
input Discharge; // When Discharge == 1'b1, stage
is discharged

reg [3:0] DPWMState; // State variable for main DPWM FSM
reg [9:0] DPWMCount; // Counter used for DPWM
reg HSSwitchReg; // Register for storing HSSwitch
output
reg LSSwitchReg; // Register for storing LSSwitch
output
reg StartPulse; // Start pulse derived
from Start but using clk_256
reg [3:0] SPState; // Start pulse FSM state
reg [7:0] DReg; // Register for storing
duty ratio at each start pulse

// Override switching signals if we should discharge the power stage
assign HSSwitch = (HSSwitchReg | Discharge);
assign LSSwitch = (LSSwitchReg | Discharge);

// Main DPWM FSM
begin

if (Reset == 1'b0)
begin
DPWMState <= 4'b0000;
DPWMCount <= 10'b0;
HSSwitchReg <= 1'b1;
LSSwitchReg <= 1'b0;
DReg <= 8'b0;
end
else
begin
case (DPWMState)
// In this state DPWM is disabled
// Wait for Enable and StartPulse to rise
4'b0000:
begin
DPWMCount <= 10'b0;
if (StartPulse == 1'b1 & Enable == 1'b1)
begin
DReg <= D;
end
else
begin
DReg <= 8'b0;
end
end
// Initial dead time
4'b0001:
begin
if (Enable == 1'b0)
begin
DPWMCount <= 10'b0;
DReg <= 8'b0;
end
else if (StartPulse == 1'b1)
begin
DPWMCount <= 10'b0;
DReg <= D;
end
if (DPWMCount >= {2'b0, DeadTime[7:0]})
begin
DPWMCount <= DPWMCount + 10'b1;
DReg <= DReg;
end
else
begin
DReg <= DReg;
end
end
// Enable HSSwitch
4'b0010:
begin
if (Enable == 1'b0)
begin
DPWMCount <= 10'b0;
DReg <= 8'b0;
end

begin
DPWMCount <= 10'b0;
DReg <= D;
end
else if (DPWMCount >= {2'b0, DReg[7:0]})
begin
DReg <= DReg;
end
else
begin
DReg <= DReg;
end
end
// Middle dead time
4'b0011:
begin
if (Enable == 1'b0)
begin
DPWMCount <= 10'b0;
DReg <= 8'b0;
end
begin
DPWMCount <= 10'b0;
DReg <= D;
end
else if (DPWMCount >= {2'b0, DReg[7:0]} + {2'b0,
DeadTime[7:0]})
begin
DReg <= DReg;
end
else
begin
DReg <= DReg;
end
end
// Enable LSSwitch
4'b0100:
begin
DPWMCount <= 10'b0;
if (Enable == 1'b0)
begin
DReg <= 8'b0;
end
begin
DReg <= D;
end
else
begin
DReg <= DReg;
end
end

endcase
end
end

// Produces a pulse lasting a single cycle of clk_256 based on StartPulse input
begin
if (Reset == 1'b0)
begin
StartPulse <= 1'b0;
SPState <= 4'b0000;
end
else
begin
case (SPState)
4'b0000:
begin
if (Start == 1'b1)
begin
StartPulse <= 1'b1;
SPState <= 4'b0001;
end
else
begin
StartPulse <= 1'b0;
SPState <= 4'b0000;
end
end
4'b0001:
begin
StartPulse <= 1'b0;
if (Start == 1'b0)
begin
SPState <= 4'b0000;
end
else
begin
SPState <= 4'b0001;
end
end
endcase
end
end

endmodule

/*******************************************************************************************
/ Module: phase_counter
/
/ This module is responsible for determining the number of phases present in the system.
*******************************************************************************************/
module phase_counter(Reset, clk, ReceiveSync, RXData, TransmitOutNoGlitch, TXDataOut,
BusModeOut, is_initial_phase, PhaseIDOut, PhaseCountOut, DonePhaseCountOut, PhaseEnabled,
InitialPhaseOverride, InitialPhaseOverrideValue, Start);

input Reset; // Reset signal (active LO)
f_s)
input ReceiveSync; // From the communication block -
rising edge indicates that a
//
transmission has just been received
input [3:0] RXData; // Data received from last
transmission - should be sampled and
//
stored shortly after ReceiveSync goes high
output TransmitOutNoGlitch; // Output to communication block - rising
edge indicates that a
//
transmission should be sent

output [3:0] TXDataOut; // Output to communication block
(4 bits) - is sampled by the
//
communication block when TransmitOutNoGlitch goes high
output BusModeOut; // Indicates whether the
communication block should operate in
//
series mode (1'b0) or bus mode (1'b1)
input is_initial_phase; // Boolean value indicating
whether the phase is the initial phase:
// the
initial phase must begin by transmitting '1' to the next
//
phase even before it has received a transmission
output [3:0] PhaseIDOut; // The ID number of this phase - can be
sampled after the phase count
// has
completed
output [3:0] PhaseCountOut; // The total number of phases present in
the system - can be sampled
//
output DonePhaseCountOut; // Goes high once the phase counting
input PhaseEnabled; // If this signal is not high,
the phase is disabled
input InitialPhaseOverride; // If this value is one use
InitialPhaseOverrideValue instead of is_initial_phase
input InitialPhaseOverrideValue; // This value is used instead of
is_initial_phase if InitialPhaseOverrideValue is high
input Start; //

reg [9:0] PCState; // State variable for the main
phase counter FSM
reg BusModeReg; // Register for storing
the BusMode output
reg Transmit; // Register indicating a
transmission should begin
reg TransmitOut; // Glitch-free version of
Transmit
reg [3:0] TXData; // Data that should be
transmitted to the comm block
purposes at different
//
stages of the FSM
reg [3:0] PhaseID; // Register for storing the
phase's ID number
reg [3:0] PhaseCount; // Register for storing the total number
of phases
reg DonePhaseCount; // Goes high once the entire
phase counting process is complete
wire is_initial_phase_final; // Final value indicating initial phase

assign BusModeOut = BusModeReg;
assign TXDataOut = TXData;
assign PhaseIDOut = PhaseID;
assign PhaseCountOut = PhaseCount;
assign DonePhaseCountOut = DonePhaseCount;
assign TransmitOutNoGlitch = TransmitOut;

// See if is_initial_phase should be overrident
assign is_initial_phase_final = ((InitialPhaseOverride == 1'b1) ?
InitialPhaseOverrideValue : is_initial_phase);

// Used to remove glitches from Transmit signal
// The transmit signal must never glitch
// This delays the signal by one clock cycle but that's OK since this stage
// is not timing critical

begin
if (Reset == 1'b0)
begin
TransmitOut <= 1'b0;
end
else
begin
TransmitOut <= Transmit;
end
end

// Main phase counter FSM
begin
if (Reset == 1'b0)
begin
PCState <= 10'b0000000000;
BusModeReg <= 1'b0;
Transmit <= 1'b0;
TXData <= 4'b0;
AuxCounter <= 8'b0;
PhaseID <= 4'b0;
PhaseCount <= 4'b0;
DonePhaseCount <= 1'b0;
end
else
begin
case (PCState)
////////////////////
// Initialization
////////////////////
10'b0101010101:
begin
PhaseCount <= 4'b0;
BusModeReg <= 1'b0;
Transmit <= 1'b0;
TXData <= 4'b0;
PhaseID <= 4'b0;
AuxCounter <= 8'b0;
if (Start == 1'b1)
begin
PCState <= 10'b0000000000;
end
else
begin
PCState <= 10'b0101010101;
end
end
// Check if phase has been enabled (by programming unit)
10'b0000000000:
begin
PhaseCount <= 4'b0;
BusModeReg <= 1'b0;
Transmit <= 1'b0;
TXData <= 4'b0;
PhaseID <= 4'b0;
if (PhaseEnabled == 1'b0)
begin
PCState <= 10'b1111111111;
AuxCounter <= 8'b0;
end
else if (AuxCounter > 8'b00010000)
begin
PCState <= 10'b0000000001;
AuxCounter <= 8'b0;
end
else
begin

PCState <= 10'b0000000000;
end
end
// Check whether this phase is the initial phase
10'b0000000001:
begin
PhaseCount <= 4'b0;
BusModeReg <= 1'b0;
Transmit <= 1'b0;
AuxCounter <= 8'b0;
TXData <= 4'b0;
PhaseID <= 4'b0;
if (is_initial_phase_final == 1'b1)
begin
PCState <= 10'b1000000000;
end
else
begin
PCState <= 10'b0000000010;
end
end
///////////////////////
// Non-initial phases
///////////////////////
// Wait until we receive a transmission
10'b0000000010:
begin
PhaseCount <= 4'b0;
BusModeReg <= 1'b0;
Transmit <= 1'b0;
AuxCounter <= 8'b0;
TXData <= 4'b0;
PhaseID <= 4'b0;
if (ReceiveSync == 1'b1)
begin
PCState <= 10'b0000000011;
end
else
begin
PCState <= 10'b0000000010;
end
end
// Transmission has been received - store the value as the
Phase ID
10'b0000000011:
begin
PhaseCount <= 4'b0;
BusModeReg <= 1'b0;
PhaseID <= RXData;
Transmit <= 1'b0;
TXData <= RXData + 4'b1;
AuxCounter <= 8'b0;
PCState <= 10'b0000000100;
end
// Wait a few clock cycles
10'b0000000100:
begin
PhaseCount <= 4'b0;
BusModeReg <= 1'b0;
PhaseID <= PhaseID;
Transmit <= 1'b0;
TXData <= TXData;
if (AuxCounter > 8'b00001000)
begin
PCState <= 10'b0000000101;
AuxCounter <= 8'b0;

end
else
begin
PCState <= 10'b0000000100;

end
end
// Transmit PhaseID + 1'b1
10'b0000000101:
begin
PhaseCount <= 4'b0;
PhaseID <= PhaseID;
Transmit <= 1'b1;
BusModeReg <= 1'b0;
TXData <= TXData;
AuxCounter <= 8'b0;
PCState <= 10'b0000000110;
end
// Wait a few cycles
10'b0000000110:
begin
PhaseCount <= 4'b0;
PhaseID <= PhaseID;
Transmit <= 1'b0;
BusModeReg <= 1'b0;
TXData <= TXData;
begin
PCState <= 10'b0000000111;
AuxCounter <= 8'b0;
end
else
begin
PCState <= 10'b0000000110;
end
end
// Go into bus mode and wait for a transmission
10'b0000000111:
begin
PhaseID <= PhaseID;
Transmit <= 1'b0;
BusModeReg <= 1'b1;
TXData <= 4'b0;
AuxCounter <= 8'b0;
begin
PCState <= 10'b0000001000;
PhaseCount <= RXData;
end
else
begin
PCState <= 10'b0000000111;
PhaseCount <= 4'b0;
end
end
// Transmission received - non-initial phase finished
10'b0000001000:
begin
PhaseCount <= PhaseCount;
PhaseID <= PhaseID;
Transmit <= 1'b0;
BusModeReg <= 1'b1;
TXData <= 4'b0;
AuxCounter <= 8'b0;
PCState <= 10'b0000001000;

end
///////////////////////
// Initial phase
///////////////////////
// Wait a few clock cycles to make sure other phases are ready
10'b1000000000:
begin
PhaseCount <= 4'b0;
BusModeReg <= 1'b0;
Transmit <= 1'b0;
TXData <= 4'b1;
PhaseID <= 4'b0;
begin
PCState <= 10'b1000000001;
AuxCounter <= 8'b0;
end
else
begin
PCState <= 10'b1000000000;
end
end
// Transmit 1'b1 to the next phase
10'b1000000001:
begin
PhaseCount <= 4'b0;
BusModeReg <= 1'b0;
Transmit <= 1'b1;
TXData <= 4'b1;
PhaseID <= 4'b0;
AuxCounter <= 8'b0;
PCState <= 10'b1000000010;
end
// Check if we receive a transmission within the next couple
clock cycles
// If so this is the only phase in the system
10'b1000000010:
begin
BusModeReg <= 1'b0;
Transmit <= 1'b0;
PhaseID <= 4'b0;
TXData <= TXData;
begin
PhaseCount <= 4'b1;
PCState <= 10'b1100000000;
AuxCounter <= 8'b0;
end
else if (AuxCounter > 8'b00000010)
begin
PhaseCount <= 4'b0;
PCState <= 10'b1000000011;
AuxCounter <= 8'b0;
end
else
begin
PhaseCount <= 4'b0;
PCState <= 10'b1000000010;
end
end
// There are other phases
// Wait until a transmission is received from the last phase in
the ring
10'b1000000011:
begin
PhaseCount <= 4'b0;

BusModeReg <= 1'b0;
Transmit <= 1'b0;
PhaseID <= 4'b0;
TXData <= 4'b0;
AuxCounter <= 8'b0;
begin
PCState <= 10'b1000000101;
end
else
begin
PCState <= 10'b1000000011;
end
end
// Wait a few clock cycles so that all other phases are in bus
mode
10'b1000000101:
begin
PhaseCount <= RXData;
BusModeReg <= 1'b0;
Transmit <= 1'b0;
PhaseID <= 4'b0;
TXData <= RXData;
begin
PCState <= 10'b1000000110;
AuxCounter <= 8'b0;
end
else
begin
PCState <= 10'b1000000101;
end
end
// Set bus mode on
10'b1000000110:
begin
BusModeReg <= 1'b1;
Transmit <= 1'b0;
PhaseID <= 4'b0;
TXData <= TXData;
AuxCounter <= 8'b0;
PCState <= 10'b1000000111;
end
// Send # of phases on bus
10'b1000000111:
begin
BusModeReg <= 1'b1;
Transmit <= 1'b1;
PhaseID <= 4'b0;
TXData <= TXData;
AuxCounter <= 8'b0;
PCState <= 10'b1000001000;
end
10'b1000001000:
begin
BusModeReg <= 1'b1;
Transmit <= 1'b0;
PhaseID <= 4'b0;
TXData <= TXData;
AuxCounter <= 8'b0;
PCState <= 10'b1100000000;

end
// Initial phase finished
10'b1100000000:
begin
BusModeReg <= 1'b1;
Transmit <= 1'b0;
PhaseID <= 4'b0;
TXData <= 4'b0;
AuxCounter <= 8'b0;
PCState <= 10'b1100000000;
end
///////////////////////
// Phase is disabled
///////////////////////
// Stay here forever if disabled
10'b1111111111:
begin
PhaseCount <= 4'b0;
BusModeReg <= 1'b1;
Transmit <= 1'b0;
PhaseID <= 4'b0;
TXData <= 4'b0;
AuxCounter <= 8'b0;
PCState <= 10'b1111111111;
end
endcase
end
end

endmodule

/******************************************************************************************
/ Module: phase_sequencer
/
/ This module measures the charge time with a fixed duty ratio, transmits the charge time,
/ receives charge times from other phases, and then computes phase order.
*******************************************************************************************/
module phase_sequencer(Reset, clk, ReceiveSync, RXData, TransmitOutNoGlitch, TXDataOut,
PhaseID, PhaseCount, DonePhaseCount, EnableDPWM, DonePhaseSequence, PhaseOrder, Discharge,
VoltageLevel, ADCIn_3, ReOrderPhases, PhaseTimer, PhaseOrderOverride,
PhaseOrderOverrideValue, SmallerPhasesOut);

f_s)
input ReceiveSync; // From the communication block -
rising edge indicates that a
//
transmission has just been received
input [3:0] RXData; // Data received from last
transmission - should be sampled and
//
stored shortly after ReceiveSync goes high
output TransmitOutNoGlitch; // Output to communication block - rising
edge indicates that a
//
output [3:0] TXDataOut; // Output to communication block
(4 bits) - is sampled by the
//
communication block when TransmitOutNoGlitch goes high
input [3:0] PhaseID; // Phase ID number of this phase - can be
sampled once phase
//
counting process is finished

//
input DonePhaseCount; // Goes high once the phase counting
output EnableDPWM; // Indicates that DPWM should be
enabled - set high when the charging
//
process occurs
output DonePhaseSequence; // Goes high once the phase ordering
output [3:0] PhaseOrder; // The order in the switching sequence of
this phase
output Discharge; // Sent to the DPWM to discharge
output before charge process begins
output VoltageLevel; // During phase sequencing step,
indicates that a lower reference
//
voltage should be used for the ADC
input ADCIn_3; // MSB of ADC output - when this
value is zero, the ADC measurement is
// >=
to the reference - stop charging at this point and measure
// the
charge time
input ReOrderPhases; // When ReOrderPhases == 1'b1, do phase
reordering as usual - otherwise
//
just set PhaseOrder = PhaseID and finish
output [15:0] PhaseTimer; //
input PhaseOrderOverride;
input [3:0] PhaseOrderOverrideValue; //
output [3:0] SmallerPhasesOut; //

reg [9:0] PSState; // State variable for the main
phase sequencing FSM
reg Transmit; // Register indicating a
transmission should begin
reg TransmitOut; // Glitch-free version of
Transmit
reg [3:0] CurrentCount; // Counter for keeping track of
which phase should currently be performing
// the
charge process
reg EnableDPWMReg; // Register for storing
EnableDPWM output
reg DonePhaseSequenceReg; // Register for storing DonePhaseSequence
output
reg [3:0] PhaseOrderReg; // Register for storing PhaseOrder output
purposes during the phase sequencing
// process
reg DischargeReg; // Register for storing Discharge
output
reg VoltageLevelReg; // Register for storing VoltageLevel
output
reg [15:0] PhaseTiming [15:0]; // Register for storing the charge times
of all phases
reg [3:0] TXData; // Data that should be
transmitted to the comm block
reg [3:0] SmallerPhases; // For counting the number of phases that
have smaller charge times
//
than this phase - info used for phase reordering
reg [1:0] BitShift; // Depending on the total number
of phases, the algorithm should shift
// by
a different number of bits
reg [19:0] CompA; // These registers are for
performing comparisons
reg [19:0] CompB;


assign TransmitOutNoGlitch = TransmitOut;
assign EnableDPWM = EnableDPWMReg;
assign DonePhaseSequence = DonePhaseSequenceReg;
assign PhaseOrder = PhaseOrderReg;
assign Discharge = DischargeReg;
assign VoltageLevel = VoltageLevelReg;
assign TXDataOut = TXData;
assign PhaseTimer = PhaseTiming[PhaseID];
assign SmallerPhasesOut = SmallerPhases;

// Used to remove glitches from Transmit signal
// The transmit signal must never glitch
// This delays the signal by one clock cycle but that's OK since this stage
// is not timing critical
begin
if (Reset == 1'b0)
begin
TransmitOut <= 1'b0;
end
else
begin
TransmitOut <= Transmit;
end
end

// Main phase sequencing FSM
begin
if (Reset == 1'b0)
begin
PSState <= 10'b0000000000;
Transmit <= 1'b0;
CurrentCount <= 4'b0;
EnableDPWMReg <= 1'b0;
DonePhaseSequenceReg <= 1'b0;
PhaseOrderReg <= 4'b0;
DischargeReg <= 1'b0;
VoltageLevelReg <= 1'b1;
TXData <= 4'b0;
SmallerPhases <= 4'b0;
end
else
begin
case (PSState)
///////////////////////////
// Initial state
///////////////////////////
// Wait until phase counting is complete
10'b0000000000:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
if ((DonePhaseCount == 1'b1) & (PhaseCount > 1'b1))
begin
PSState <= 10'b0000000001;
end
else
begin
PSState <= 10'b0000000000;
end

end
/////////////////////////////////////////////////////////
// Branch depending on whether it is this phase's turn
/////////////////////////////////////////////////////////
// Check whether this phase should do the charge process, wait
// for another phase, or we are finished
10'b0000000001:
begin
Transmit <= 1'b0;
CurrentCount <= CurrentCount;
TXData <= 4'b0;
// Don't reorder phases - set PhaseOrderReg to PhaseID
and go to final state
if (ReOrderPhases == 1'b0)
begin
PhaseOrderReg <= PhaseID;
PSState <= 10'b1111111111;
end
else if (PhaseOrderOverride == 1'b1)
begin
PhaseOrderReg <= PhaseOrderOverrideValue;
PSState <= 10'b1111111111;
end
// Do charge process
else if (PhaseID == CurrentCount)
begin
PSState <= 10'b1000000000;
end
// Done all charge processes - go to stage for
calculating phase order
else if (PhaseCount == CurrentCount)
begin
PSState <= 10'b1110000000;
end
// Wait for another phase to do the charge process
else
begin
PSState <= 10'b1100000000;
end
end
//////////////////////////
// This phase's turn
//////////////////////////
// Discharge for a while before starting
10'b1000000000:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
begin
PSState <= 10'b1000000001;
end
else
begin
PSState <= 10'b1000000000;
end

end
// Start charging
10'b1000000001:
begin
Transmit <= 1'b0;
PSState <= 10'b1000000010;
TXData <= 4'b0;
end
// Wait for ADC output to be >= 0
// This occurs when the MSB of ADCIn is 1'b0
10'b1000000010:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
if (ADCIn_3 == 1'b1)
begin
PSState <= 10'b1000000011;
end
else
begin
PSState <= 10'b1000000010;
end
end
// Record charge time
10'b1000000011:
begin
Transmit <= 1'b0;
AuxCounter <= 20'd0;
PhaseTiming[PhaseID][15:0] <= AuxCounter[15:0];
TXData <= AuxCounter[3:0];
PSState <= 10'b1000000100;
end
// Transmit first 4 bits
10'b1000000100:
begin
Transmit <= 1'b1;
TXData <= TXData;
if (AuxCounter == 20'b1)
begin
PSState <= 10'b1000010100;
end
else
begin
PSState <= 10'b1000000100;

end
end
// Prepare transmission for bits 7:4
10'b1000010100:
begin
Transmit <= 1'b0;
begin
PSState <= 10'b1000000101;
TXData <= PhaseTiming[PhaseID][7:4];
end
else
begin
PSState <= 10'b1000010100;
TXData <= TXData;
end
end
// Transmit bits 7:4
10'b1000000101:
begin
Transmit <= 1'b1;
TXData <= TXData;
PSState <= 10'b1000000110;
end
10'b1000000110:
begin
Transmit <= 1'b0;
begin
PSState <= 10'b1000000111;
end
else
begin
PSState <= 10'b1000000110;
TXData <= TXData;
end
end
10'b1000000111:
begin
Transmit <= 1'b1;

TXData <= TXData;
begin
PSState <= 10'b1000001000;
end
else
begin
PSState <= 10'b1000000111;
end
end
10'b1000001000:
begin
Transmit <= 1'b0;
begin
PSState <= 10'b1000001001;
end
else
begin
PSState <= 10'b1000001000;
TXData <= TXData;
end
end
10'b1000001001:
begin
Transmit <= 1'b1;
TXData <= TXData;
begin
CurrentCount <= CurrentCount + 4'b1;
PSState <= 10'b1000001010;
end
else
begin
PSState <= 10'b1000001001;
end
end
// Wait a few cycles
10'b1000001010:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
begin
PSState <= 10'b0000000001;

end
else
begin
PSState <= 10'b1000001010;
end
end
/////////////////////////////
// Other phase's turn
/////////////////////////////
// Wait for transmission of bits 3:0
10'b1100000000:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
begin
PSState <= 10'b1100000001;
PhaseTiming[CurrentCount][3:0] <= RXData[3:0];
end
else
begin
PSState <= 10'b1100000000;
end
end
// Prepare for transmission of bits 7:4
10'b1100000001:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
begin
PSState <= 10'b1100000010;
end
else
begin
PSState <= 10'b1100000001;
end
end
10'b1100000010:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
begin
PSState <= 10'b1100000011;
end
else
begin

PSState <= 10'b1100000010;
end
end
10'b1100000011:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
begin
PSState <= 10'b1100000100;
end
else
begin
PSState <= 10'b1100000011;
end
end
10'b1100000100:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
begin
PSState <= 10'b1100000101;
end
else
begin
PSState <= 10'b1100000100;
end
end
10'b1100000101:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
begin
PSState <= 10'b1100000110;
end
else
begin
PSState <= 10'b1100000101;
end
end
10'b1100000110:
begin
Transmit <= 1'b0;

TXData <= 4'b0;
begin
PSState <= 10'b1100000111;
end
else
begin
PSState <= 10'b1100000110;
end
end
// Wait for ReceiveSync to go LO
10'b1100000111:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
begin
PSState <= 10'b1100001000;
end
else
begin
PSState <= 10'b1100000111;
end
end
// Go back to branching state
10'b1100001000:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
PSState <= 10'b0000000001;
end

//////////////////////////////////////////////////////////////////
// Each phase calculates its position in the switching cycle

//////////////////////////////////////////////////////////////////
// Wait one cycle
10'b1110000000:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
SmallerPhases <= 4'b0;

PSState <= 10'b1110000001;
end
// Determine # of phases that have smaller charge times
10'b1110000001:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
SmallerPhases <= SmallerPhases;
if (CurrentCount >= PhaseCount)
begin
PSState <= 10'b1110000010;
end
else
begin
CompA <= {PhaseTiming[PhaseID][15:0],
PhaseID[3:0]};
CompB <= {PhaseTiming[CurrentCount][15:0],
CurrentCount[3:0]};
PSState <= 10'b1110010001;
end
end
// Do actual comparison in this state
10'b1110010001:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
PSState <= 10'b1110000001;
if (CompA > CompB)
begin
SmallerPhases <= SmallerPhases + 4'b1;
end
else
begin
end
end
// Shift according to total number of phases to determine order
10'b1110000010:
begin
Transmit <= 1'b0;
TXData <= 4'b0;
if (ReOrderPhases == 1'b0)
begin
PhaseOrderReg <= PhaseID;
end
else if (BitShift == 2'b11)
begin
PhaseOrderReg <= {SmallerPhases[0],
SmallerPhases[3:1]};

end
begin
PhaseOrderReg <= {1'b0, SmallerPhases[0],
SmallerPhases[2:1]};
end
begin
PhaseOrderReg <= {2'b00, SmallerPhases[0],
SmallerPhases[1]};
end
else
begin
PhaseOrderReg <= {3'b000, SmallerPhases[0]};
end
PSState <= 10'b1111111111;
end
///////////////////
// All done
///////////////////
// Stay in this state forever - we are all done
10'b1111111111:
begin
Transmit <= 1'b0;
PhaseOrderReg <= PhaseOrderReg;
TXData <= 4'b0;
PSState <= 10'b1111111111;
end

endcase
end
end

// Calculates BitShift based on total number of phases
always @(PhaseCount)
begin
if (PhaseCount > 4'b1000)
begin
BitShift = 2'b11;
end
else if (PhaseCount > 4'b0100)
begin
BitShift = 2'b10;
end
else if (PhaseCount > 4'b0010)
begin
BitShift = 2'b01;
end
else
begin
BitShift = 2'b00;
end
end

endmodule

/*******************************************************************************************
/ Module: phase_timer
/
/ This module waits for the DLL to lock and then measures and transmits errors on the bus
/ for the timing of all the phases.
*******************************************************************************************/
module phase_timer(Reset, clk_dll, PhaseCount, TXData, Transmit, Locked, ADCSample, ADCIn);


input clk_dll; // DLL clock - approximately
N*f_s where N is the number of phases
//
output [3:0] TXData; // Output to communication block (4 bits)
output Transmit; // Output to communication block
- rising edge indicates that a
//
input Locked; // Goes high when DLL is "locked"
output ADCSample; // Positive edge sent to ADC to
start ADC measurement and sampling process
input [3:0] ADCIn; // ADC value

reg [9:0] PTState; // State variable for main phase
timer FSM
reg [3:0] CurrentCount; // For keeping track of the
currently active phase
reg ADCSampleReg; // Register for storing ADCSample
output
reg [3:0] TXDataReg; // Register for storing TXData output
reg TransmitEnable; // For controlling when this
module is active
reg [3:0] TXDataOut; // Register for storing TXData output
(sampled at negative clock edge)
reg [2:0] LockedMetastable; // Metastable version of Locked input

assign ADCSample = ADCSampleReg;
assign TXData = TXDataOut;

// Only transmit when TransmitEnable is high
assign Transmit = clk_dll & TransmitEnable;

// Metastabilize Locked input
always @(negedge Reset or posedge clk_dll)
begin
if (Reset == 1'b0)
begin
LockedMetastable <= 3'b0;
end
else
begin
LockedMetastable[0] <= Locked;
LockedMetastable[1] <= LockedMetastable[0];
LockedMetastable[2] <= LockedMetastable[1];
end
end

// Main phase timer FSM
always @(negedge Reset or posedge clk_dll)
begin
if (Reset == 1'b0)
begin
PTState <= 10'b0000000000;
TXDataReg <= 4'b0;
TransmitEnable <= 1'b0;
end
else
begin
case (PTState)
// Initial state
// Wait for DLL to lock - this will only happen if this state
has PhaseOrder 4'b0000
// (no need to check this again here)

10'b0000000000:
begin
TXDataReg <= 4'b0;
if (LockedMetastable[2] == 1'b1)
begin
PTState <= 10'b0000000001;
end
else
begin
PTState <= 10'b0000000000;
end
end
// Obtain initial sample of ADC
10'b0000000001:
begin
TXDataReg <= 4'b0;
PTState <= 10'b0000000010;
end
// Wait a few cycles to make sure first ADC sample is ready
10'b0000000010:
begin
TXDataReg <= ADCIn;
if (CurrentCount >= (PhaseCount - 4'b1))
begin
PTState <= 10'b0000000011;
end
else
begin
PTState <= 10'b0000000010;
end
end
// Steady state
10'b0000000011:
begin
if (CurrentCount == 4'b0)
begin
end
else
begin
end
if (CurrentCount == (PhaseCount - 4'd1))
begin
TXDataReg <= ADCIn;
end
else
begin
TXDataReg <= TXDataReg;
end
if (CurrentCount == (PhaseCount - 4'b1))
begin
end
else
begin
end
PTState <= 10'b0000000011;
end

endcase
end
end

// Sample TXDataReg at negative edge of the clock to satisfy both setup and hold times
always @(negedge Reset or negedge clk_dll)
begin
if (Reset == 1'b0)
begin
TXDataOut <= 4'b0;
end
else
begin
TXDataOut <= TXDataReg;
end
end

endmodule

/*******************************************************************************************
/ Module: pi_compensator
/
/ Basic PI compensator with output saturation.
*******************************************************************************************/
module pi_compensator(DOut, DLast, Error, LUT0, LUT1, LUT2, LUT3, LUT4, LUT5, LUT6, LUT7,
LUT8, DeadTime);

output signed [15:0] DOut; // Duty ratio output
input signed [15:0] DLast; // Previous duty ratio
input [3:0] Error; // Error value
input signed [15:0] LUT8; // These 9 entries are the
values for the PI look-up table
input signed [15:0] LUT7; // There is a different
value for each error value:
input signed [15:0] LUT6; // -4, -3,
-2, -1, 0, +1, +2, +3, +4
input signed [15:0] LUT5;
input [7:0] DeadTime;

// Note: all numbers in this block have 6 binary digits to the right of the decimal
point and 10 binary
// digits to the left (for a total of 16 digits).

// Registers and wires
reg signed [15:0] EA;
wire signed [15:0] DUnsaturated;
reg signed [15:0] DSaturated;
wire [14:0] min_d_shifted;
wire [14:0] max_d_shifted;

// Minimum and maximum duty ratios
assign max_d_shifted = 14'd16000;
assign min_d_shifted = {1'b0, DeadTime, 6'b0} + 14'd128;

// Calculate unsaturated duty ratio
assign DUnsaturated = DLast + EA;

// Set output duty ratio to appropriate bits of DSaturated
assign DOut = DSaturated;

// Saturate duty ratio
always @(DUnsaturated or max_d_shifted or min_d_shifted)
begin
if (DUnsaturated[15] == 1'b0)
begin

if (DUnsaturated[14:0] >= max_d_shifted)
begin
DSaturated[15] = 1'b0;
DSaturated[14:0] = max_d_shifted;
end
else if (DUnsaturated[15:0] <= min_d_shifted)
begin
DSaturated[14:0] = min_d_shifted;
end
else
begin
DSaturated = DUnsaturated;
end
end
else
begin
DSaturated[14:0] = min_d_shifted;
end
end

// Calculate A*Error (look-up table)
always @(Error or LUT0 or LUT1 or LUT2 or LUT3 or LUT4 or LUT5 or LUT6 or LUT7 or
LUT8)
begin
case (Error)
// +4
4'b0100:
begin
EA = LUT8;
end
// +3
4'b0011:
begin
EA = LUT7;
end
// +2
4'b0010:
begin
EA = LUT6;
end
// +1
4'b0001:
begin
EA = LUT5;
end
// 0
4'b0000:
begin
EA = LUT4;
end
// -1
4'b1111:
begin
EA = LUT3;
end
// -2
4'b1110:
begin
EA = LUT2;
end
// -3
4'b1101:
begin
EA = LUT1;
end
// -4
4'b1100:
begin
EA = LUT0;

end
// Default
default:
begin
EA = LUT4;
end
endcase
end

endmodule

/*******************************************************************************************
/ Module: programmable_unit
/
/ Programs various values onto the prototype chip
*******************************************************************************************/
module programmable_unit (Reset, ClkProgram, DataBus, PhaseEnabled, PhaseReOrder,
InitialPhaseOverride, InitialPhaseOverrideValue, Start, Vref0, Vref1, OpenLoop,
PhaseOrderOverride, DOpenLoop, DeadTime, DCharge, LUT0, LUT1, LUT2, LUT3, LUT4, LUT5, LUT6,
LUT7, LUT8, PhaseOrder, MuxControlOverride, DelayControlOverride, MuxControlOverrideValue,
DelayControlOverrideValue, DebugRail, DonePhaseCount, DonePhaseSequence, Locked, PhaseID,
PhaseOrderInternal, PhaseCount, PhaseTimer, IsInitialPhase, RingOscFreq, D, Error,
DelayControlIn, DAC_enable, DAC_freq, SmallerPhases, Prog_select, ADC_enable,
Ring_osc_enable, DLL_enable);

input Reset;
input ClkProgram;
input [7:0] DataBus;
output [3:0] DebugRail;
input Prog_select;

output PhaseEnabled;
output PhaseReOrder;
output InitialPhaseOverride;
output InitialPhaseOverrideValue;
output Start;
output OpenLoop;
output PhaseOrderOverride;
output [9:0] Vref0;
output [9:0] Vref1;
output [7:0] DOpenLoop;
output [7:0] DeadTime;
output [7:0] DCharge;
output [15:0] LUT0;
output [15:0] LUT1;
output [15:0] LUT2;
output [15:0] LUT3;
output [15:0] LUT4;
output [15:0] LUT5;
output [15:0] LUT6;
output [15:0] LUT7;
output [15:0] LUT8;
output [3:0] PhaseOrder;
output MuxControlOverride;
output DelayControlOverride;
output [6:0] MuxControlOverrideValue;
output [2:0] DelayControlOverrideValue;
output [7:0] RingOscFreq;
output DAC_enable;
output [2:0] DAC_freq;
output ADC_enable;
output Ring_osc_enable;
output DLL_enable;

input DonePhaseCount;
input DonePhaseSequence;
input Locked;
input [3:0] PhaseID;
input [3:0] PhaseOrderInternal;
input [3:0] PhaseCount;

input [15:0] PhaseTimer;
input IsInitialPhase;
input [7:0] D;
input [3:0] Error;
input [2:0] DelayControlIn;
input [3:0] SmallerPhases;

wire [7:0] DebugMuxSelect;
reg [3:0] DebugRailReg;
assign DebugRail = DebugRailReg;

reg [7:0] ProgramData [32:0];
reg [1:0] ProgramState;
reg [7:0] Address;

parameter signed a = 16'b0000000000100011;
parameter A0 = a*(16'hffff-16'd4+16'd1);
parameter A4 = a*16'd0;

parameter Unused = 8'b0;

// Default values and output assignments

// 00: - PhaseOrderOverride OpenLoop Start InitialPhaseOverrideValue
InitialPhaseOverride PhaseReOrder PhaseEnabled
parameter ProgramData_00 = 8'b0_0_0_0_0_0_1_1;
assign PhaseEnabled = ProgramData[0][0];
assign PhaseReOrder = ProgramData[0][1];
assign InitialPhaseOverride = ProgramData[0][2];
assign InitialPhaseOverrideValue = ProgramData[0][3];
assign Start = ProgramData[0][4];
assign OpenLoop = ProgramData[0][5];
assign PhaseOrderOverride = ProgramData[0][6];
// 01: Vref0[7:0]
parameter ProgramData_01 = 8'b01010101;
// 02: Vref0[9:8]
parameter ProgramData_02 = 8'b000000_01;
assign Vref0 = {ProgramData[2][1:0], ProgramData[1]};
// 03: Vref1[7:0]
// 04: Vref1[9:8]
assign Vref1 = {ProgramData[4][1:0], ProgramData[3]};
// 05: DOpenLoop
assign DOpenLoop = ProgramData[5];
// 06: DeadTime
assign DeadTime = ProgramData[6];
// 07: DCharge
assign DCharge = ProgramData[7];
// 08: LUT8[7:0]
parameter ProgramData_08 = A8[7:0];
// 09: LUT8[15:8]
assign LUT8 = {ProgramData[9], ProgramData[8]};
// 10: LUT7[7:0]
// 11: LUT7[15:8]
// 12: LUT6[7:0]

// 13: LUT6[15:8]
// 14: LUT5[7:0]
// 15: LUT5[15:8]
// 16: LUT4[7:0]
// 17: LUT4[15:8]
// 18: LUT3[7:0]
// 19: LUT3[15:8]
// 20: LUT2[7:0]
// 21: LUT2[15:8]
// 22: LUT1[7:0]
// 23: LUT1[15:6]
// 24: LUT0[7:0]
// 25: LUT0[15:8]
// 26: - - - - PhaseOrder
assign PhaseOrder = ProgramData[26][3:0];
// 27: - - - - - - MuxControlOverride DelayControlOverride
assign MuxControlOverride = ProgramData[27][1];
assign DelayControlOverride = ProgramData[27][0];
// 28: - MuxControlOverrideValue
assign MuxControlOverrideValue = ProgramData[28][6:0];
// 29: - - - - - DelayControlOverrideValue
assign DelayControlOverrideValue = ProgramData[29][2:0];
// 30: DebugMuxSelect
assign DebugMuxSelect = ProgramData[30];
// 31: RingOscFreq
assign RingOscFreq = ProgramData[31];
// 32: - ADC_enable Ring_osc_enable DLL_enable DAC_enable DAC_freq
parameter ProgramData_32 = 8'b0_1_1_1_0_001;
assign DAC_enable = ProgramData[32][3];
assign DAC_freq = ProgramData[32][2:0];
assign ADC_enable = ProgramData[32][6];
assign Ring_osc_enable = ProgramData[32][5];
assign DLL_enable = ProgramData[32][4];

always @(negedge Reset or posedge ClkProgram)
begin
if (Reset == 1'b0)
begin
ProgramState <= 2'b00;
Address <= 8'b00000000;
ProgramData[0] <= ProgramData_00;

end
else
begin
if (Prog_select == 1'b1)
begin
Address <= 8'b00000000;
end
else
begin
case (ProgramState)
2'b00:
begin
Address <= DataBus;
end
2'b01:
begin
ProgramData[Address[5:0]] <= DataBus;
end
endcase
end
end
end

always @(DebugMuxSelect or DebugRail or DonePhaseCount or DonePhaseSequence or Locked
or PhaseID or PhaseOrderInternal or PhaseCount or PhaseTimer or IsInitialPhase or D or Error
or DelayControlIn or SmallerPhases)
begin
case (DebugMuxSelect)
8'b00000000:
begin
DebugRailReg = {IsInitialPhase, Locked, DonePhaseSequence,
DonePhaseCount};
end
8'b00000001:
begin
DebugRailReg = PhaseID;
end
8'b00000010:
begin
DebugRailReg = PhaseOrderInternal;

end
8'b00000011:
begin
DebugRailReg = SmallerPhases;
end
8'b00000100:
begin
DebugRailReg = PhaseCount;
end
8'b00000101:
begin
DebugRailReg = PhaseTimer[3:0];
end
8'b00000110:
begin
end
8'b00000111:
begin
end
8'b00001000:
begin
end
8'b00001001:
begin
DebugRailReg = D[3:0];
end
8'b00001010:
begin
DebugRailReg = D[7:4];
end
8'b00001011:
begin
DebugRailReg = Error;
end
8'b00001100:
begin
DebugRailReg = DelayControlIn;
end
default:
begin
DebugRailReg = 4'b0;
end
endcase
end

endmodule

/*******************************************************************************************
/ Module: reg_operation
/
/ Set of FSM's for controlling the regular operation of the system. Contains
/ functionality for both single phase and multiphase operation. For single phase
/ operation, the main 1 MHz clock is used, otherwise the bus signals are used for timing.
*******************************************************************************************/
module reg_operation(Reset, Clk_256, Clk, DOut, DonePhaseSequence, DonePhaseCount,
PhaseCount, PhaseOrder, DPWMStart, ReceiveEnd, RXData, DPID, DLastOut, ErrorOut, ADCIn,
OpenLoop, DOpenLoop);

input Clk_256; // 256 MHz clock
input Clk; // 1 MHz clock
output [7:0] DOut; // Duty ratio sent to DPWM
input DonePhaseSequence; // Indicates phase sequencing process is
complete
input DonePhaseCount; // Indicates phase counting process is
complete
input [3:0] PhaseCount; // System phase count

input [3:0] PhaseOrder; // This phase's order in the
switching sequence
output DPWMStart; // Start pulse sent to DPWM
input ReceiveEnd; // Pulse sent from communication
block when each transmission is
//
complete - acts as a clock for multiphase operation
input [3:0] RXData; // Data received from the bus
(corresponds to error signal)
input [15:0] DPID; // Duty ratio caculated by the
compensator
output [15:0] DLastOut; // Last duty ratio send to the
compensator
output [3:0] ErrorOut; // Error value sent to the compensator
input [3:0] ADCIn; // ADC signal
input OpenLoop; // Indicates whether the
system should operate in open-loop mode
input [7:0] DOpenLoop; // Open-loop duty ratio

reg [3:0] RState; // State variable for multiphase
FSM
reg [3:0] PhaseTracker; // For counting phases for
multiphase operation
reg StartPulse; // Start pulse for
beginning of cycle
reg [3:0] SState; // State variable for main
control (both single phase and multiphase)
reg DPWMStartReg; // Indicates DPWM should begin
new switching cycle
reg [3:0] RXDataReg; // Data received from the bus
reg [15:0] DLast; // Previous duty radio
purposes
reg [15:0] DReg; // Duty ratio sent to the
DPWM
reg [3:0] TState; // State variable for single
phase FSM
reg TStartPulse; // Indicates DPWM should begin
its switching cycle for single phase operation
wire AStartPulse; // DPWM start signal
wire SelfFlag; // Indicates whether we are using
single phase or multiphase operation
// If on, the main
clock will be used instead of the bus transmission signals
reg [3:0] ADCCapture; // Register for holding the last ADC
value (used for single phase operation)
reg [2:0] DonePhaseSequenceMS; // Metastable verion of DonePhaseSequence
reg [2:0] DonePhaseCountMS_256; // Metastable version of DonePhaseCount
(for clk_256)
reg [1:0] AStartPulseMS; // Metastable version of AStartPulse;

assign DPWMStart = DPWMStartReg;
assign DLastOut = DLast;
assign DOut = (OpenLoop == 1'b1 ? DOpenLoop : DReg[13:6]);
assign ErrorOut = RXDataReg;

// ADC input is captured at every clock cycle for single phase operation
always @(negedge Reset or posedge Clk)
begin
if (Reset == 1'b0)
begin
ADCCapture <= 4'b0;
end
else
begin
ADCCapture <= ADCIn;
end
end


// Metastabilize DonePhaseSequence input
always @(negedge Reset or posedge ReceiveEnd)
begin
if (Reset == 1'b0)
begin
DonePhaseSequenceMS <= 3'b0;
end
else
begin
DonePhaseSequenceMS[0] <= DonePhaseSequence;
DonePhaseSequenceMS[1] <= DonePhaseSequenceMS[0];
DonePhaseSequenceMS[2] <= DonePhaseSequenceMS[1];
end
end

// Metastabilize DonePhaseCount input (for Clk_256)
always @(negedge Reset or posedge Clk_256)
begin
if (Reset == 1'b0)
begin
DonePhaseCountMS_256 <= 3'b0;
end
else
begin
DonePhaseCountMS_256[0] <= DonePhaseCount;
DonePhaseCountMS_256[1] <= DonePhaseCountMS_256[0];
DonePhaseCountMS_256[2] <= DonePhaseCountMS_256[1];
end
end

// Metastabilize AStartPulse (for Clk_256)
begin
if (Reset == 1'b0)
begin
AStartPulseMS <= 2'b0;
end
else
begin
AStartPulseMS[0] <= AStartPulse;
AStartPulseMS[1] <= AStartPulseMS[0];
end
end

// Set DPWM block start pulse depending on whether we are using single phase or
multiphase operation
assign AStartPulse = ((DonePhaseCount == 1'b1 & PhaseCount == 4'b1) ? TStartPulse :
StartPulse);
// Indicates whether we are using single phase or multiphase operation
assign SelfFlag = ((DonePhaseCount == 1'b1 & PhaseCount == 4'b1) ? 1'b1 : 1'b0);

// Main FSM for multiphase operation
always @(negedge Reset or posedge ReceiveEnd)
begin
if (Reset == 1'b0)
begin
RState <= 4'b0000;
PhaseTracker <= 4'b0000;
StartPulse <= 1'b0;
end
else
begin
case (RState)
// Initial state
// Wait until phase sequencing has been performed
4'b0000:
begin
if (DonePhaseSequenceMS[2] == 1'b1)
begin
RState <= 4'b0001;

if (PhaseOrder == 4'b0)
begin
StartPulse <= 1'b1;
end
else
begin
StartPulse <= 1'b0;
end
end
else
begin
RState <= 4'b0000;
StartPulse <= 1'b0;
end
end
// Steady state
// Receive transmissions and act if current count is this phase
4'b0001:
begin
if (PhaseTracker == PhaseOrder)
begin
StartPulse <= 1'b1;
end
else
begin
StartPulse <= 1'b0;
end
if (PhaseTracker == (PhaseCount - 4'b1))
begin
end
else
begin
PhaseTracker <= (PhaseTracker + 4'b1);
end
RState <= 4'b0001;
end
endcase
end
end

// Similar to above except using Clk instead of ReceiveEnd for timing
begin
if (Reset == 1'b0)
begin
TState <= 4'b0000;
TStartPulse <= 1'b0;
end
else
begin
case (TState)
// Initial state
// Wait until phases have been counted and this is the only
phase
4'b0000:
begin
if (DonePhaseCountMS_256[2] == 1'b1 & PhaseCount ==
4'b1)
begin
TState <= 4'b0001;
end
else
begin
TState <= 4'b0000;
end
end
// Before first cycle
4'b0001:

begin
if (Clk == 1'b1)
begin
TState <= 4'b0010;
end
else
begin
TState <= 4'b0001;
end
end
// Still before first cycle
4'b0010:
begin
if (Clk == 1'b0)
begin
TState <= 4'b0011;
end
else
begin
TState <= 4'b0010;
end
end
// Regular operation
// Mirror Clk pulses
4'b0011:
begin
if (Clk == 1'b1)
begin
TState <= 4'b0100;
end
else
begin
TState <= 4'b0011;
end
end
// Regular operation
4'b0100:
begin
if (Clk == 1'b0)
begin
TState <= 4'b0011;
end
else
begin
TState <= 4'b0100;
end
end
endcase
end
end

// Main FSM for both single phase and multiphase operation
begin
if (Reset == 1'b0)
begin
SState <= 4'b0000;
RXDataReg <= 4'b0;
DLast <= 16'b0;
AuxCounter <= 4'b0;
DReg <= 16'b0;
end
else
begin

case (SState)
// Initial phase
// Wait for start pulse
4'b0000:
begin
AuxCounter <= 4'b0;
if (AStartPulseMS[1] == 1'b1)
begin
SState <= 4'b0001;
if (SelfFlag == 1'b1)
begin
RXDataReg <= ADCCapture;
end
else
begin
RXDataReg <= RXData;
end
end
else
begin
SState <= 4'b0000;
RXDataReg <= RXDataReg;
end
DLast <= DLast;
DReg <= DReg;
end
// Wait a few cycles and record duty ratio
4'b0001:
begin
if (AuxCounter == 1'b0 & AStartPulseMS[1] == 1'b0)
begin
DLast <= DLast;
DReg <= DReg;
SState <= 4'b0000;
end
else if (AuxCounter >= 4'd3)
begin
DLast <= DReg;
DReg <= DPID;
SState <= 4'b0010;
end
else
begin
DLast <= DLast;
DReg <= DReg;
SState <= 4'b0001;
end
end
// Send start signal to DPWM and return to initial state and
wait for next cycle
4'b0010:
begin
AuxCounter <= 4'b0;
DLast <= DLast;
DReg <= DReg;
if (AStartPulseMS[1] == 1'b0)
begin
SState <= 4'b0000;
end
else
begin
SState <= 4'b0010;
end
end
endcase

end
end

endmodule

APPENDIX B: GATE-LEVEL NETLIST FOR COMMUNICATION BLOCK 128

Appendix B: Gate-Level Netlist for
Communication Block
`timescale 1ns/1ps

module comm_block_digital (Reset, Transmit, TXData, comm_out, ReceiveEnd, RXData, comm_in,
IsInitialPhase, clk_256, Clk_out, clk_128_out);

////////////////
// I/O pins
////////////////

input Reset;
input Transmit;
input [3:0] TXData;
inout comm_out;
output ReceiveEnd;
output [3:0] RXData;
input comm_in;
output IsInitialPhase;
input clk_256;
output Clk_out;
output clk_128_out;

///////////////
// Wires
///////////////

wire TranOut;
wire TranEnable;
wire [3:0] TXDataReg;
wire [5:0] TransmitClk;
wire n9, n10, n11, n12, n13, n14;
wire [3:0] ReceiveClk;
wire comm_in_buffered;
wire [19:0] TranDelay0;
wire TranDelayInv2;
wire TranDelayInv3;
wire TranDelayInv4;
wire TranDelayInv5;
wire TranDelayInv6;
wire ReceiveClkWait;
wire [27:0] RecDelay0;
wire RecDelayInv4;
wire ReceiveClkWaitNot;
wire OrTempOutput;
wire TranDelayInv2Reset;

wire RecDelayInv4Reset;
wire ReceiveClkWaitNotReset;
wire hi;
wire [4:0] comm_in_delayed;
wire comm_in_delayed_n;

// Tie Hi
TIEHI TH (.Y(hi));

// Clock divider wires
wire AN2, AN3, AN4, AN5, AN6, AN7, AN8, An1, add_22100_carry_7, add_22100_carry_6,
add_22100_carry_5, add_22100_carry_4, add_22100_carry_3, add_22100_carry_2;
wire [7:0] CDCount;
wire clk_128;
wire Clk;

////////////////
// Transmitter
////////////////

// Buffer with enable input
TBUFX20 Tran_B (.A(TranOut), .OE(TranEnable), .Y(comm_out));
OR4X1 ORA1 (.A(TransmitClk[0]), .B(TransmitClk[1]), .C(TransmitClk[2]),
.D(TransmitClk[3]), .Y(OrTempOutput));
OR2X1 ORB1 (.A(TransmitClk[4]), .B(OrTempOutput), .Y(TranEnable));

// Register TXData
DFFRHQX1 TXDReg0 (.D(TXData[0]), .CK(Transmit), .Q(TXDataReg[0]), .RN(Reset));

// Transmitter combinational logic
NAND2BX1 U11 (.AN(TransmitClk[5]), .B(n9), .Y(TranOut));
AOI22X1 U12 (.A0(n10), .A1(n11), .B0(TXDataReg[3]), .B1(TransmitClk[4]), .Y(n9));
INVX1 U13 (.A(TransmitClk[4]), .Y(n11));
MX2X1 U14 (.S0(TransmitClk[3]), .B(TXDataReg[2]), .A(n12), .Y(n10));
MX2X1 U15 (.S0(TransmitClk[2]), .B(TXDataReg[1]), .A(n13), .Y(n12));
AOI2BB2X1 U16 (.A0N(TXDataReg[0]), .A1N(n14), .B0(TransmitClk[0]), .B1(n14), .Y(n13));
INVX1 U17 (.A(TransmitClk[1]), .Y(n14));

// Transmitter timing block
// TransmitClk[0]
DFFRHQX1 TSB0 (.D(hi), .CK(Transmit), .Q(TransmitClk[0]), .RN(TranDelayInv2Reset));
DLY4X1 DL00 (.A(TransmitClk[0]), .Y(TranDelay0[0]));
DLY4X1 DL01 (.A(TranDelay0[0]), .Y(TranDelay0[1]));
// TransmitClk[1]
DFFRHQX1 TSB1 (.D(hi), .CK(TranDelay0[19]), .Q(TransmitClk[1]),
.RN(TranDelayInv3Reset));

// TransmitClk[2]
INVX1 TINV2 (.A(TransmitClk[2]), .Y(TranDelayInv2));
AND2X1 TAND2 (.A(Reset), .B(TranDelayInv2), .Y(TranDelayInv2Reset));
// TransmitClk[3]
// TransmitClk[4]

// TransmitClk[5]
INVX1 TINV6 (.A(TranDelay5[19]), .Y(TranDelayInv6));

////////////////
// Receiver
////////////////

// Buffer comm_in
BUFX1 InBuff (.A(comm_in), .Y(comm_in_buffered));

// Register RXData
DFFRHQX4 RXDReg0 (.D(comm_in_buffered), .CK(ReceiveClk[0]), .Q(RXData[0]),
.RN(Reset));
.RN(Reset));
.RN(Reset));
.RN(Reset));

// Receiver timing block
// ReceiveClkWait
DFFNRX1 RB0 (.D(hi), .CKN(comm_in_buffered), .Q(ReceiveClkWait),
.RN(RecDelayInv4Reset));
DLY4X1 RDL00 (.A(ReceiveClkWait), .Y(RecDelay0[0]));

DLY4X1 RDL01 (.A(RecDelay0[0]), .Y(RecDelay0[1]));
// ReceiveClk[0]
DFFRHQX1 RB1 (.D(hi), .CK(RecDelay0[27]), .Q(ReceiveClk[0]), .RN(RecDelayInv4Reset));
DLY4X1 RDL10 (.A(ReceiveClk[0]), .Y(RecDelay1[0]));
// ReceiveClk[1]

// ReceiveClk[2]
// ReceiveClk[3]
INVX1 RINV4 (.A(RecDelay4[19]), .Y(RecDelayInv4));
AND2X1 RAND4 (.A(Reset), .B(RecDelayInv4), .Y(RecDelayInv4Reset));

DLY4X1 RDL40b (.A(RecDelay4[19]), .Y(RecDelay4[20]));

// ReceiveEnd
INVX1 RINV5 (.A(ReceiveClkWait), .Y(ReceiveClkWaitNot));
AND2X1 REAND (.A(Reset), .B(ReceiveClkWaitNot), .Y(ReceiveClkWaitNotReset));
DFFRHQX1 FIN (.D(hi), .CK(RecDelay4[29]), .RN(ReceiveClkWaitNotReset),
.Q(ReceiveEnd));

///////////////////////////
// Initial phase detector
///////////////////////////

DLY4X1 IPD0 (.A(comm_in_buffered), .Y(comm_in_delayed[0]));
DLY4X1 IPD1 (.A(comm_in_delayed[0]), .Y(comm_in_delayed[1]));

INVX1 IPDINV (.A(comm_in_delayed[4]), .Y(comm_in_delayed_n));
DFFHQX2 IPDDFF (.D(comm_in_delayed_n), .CK(Reset), .Q(IsInitialPhase));

///////////////////////////
// Clock divider
///////////////////////////

DFFRX1 ClkReg_reg (.D(CDCount[7]), .CK(clk_256), .RN(Reset), .Q(Clk));
DFFRX1 clk_128_reg_reg (.D(CDCount[0]), .CK(clk_256), .RN(Reset), .Q(clk_128));
ADDHXL \Aadd_22/U1_1_1 (.A(CDCount[1]), .B(CDCount[0]), .S(N2),
.CO(add_22100_carry_2));
ADDHXL \Aadd_22/U1_1_5 (.A(CDCount[5]), .B(add_22100_carry_5), .S(AN6),
XOR2X1 U3A (.A(add_22100_carry_7), .B(CDCount[7]), .Y(AN8));
DFFRX1 \CDCount_reg[0] (.D(n1), .CK(clk_256), .RN(Reset), .Q(CDCount[0]), .QN(n1));
DFFRX1 \CDCount_reg[2] (.D(AN3), .CK(clk_256), .RN(Reset), .Q(CDCount[2]));
DFFRX1 \CDCount_reg[1] (.D(N2), .CK(clk_256), .RN(Reset), .Q(CDCount[1]));

CLKBUFX12 CB_a (.A(Clk), .Y(Clk_out));
CLKBUFX12 CB_b (.A(clk_128), .Y(clk_128_out));

endmodule
APPENDIX C: PCB BOARD AND SCHEMATICS 135

Appendix C: PCB Board and Schematics
The printed-circuit board (PCB) design below was fabricated to test the fabricated chip. The
main board includes hardware for interfacing an FPGA development board with the system
for debugging purposes, as well as other necessary hardware including linear regulators and
power connectors. Also included is 4 sockets for connecting modules. Each module consists
of a plug-and-play digital controller chip and a power stage. The PCB layouts and
schematics are shown in the figures below for the main board and the module board.

Figure C. 1: Layout for the main board
2
2
2
2
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2 1
2 1
2 1
2 1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
1 2 3
4
1 2 3
4
1 2 3
4
15 16 17 18 19 20 21 22 23 24 25 26 27 28
14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 2
2 1
1 2
2
1
1 2
3
2 1
3
1
4
2
4 3
2 1
4 3
2 1
1 2
3 4
4 3
2 1
1 2
3 4
5
6
7
8
4
3
2
1
5
6
7
8
4
3
2
1
40 39
38
36
34
32
28
26
24
22
20
18
16
27
25
23
21
19
17
15
13
9
7
5
3
1
10
11 12
14
29 30
31
33
35
37
2
4
6
8
30
15
13
9
7
5
3
34
40
38
36
32
28
26
24
22
20
18
16
14
10
8
11 12
29
1 2
4
6
17
19
21
23
25
27
31
33
35
37
39
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
2 1 2 1 2 1 2 1
2 1
1
2
2 1
2 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
6
7
8
4
3
2
1
1
2
3
1
2
3
1
2
3
2
1 1
2
2
1 2
1
1
2
2
1
2
1
2 1
2
1
2
1
2
1
1 2
2
1
2
1
2
1
1 2
2
1 1 2 3
4 5
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9

Figure C. 2: Top-level schematic for the main board

Figure C. 3: Schematic for output voltage capacitors and connectors

+1
--2
J1
CONN
+9V
1
H1
GND
+1
--2
J3
CONN
GND
VIN
+1
--2
J4
CONN
GND
VIN
+1
--2
J2
CONN
GND
VDRIVE
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
JP5
Header 20X2
VCC5_JP5 VCC33_JP5
GND GND
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
JP6
Header 20X2
VCC5_JP6 VCC33_JP6
GND GND
VIN
VDRIVE
VOUT
VIN
VDRIVE
VOUT
GND GND
GND GND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP1
Header 20X2
LOADSTEP2
LOADSTEP1
+1
--2
J5
CONN
GND
VBANDGAP
U_PowerBlock
PowerBlock.SchDoc
U_PowerOutput
PowerOutput.SchDoc
Data_bus_3 Data_bus_2
Reset Prog_select
comm_out_0 comm_out_3
DebugRail_0_0
DebugRail_1_0
DebugRail_2_0
DebugRail_3_0 Prog_clk_0
MS0_EXT
SR0_EXT
+1.8V
+3.3V +3.3V
+1.8V
VBANDGAP
VIN
VDRIVE
VOUT
VIN
VDRIVE
VOUT
GND GND
GND GND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP2
Header 20X2
Reset Prog_select
DebugRail_0_1
DebugRail_1_1
DebugRail_2_1
MS1_EXT
SR1_EXT
+1.8V
+3.3V +3.3V
+1.8V
VBANDGAP
VIN
VDRIVE
VOUT
VIN
VDRIVE
VOUT
GND GND
GND GND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP3
Header 20X2
Reset Prog_select
DebugRail_0_2
DebugRail_1_2
DebugRail_2_2
MS2_EXT
SR2_EXT
+1.8V
+3.3V +3.3V
+1.8V
VBANDGAP
VIN
VDRIVE
VOUT
VIN
VDRIVE
VOUT
GND GND
GND GND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP4
Header 20X2
Reset Prog_select
DebugRail_0_3
DebugRail_1_3
DebugRail_2_3
MS3_EXT
SR3_EXT
+1.8V
+3.3V +3.3V
+1.8V
VBANDGAP
1 2
3 4
P1
Header 2X2
1 2
3 4
P2
Header 2X2
1 2
3 4
P3
Header 2X2
1 2
3 4
P4
Header 2X2
comm_out_3 comm_out_0 comm_out_0 comm_out_1 comm_out_1 comm_out_2
comm_out_2
comm_out_3
A
u
x
R
e
s
e
t_
fp
g
a
A
u
x
R
e
s
e
tE
n
a
b
le
_
fp
g
a
R
e
s
e
t_
fp
g
a
D
a
ta
_
b
u
s
_
0
_
fp
g
a
D
a
ta
_
b
u
s
_
1
_
fp
g
a
D
a
ta
_
b
u
s
_
4
_
fp
g
a
D
a
ta
_
b
u
s
_
3
_
fp
g
a
D
a
ta
_
b
u
s
_
2
_
fp
g
a
D
a
ta
_
b
u
s
_
5
_
fp
g
a
D
a
ta
_
b
u
s
_
6
_
fp
g
a
D
a
ta
_
b
u
s
_
7
_
fp
g
a
P
ro
g
_
s
e
le
c
t_
fp
g
a
S
R
0
_
E
X
T
M
S
0
_
E
X
T
S
R
1
_
E
X
T
M
S
1
_
E
X
T
S
R
2
_
E
X
T
M
S
2
_
E
X
T
D
e
b
u
g
R
a
il_
3
_
2
_
fp
g
a
D
e
b
u
g
R
a
il_
2
_
2
_
fp
g
a
D
e
b
u
g
R
a
il_
1
_
2
_
fp
g
a
D
e
b
u
g
R
a
il_
0
_
2
_
fp
g
a
D
e
b
u
g
R
a
il_
3
_
1
_
fp
g
a
D
e
b
u
g
R
a
il_
2
_
1
_
fp
g
a
D
e
b
u
g
R
a
il_
1
_
1
_
fp
g
a
D
e
b
u
g
R
a
il_
0
_
1
_
fp
g
a
D
e
b
u
g
R
a
il_
3
_
0
_
fp
g
a
D
e
b
u
g
R
a
il_
2
_
0
_
fp
g
a
D
e
b
u
g
R
a
il_
1
_
0
_
fp
g
a
D
e
b
u
g
R
a
il_
0
_
0
_
fp
g
a
P
ro
g
_
c
lk
_
3
_
fp
g
a
P
ro
g
_
c
lk
_
2
_
fp
g
a
P
ro
g
_
c
lk
_
1
_
fp
g
a
P
ro
g
_
c
lk
_
0
_
fp
g
a
M
S
3
_
E
X
T
S
R
3
_
E
X
T
D
e
b
u
g
R
a
il_
0
_
3
_
fp
g
a
D
e
b
u
g
R
a
il_
1
_
3
_
fp
g
a
D
e
b
u
g
R
a
il_
2
_
3
_
fp
g
a
D
e
b
u
g
R
a
il_
3
_
3
_
fp
g
a
AuxReset_fpga
AuxResetEnable_fpga
Reset_fpga
Data_bus_0_fpga
Data_bus_1_fpga
Data_bus_2_fpga
Data_bus_3_fpga
Data_bus_4_fpga
Data_bus_5_fpga
Data_bus_6_fpga
Data_bus_7_fpga
DebugRail_0_0_fpga
DebugRail_1_0_fpga
DebugRail_2_0_fpga
DebugRail_3_0_fpga
DebugRail_0_1_fpga
DebugRail_1_1_fpga
DebugRail_2_1_fpga
DebugRail_3_1_fpga
DebugRail_0_2_fpga
DebugRail_1_2_fpga
DebugRail_2_2_fpga
DebugRail_3_2_fpga
DebugRail_0_3_fpga
DebugRail_1_3_fpga
DebugRail_2_3_fpga
DebugRail_3_3_fpga
Prog_select_fpga
Prog_clk_0_fpga
Prog_clk_1_fpga
Prog_clk_2_fpga
Prog_clk_3_fpga
AuxReset
Reset
Data_bus_0
Data_bus_1
Data_bus_2
Data_bus_3
Data_bus_4
Data_bus_5
Data_bus_6
Data_bus_7
DebugRail_0_0
DebugRail_1_0
DebugRail_2_0
DebugRail_3_0
DebugRail_0_1
DebugRail_1_1
DebugRail_2_1
DebugRail_3_1
DebugRail_0_2
DebugRail_1_2
DebugRail_2_2
DebugRail_3_2
DebugRail_0_3
DebugRail_1_3
DebugRail_2_3
DebugRail_3_3
Prog_select
Prog_clk_0
Prog_clk_1
Prog_clk_2
Prog_clk_3
U_LevelShift
LevelShift.SchDoc
AuxReset_fpga
AuxResetEnable_fpga
Reset_fpga
Data_bus_0_fpga
Data_bus_1_fpga
Data_bus_2_fpga
Data_bus_3_fpga
Data_bus_4_fpga
Data_bus_5_fpga
Data_bus_6_fpga
Data_bus_7_fpga
Prog_select_fpga
Prog_clk_0_fpga
Prog_clk_1_fpga
Prog_clk_2_fpga
Prog_clk_3_fpga
DebugRail_0_0
DebugRail_1_0
DebugRail_2_0
DebugRail_3_0
DebugRail_0_1
DebugRail_1_1
DebugRail_2_1
DebugRail_3_1
DebugRail_0_2
DebugRail_1_2
DebugRail_2_2
DebugRail_3_2
DebugRail_0_3
DebugRail_1_3
DebugRail_2_3
DebugRail_3_3
Prog_clk_3
Prog_clk_2
Prog_clk_1
Prog_clk_0
Prog_select
Data_bus_7
Data_bus_6
Data_bus_4
Data_bus_5
Data_bus_3
Data_bus_2
Data_bus_1
Data_bus_0
Reset
AuxReset
DebugRail_3_3_fpga
DebugRail_2_3_fpga
DebugRail_1_3_fpga
DebugRail_0_3_fpga
DebugRail_3_2_fpga
DebugRail_1_2_fpga
DebugRail_2_2_fpga
DebugRail_0_2_fpga
DebugRail_3_1_fpga
DebugRail_2_1_fpga
DebugRail_1_1_fpga
DebugRail_3_0_fpga
DebugRail_0_1_fpga
DebugRail_2_0_fpga
DebugRail_1_0_fpga
DebugRail_0_0_fpga
1
H2
1
H3
1
H4
1
H5
L
O
A
D
S
T
E
P
2
L
O
A
D
S
T
E
P
1
AuxReset
ADC_B07
ADC_B08
ADC_B09
ADC_B10
ADC_B11
ADC_B12
ADC_B01
ADC_B02
ADC_B03
ADC_B04
ADC_B05
ADC_B06
ADC_CLK
U_ADC
ADC.SchDoc
ADC_CLK ADC_B01
ADC_B02
ADC_B03
ADC_B04
ADC_B05
ADC_B06
ADC_B07
ADC_B08
ADC_B09
ADC_B10
ADC_B11
ADC_B12
A
D
C
_
C
L
K
A
D
C
_
B
0
1
A
D
C
_
B
0
2
A
D
C
_
B
0
3
A
D
C
_
B
0
4
A
D
C
_
B
0
5
A
D
C
_
B
0
6
A
D
C
_
B
0
7
A
D
C
_
B
0
8
A
D
C
_
B
0
9
A
D
C
_
B
1
0
A
D
C
_
B
1
1
A
D
C
_
B
1
2
LOADSTEP2
LOADSTEP1
U_LoadStep
LoadStep.SchDoc
1
H6
1
H7
1
H8
GND
1
H4o
+1
--2
J1o
CONN
GND
1
H2o
C2o
Cap Semi
C3o
Cap Semi
C4o
Cap Semi
C5o
Cap Semi
C6o
Cap Semi
C1o
Cap Semi
1
H3o
VOUT
1
H1o
1
H5o
1
H6o

Figure C. 4: Schematic for linear regulators

Figure C. 5: Schematic for load-step circuit

+9V
GND
+1.8V
C1p
Cap Semi
GND
C2p
Cap Semi
GND
R1p
Res3
GND
+9V
GND GND
+3.3V
C3p
Cap Semi
GND
C4p
Cap Semi
GND
R2p
Res3
D2
SUPER REDLED
GND
Output
3
Vin
1
G
N
D
2
G
N
D
4
U2p uA78M15
1
H1p
1
H2p
D1
SUPER REDLED
+9V
GND GND
+5.0V
C5p
Cap Semi
GND
C6p
Cap Semi
GND
R3p
Res3
D3
SUPER REDLED
GND
Output
3
Vin
1
G
N
D
2
G
N
D
4
U3p uA78M15
1
H3p
Output
3
Vin
1
G
N
D
2
G
N
D
4
U1p uA78M15
GND
D4
5
D3
6
D2
7
D1
8
G1
4
S3
3
S2
2
S1
1
M2
IRF7832
D4
5
D3
6
D2
7
D1
8
G1
4
S3
3
S2
2
S1
1
M1
IRF7832
OUTB
5
VDD
6
OUTA
7
NC2
8
INB
4
GND
3
INA
2
NC1
1
DRV1
VDRIVE
GND
GND
1
H1L
1
H2L
1
H3L
C1L
Cap Semi
1 2
3 4
P2L
Header 2X2
GND
GND
+1
--2
J2L
CONN
+1
--2
J1L
CONN
1 2
3 4
P1L
Header 2X2
LOADSTEP2
LOADSTEP1
1
H4L
VOUT

Figure C. 6: Schematic for level-shifting for communication between the ICs and the FPGA

Figure C. 7: Layout of the plug-in module

AuxReset_fpga
AuxResetEnable_fpga
Reset_fpga
Data_bus_0_fpga
Data_bus_1_fpga
Data_bus_2_fpga
Data_bus_3_fpga
Data_bus_4_fpga
Data_bus_5_fpga
Data_bus_6_fpga
Data_bus_7_fpga
DebugRail_0_0_fpga
DebugRail_1_0_fpga
DebugRail_2_0_fpga
DebugRail_3_0_fpga
DebugRail_0_1_fpga
DebugRail_1_1_fpga
DebugRail_2_1_fpga
DebugRail_3_1_fpga
DebugRail_0_2_fpga
DebugRail_1_2_fpga
DebugRail_2_2_fpga
DebugRail_3_2_fpga
DebugRail_0_3_fpga
DebugRail_1_3_fpga
DebugRail_2_3_fpga
DebugRail_3_3_fpga
Prog_select_fpga
Prog_clk_0_fpga
Prog_clk_1_fpga
Prog_clk_2_fpga
Prog_clk_3_fpga
AuxReset
Reset
Data_bus_0
Data_bus_1
Data_bus_2
Data_bus_3
Data_bus_4
Data_bus_5
Data_bus_6
Data_bus_7
DebugRail_0_0
DebugRail_1_0
DebugRail_2_0
DebugRail_3_0
DebugRail_0_1
DebugRail_1_1
DebugRail_2_1
DebugRail_3_1
DebugRail_0_2
DebugRail_1_2
DebugRail_2_2
DebugRail_3_2
DebugRail_0_3
DebugRail_1_3
DebugRail_2_3
DebugRail_3_3
Prog_select
Prog_clk_0
Prog_clk_1
Prog_clk_2
Prog_clk_3
VCC
1
A_EN
2
A
3
E
4
F
5
B
6
G
11
NC
12
H
13
D
14
D_EN
15
VDD
16
B_EN
7
VSS
8
C
10
C_EN
9
B3s
HCF40109 Quad Low-to-High Voltage Level Shifter
+3.3V
GND
AuxReset_fpga
AuxReset
AuxResetEnable_fpga
AuxReset_fpga
AuxResetEnable_fpga
Reset_fpga
Data_bus_0_fpga
Data_bus_1_fpga
Data_bus_2_fpga
Data_bus_3_fpga
Data_bus_4_fpga
Data_bus_5_fpga
Data_bus_6_fpga
Data_bus_7_fpga
Prog_select_fpga
Prog_clk_0_fpga
Prog_clk_1_fpga
Prog_clk_2_fpga
Prog_clk_3_fpga
DebugRail_0_0_fpga
DebugRail_1_0_fpga
DebugRail_2_0_fpga
DebugRail_3_0_fpga
DebugRail_0_1_fpga
DebugRail_1_1_fpga
DebugRail_2_1_fpga
DebugRail_3_1_fpga
DebugRail_0_2_fpga
DebugRail_1_2_fpga
DebugRail_2_2_fpga
DebugRail_3_2_fpga
DebugRail_0_3_fpga
DebugRail_1_3_fpga
DebugRail_2_3_fpga
DebugRail_3_3_fpga
AuxReset
Reset
Data_bus_0
Data_bus_1
Data_bus_2
Data_bus_3
Data_bus_4
Data_bus_5
Data_bus_6
Data_bus_7
Prog_select
Prog_clk_0
Prog_clk_1
Prog_clk_2
Prog_clk_3
DebugRail_0_0
DebugRail_1_0
DebugRail_2_0
DebugRail_3_0
DebugRail_0_1
DebugRail_1_1
DebugRail_2_1
DebugRail_3_1
DebugRail_0_2
DebugRail_1_2
DebugRail_2_2
DebugRail_3_2
DebugRail_0_3
DebugRail_1_3
DebugRail_2_3
DebugRail_3_3
C1s
Cap Semi
C2s
Cap Semi
C3s
Cap Semi
C4s
Cap Semi
GND GND
+1.8V +3.3V
1DIR
1
1B1
2
1B2
3
GND1
4
1B3
5
1B4
6
VCCB1
7
1B5
8
1B6
9
GND2
10
1B7
11
1B8
12
2B1
13
2B2
14
GND3
15
2B3
16
2B4
17
VCCB2
18
2B5
19
2B6
20
GND4
21
2B7
22
2B8
23
2DIR
24
2OE
25
2A8
26
2A7
27
GND8
28
2A6
29
2A5
30
VCCA2
31
2A4
32
2A3
33
GND7
34
2A2
35
2A1
36
1A8
37
1A7
38
GND6
39
1A6
40
1A5
41
VCCA1
42
1A4
43
1A3
44
GND5
45
1A2
46
1A1
47
1OE
48
B1s
SN74AVC16T245
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
Reset_fpga
Data_bus_0_fpga
Data_bus_1_fpga
Data_bus_2_fpga
Data_bus_3_fpga
Data_bus_4_fpga
Data_bus_5_fpga
Data_bus_6_fpga
Data_bus_7_fpga
Prog_select_fpga
Prog_clk_0_fpga
Prog_clk_1_fpga
Prog_clk_2_fpga
Prog_clk_3_fpga
+3.3V
+3.3V +1.8V
+1.8V
Data_bus_4
Data_bus_3
Data_bus_2
Data_bus_1
Data_bus_0
Reset
Data_bus_5
Data_bus_6
Data_bus_7
Prog_select
Prog_clk_0
Prog_clk_1
Prog_clk_2
Prog_clk_3
GND
GND
1DIR
1
1B1
2
1B2
3
GND1
4
1B3
5
1B4
6
VCCB1
7
1B5
8
1B6
9
GND2
10
1B7
11
1B8
12
2B1
13
2B2
14
GND3
15
2B3
16
2B4
17
VCCB2
18
2B5
19
2B6
20
GND4
21
2B7
22
2B8
23
2DIR
24
2OE
25
2A8
26
2A7
27
GND8
28
2A6
29
2A5
30
VCCA2
31
2A4
32
2A3
33
GND7
34
2A2
35
2A1
36
1A8
37
1A7
38
GND6
39
1A6
40
1A5
41
VCCA1
42
1A4
43
1A3
44
GND5
45
1A2
46
1A1
47
1OE
48
B2s
SN74AVC16T245
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
+1.8V
+1.8V
+3.3V
+3.3V
+1.8V
+1.8V
DebugRail_0_0_fpga
DebugRail_1_0_fpga
DebugRail_2_0_fpga
DebugRail_3_0_fpga
DebugRail_0_0
DebugRail_1_0
DebugRail_2_0
DebugRail_3_0
DebugRail_0_1_fpga
DebugRail_1_1_fpga
DebugRail_2_1_fpga
DebugRail_3_1_fpga
DebugRail_0_1
DebugRail_1_1
DebugRail_2_1
DebugRail_3_1
DebugRail_0_2_fpga
DebugRail_1_2_fpga
DebugRail_2_2_fpga
DebugRail_3_2_fpga
DebugRail_0_2
DebugRail_2_2
DebugRail_1_2
DebugRail_3_2
DebugRail_0_3
DebugRail_1_3
DebugRail_2_3
DebugRail_3_3 DebugRail_3_3_fpga
DebugRail_2_3_fpga
DebugRail_1_3_fpga
DebugRail_0_3_fpga
+3.3V
5
6
7
8
4
3
2
1
1 2
1
2
1 2
1 2
1 2
2
1
2
1
4 3
2 1
4 3
2 1
1
2
3
4
8
7
6
5 1 2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
33 32 31 30 29 28 27 26 25 24 23
22
21
20
19
18
17
16
15
14
13
12
11 10 9 8 7 6 5 4 3 2 1
44
43
42
41
40
39
38
37
36
35
34
1
1 1
1
1
1
1
1
1
2
1
2 2
1 1 2

Figure C. 8: Schematic for the plug-in module
VIN
VDRIVE
VOUT
VIN
VDRIVE
VOUT
GND GND
GND GND
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JP1
Header 20X2
Reset Prog_select
comm_out comm_in
DebugRail_0
DebugRail_1
DebugRail_2
DebugRail_3 Prog_clk
MS0_EXT
SR0_EXT
+1.8V
+3.3V +3.3V
+1.8V
VBANDGAP
OUTB
5
VDD
6
OUTA
7
NC2
8
INB
4
GND
3
INA
2
NC1
1
DRV1
GND GND GND
C4
100uF/6.3V
C5
100uF/6.3V
GND
1
H2
VIN
1
H8
C3
100uF/6.3V
GND
1
H3
1
H6
1
H7
1
H1
1
H5
1
H4
MS1
SR1
LX
S1
1
G1
2
S2
3
G2
4
D
8
D
7
D
6
D
5
M1
IRF7379PbF
LX
C1
10uF/16V
C2
10uF/16V
L1
UP1B-R47-R
D
e
b
u
g
R
a
i
l
_
1
D
e
b
u
g
R
a
i
l
_
2
D
e
b
u
g
R
a
i
l
_
3
R
e
s
e
t
c
o
m
m
_
i
n
c
o
m
m
_
o
u
t
P
r
o
g
_
s
e
l
e
c
t
S
R
0
_
I
N
T
M
S
0
_
I
N
T
DebugRail_0
Data_bus_0
Data_bus_1
Data_bus_2
Data_bus_3
Data_bus_4
Data_bus_5
Data_bus_6
Data_bus_7
Prog_clk
VDRIVE
VOUT
+1.8V
R1
100k
R2
100k
comm_out
1 2
3 4
P1
Header 2X2
SR0_EXT
MS0_EXT
1 2
3 4
P2
Header 2X2
VBANDGAP
GND
GND
GND
VSS_2
34
CLK_PARAM
35
DATA_BUS_7
36
DATA_BUS_6
37
DATA_BUS_5
38
DATA_BUS_4
39
DATA_BUS_3
40
DATA_BUS_2
41
DATA_BUS_1
42
DATA_BUS_0
43
DRAIL_0
44
NC
12
NC
13
NC
14
NC
15
NC
16
NC
17
NC
18
NC
19
NC
20
NC
21
NC
22
D
R
A
I
L
_
1
1
D
R
A
I
L
_
2
2
D
R
A
I
L
_
3
3
V
S
S
_
3
4
V
D
D
1
8
_
I
O
R
I
N
G
5
R
E
S
E
T
6
C
O
M
M
_
I
N
7
C
O
M
M
_
O
U
T
8
P
R
O
G
_
S
E
L
E
C
T
9
N
C
1
0
N
C
1
1
V
D
D
1
8
_
O
S
C
3
3
M
S
3
2
S
R
3
1
V
O
U
T
3
0
V
D
D
3
3
2
9
V
_
B
A
N
D
G
A
P
2
8
V
D
D
1
8
_
A
D
C
2
7
V
S
S
1
2
6
N
C
2
5
N
C
2
4
N
C
2
3 ICFTRFBS
ICFTRFBS
+3.3V +1.8V
+1.8V
+1.8V
VOUT
SR0_INT
MS0_INT
+3.3V +1.8V VBANDGAP
C6
100uF/6.3V
C7
100uF/6.3V
C8
100uF/6.3V
GND GND GND
R3
100k
REFERENCES 140

References
[1] J. B. Wang and S. Chuang, "A study of the interleaved buck derived converters," in
International Conference on Industrial Technology, 2006, pp. 557-562.
[2] Intel Corporation, "Intel Pentium 4 Processor VR-Down Design Guidelines," 2002.
[3] Current Solutions, Inc., APC-D2000 Product Data Sheet, 2004.
[4] Enatel Limited, CM1748/48 Product Data Sheet, 2008.
[5] Robin Kelley, Michael S. Mazzola, and Volodymyr Bondarenko, "A Scalable SiC
Device for DC/DC Converters in Future Hybrid Electric Vehicles," in 21st Annual
Applied Power Electronics Conference, 2006.
[6] L. Palma and P. Enjeti, "A Modular Fuel Cell, Modular DC-DC Converter Concept for
High Performance and Enhanced Reliability," in Power Electronics Specialists
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[8] Wenkang Huang, George Schuellein, and Danny Clavette, "A Scalable Multiphase Buck
Converter with Average Current Share Bus," in 18th Annual Applied Power Electronics
Conference, 2003.
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22nd Annual IEEE Applied Power Electronics Conference, 2007, pp. 42-47.
[10] Z. Lukic, Z. Zhao, A. Prodic, and D. Goder, "Digital Controller for Multi-Phase DC-DC
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Buck Converter With Integrated Output Filter in 0.18 m SiGe Process," IEEE
Transactions on Power Electronics, Vol. 22, No. 6, pp. 2164-2175, 2007.
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Modulator," IEEE Transactions on Power Electronics, Vol. 23, No. 4, pp. 2201-2205,
2008.
[13] Andrija Stupar, "Implementation of Fast Transient Response Digital Controllers for
High Frequency Switch-Mode Power Supplies," University of Toronto, M.A.Sc. Thesis
2008.
[14] L. Corradini, P. Mattavelli, W. Stefanutti, and S. Saggini, "Simplified Model Reference-
Based Autotuning for Digitally Controlled SMPS," IEEE Transactions on Power
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Electronics, Vol. 23, No. 4, pp. 1956-1963, 2008.
[15] W. Stefanutti, P. Mattavelli, S. Saggini, and M. Ghioni, "Autotuning of Digitally
Controlled DCDC Converters Based on Relay Feedback," IEEE Transactions on
Power Electronics, Vol. 22, No. 1, pp. 199-207, 2007.
[16] W. Stefanutti, S. Saggini, E. Tedeschi, P. Mattavelli, and P. Tenti, "Simplified Model
Reference Tuning of PID Regulators of Digitally Controlled DC-DC Converters Based
on Crossover Frequency Analysis," in Power Electronics Specialists Conference, 2007,
pp. 785-791.
[17] W. Xiao and W. G. Dunford, "Fuzzy logic auto-tuning applied on DC-DC converter,"
30th Annual Conference of the Industrial Electronics Society, pp. 2661-2666, 2004.
[18] Z. Zhao and A. Prodic, "Limit-Cycle Oscillations Based Auto-Tuning System for
Digitally Controlled DC-DC Power Supplies," IEEE Transactions on Power
Electronics, Vol. 24, No. 6, pp. 2211-2222, 2007.
[19] O. Garcia, A. de Castro, P. Zumelis, and J. A. Cobos, "Digital-Control-Based Solution
to the Effect of Nonidealities of the Inductors in Multiphase Converters," IEEE
Transactions on Power Electronics, vol. 22, no. 6, pp. 2155-2163, 2007.
[20] Dallas Semiconductor Corp., "1-Wire Products Mixed-Signal Design Guide," Technical
Report 2005.
[21] C. K. Liu, P. L. Cheng, S. Y. Y. Leung, and D. C. C. Lam, "Inductance Tolerance
Analyses and Design-Process Map of Embedded Planar Spiral Inductor," in 54th
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Electronic Components and Technology Conference, 2004, pp. 1108-1112.
[22] Robert W. Erickson and Dragan Maksimovic, Fundamentals of Power Electronics, 2nd
ed.: Springer Science+Business Media Inc., 2001.
[23] NXP Semiconductors, "PIP212-12M Product Data Sheet," Technical Report 2006.
[24] Z. Lukic, N. Rahman, and A. Prodic, "Multibit Sigma-Delta PWM Digital Controller IC
for DCDC Converters Operating at Switching Frequencies Beyond 10 MHz," IEEE
Transactions on Power Electronics, vol. 22, no. 5, pp. 1693-1707, September 2007.
[25] Amir Parayandeh, "Programmable Application Specific ADC for Digitally Controlled
Switch-Mode Power Supplies," University of Toronto, M.A.Sc. Thesis 2006.

Weinstein Jason 200911 MASc Thesis

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PLUG-AND-PLAY DIGITAL CONTROLLERS FOR SCALABLE LOW-POWER

SWITCH-MODE POWER SUPPLIES

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