VLSI PROJECTS

SL.NO .
1 2

PROJECT TITLE
Low-Power and Area-Efficient Carry Select Adder Field Programmable Gate Array Prototyping of End-Around Carry Parallel Prefix Tree Architectures. A New Reversible Design Of BCD Adder 4 Bit SQF Multiplier Based On Booth Encoder A Low-Power And Portable Spread Spectrum Clock Generator For SOC Applications A Design Of Network Remote Control System Design And Characterization Of Parallel Prefix Adders Using FPGAs An FPGA Implementation of a Simple Lossless Data Compression Coprocessor A Distributed Canny Edge Detector And Its Implementation On FPGA Design Of Low Power And High Speed Configurable Booth Multiplier An Efficient Architecture Design For VGA Monitor Controller High-Accuracy Fixed-Width Modified Booth Multipliers For Lossy Applications Efficient Iterative Techniques For Soft Decision Decoding Of Reed-Solomon Codes A Novel Low Power And High Speed Wallace Tree Multiplier For RISC Processor Image Encryption Based On AES Key Expansion A Flexible Hardware Implementation Of SHA-1 And SHA-2 Hash Functions Effect Of Carrier Frequency Offset On Single-Carrier CDMA With Frequency- Domain Equalization A Median Filter FPGA With Harvard Architecture A Lightweight High-Performance Fault Detection Scheme For The Advanced Encryption Standard Using Composite Fields Performance Analysis Of Integer Wavelet Transform For Image Compression FPGA Implementation Of RS232 To Universal Serial Bus Converter

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

18 19

20 21

22

Direct Digital Frequency Synthesizer Using Nonuniform Piecewise-Linear Approximation FPGA Implementation of a CORDIC-based Radix-4 FFT Processor for Real-Time Harmonic Analyzer A New Adaptive Weight Algorithm For Salt And Pepper Noise Removal Low Power Chien Search For BCH Decoder Using RT-Level Power Management Design And Implementation Of Area-Optimized AES Based On FPGA Sort Optimization Algorithm Of Median Filtering Based On FPGA Design Of SHA-1 Algorithm Based On FPGA Design Space Exploration Of Hard-Decision Viterbi Decoding: Algorithm And VLSI Implementation FPGA Design Of AES Core Architecture For Portable Hard Disk Design And FPGA Implementation Of Modified Distributive Arithmetic Based DWT-IDWT Processor For Image Compression FPGA Based FFT Algorithm Implementation In WiMAX Communications System Systematic Design Of RSA Processors Based On High-Radix Montgomery Multipliers An FPGA-Based Architecture For Linear And Morphological Image Filtering RFID-Based Hospital Real-Time Patient Management System Design And Simulation Of UART Serial Communication Module Based On VHDL A Review On Power Optimization Of Linear Feedback Shift Register (LFSR) For Low Power Built In Self Test (BIST) Cyclic Prefixed OQAM-OFDM And Its Application To Single-Carrier FDMA Pseudorandom Bit Generation Using Coupled Congruential Generators An Efficient Implementation Of Floating Point Multiplier High-Speed Low-Power Viterbi Decoder Design For TCM Decoders A Very Fast And Low Power Carry Select Adder Circuit High Speed ASIC Design Of Complex Multiplier Using Vedic Mathematics Technique Of LFSR Based Test Generator Synthesis For Deterministic And Pseudorandom Testing

23 24 25 26 27 28

29 30 31

32 33 34 35 36

37 38 39 40 41 42 43

44

45

Adder Designs using Reversible Logic Gates A Pipeline VLSI Architecture For High-Speed Computation Of The 1-D Discrete Wavelet Transform Image Edge Detection Based On FPGA FPGA Implementation of Fast Block LMS Adaptive Filter Using Distributed Arithmetic for High Throughput. FPGA-based for Implementation of Multi-Serials to Ethernet Gateway. A Novel Error-Tolerant Method in AES for Satellite Images.

46 47

48 49 50

For More Details visit: www.vedlabs.com