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JawaharlalNehruEngineeringcollege

Laboratory Manual

DIGITAL COMMUNICATION For Third Year Students


Author JNEC, Aurangabad

FOREWORD It is my great pleasure to present this laboratory manual for second year engineering students for the subject of digital Communication keeping in view the vast coverage required for visualization of concepts of basic coding techniques. As a student, many of you may be wondering with some of the questions in your mind regarding the subject and exactly that has been tried to answer through this manual. Faculty members are also advised that covering these aspects in initial stage itself, will greatly relieve them in future, as much of the load will be taken care by the enthusiastic energies of the students, once they are conceptually clear.

Prof. J.B.BOTHE

LABORATORY MANUAL CONTENTS This manual is intended for the Third year students of Electronics & telecommunication Branch in the subject of Digital Communication. This manual typically contains Practical/Lab Sessions related to digital Communication Covering various aspects related the subject to enhance understanding of the subject. Students are advised to thoroughly go through this manual rather than only topics mentioned in the syllabus, as practical aspects are the key to understanding conceptual visualization of theoretical aspects covered in the books.

Good Luck for your Enjoyable Laboratory Sessions.

Prof. J.B.Bothe Author

SUBJECT INDEX 1.Dos and Donts

2.Lab Exercises. 1. To study sampling of a signal and its reconstruction. 2. 3. 4. 5. 6. 7. To study amplitude shift keyed (ASK generation and detection. To study Frequency shift keyed (FSK) generation and detection. To study phase shift keyed (PSK)generation and detection . Generation of PCM signals and recovery of information. To study delta modulation. To study (TDM) and recovery of two bandlimited signals of PAM signals. 8. 9. To study DPSK generation and detection. To study QPSK generation.

3. 4. 5.

Quiz on the subject Conduction VivaVoce Examination Evaluation and Marking Systems

DOsandDONTsinLaboratory:
1. Do not handle any equipment before reading the instructions/Instruction manuals. 2. Read carefully the power ratings of the equipment before it is switched on whether ratings 230 V/50 Hz or 115V/60 Hz. For Indian equipments, the power ratings are normally 230V/50Hz. If you have equipment with 115/60 Hz ratings, do not insert power plug, as our normal supply is 230V/50 Hz, which will damage the equipment. 3. Observe type of sockets of equipment power to avoid mechanical damage. 4. Do not forcefully place connectors to avoid the damage. 5. Strictly observe the instructions given by the teacher/Lab Instructor.

InstructionforLaboratoryTeachers::
1. Submission related to whatever lab work has been completed should be done during the next lab session. 2. The promptness of submission should be encouraged by way of marking and evaluation patterns that will benefit the sincere students.

EXPERIMENTNO.1
AIM:
To study sampling of a siganl and its re-construction.

THEORY:
SAMPLING FREQUENCY: The 6.4 MHz Crystal oscillator generates the 6.4 MHz clock. The decade counter divides the frequency by 10 and the ripple counter generate the basic sampling frequencies - 320KHz to 20 KHz and the other control frequencies. The basic sampling frequencies is given to a multiplexer For each "Press" on the frequency select switch, the output of the state counter increases by one and it counts from 000 to 100. As the state counter counts from 000 to 100, the corresponding input of the multiplexer is switched to the output. As soon as the count reaches 101, the output of the 3 to 8 decoder resets the state counter and the whole cycle repeats. Also LED connected to the output of the decoder is switch ON, which indicates the sampling frequency selected. Refer the truth table for better understanding.

EQUIPMENTS:
Analog Signal Sampling & Reconstruction Kit, 20 MHz Dual Trace Oscilloscope,Patch Chords

PROCEDURE:
1. 2. 3. 4. 5. 6. 7. Connect power supply in proper polarity to the kit & switch on. Connect the lKHz,5V pp Sinewave signal, generated onboard, to the ANALOG INPUT, by means of the patch-cords provided. Connect the sampling frequency signal in the internal mode, by means of the shorting pin provided. Using switch SW1 select 50% duty cycle as shown in the table. Connect the SAMPLE OUTPUT to the input of the 2nd Order Low Pass Filter. Using frequency selector switch, select desired sampling frequency. The selected sampling frequency is indicated by the glowing LED. Take observation as mentioned below for various sampling frequency: 32 KHz, 16KHz, 8KHz, 4KHz , 2KHz.

OBSERVATIONS:_
Observe the following waveforms in order for every setting and plot it on the paper. a. 1 KHz Analog Input waveform. b. Sampling frequency waveform. c. Sampled Signal and corresponding reconstructed output of 2nd order Low Pass Filter. d. Sample and Hold signal and corresponding reconstructed output of 2nd order Low Pass Filter.

6.4MHZ CLOCK

DECADE COUNTER

BINARY COUNTER

MUL TI PLEXER

BCD COUNTER

4BIT COMPA RA TER

ST TE A COUNTER FREQUENCY SELECTSW ITCH

D E C O D E R

DUTYCYCLE SELECTION SW ITCH

LA TCH

SAM PLING SIGNALOUTPUT (INTERNAL)

BLOCKDIAGRAMFORSAMPLINGCONTROLLOGICE

SETTINGFOREXPERIMENT 2
DUTYCYCLESELECTIONSW ITCH

SW1 1 2 3 ON 50% 4

SAM PLINGSIGNALSELECTIONJUM PER

EXTERNAL

INTERNAL

DUTYCYCLE50% SAMPLINGFREQUENCYfs.2KHz 6Vp.p

(1) 1Khz.5Vp.p. ANALOGI/p

(2)

2KHz,5Vp.p. SAMPLINGFREQUENCY DUTYCYCLE50%

(3)

(5)

SUPPLIEDSIGNALO/P (4) (5)

O/POF2NDORDERLPF

SAMPLE&HOLDO/P

O/POF4THORDERLPF

FIGURENO.IIB DUTYCYCLE50% SAMPLINGFREQUENCYfs..8KHz 6Vp.p

(1) 1Khz.5Vp.p. ANALOGI/p

(2)

6KHz,5Vp.p. SAMPLINGFREQUENCY DUTYCYCLE50%

(3)

(5)

SUPPLIEDSIGNALO/P (4) (5)

O/POF2NDORDERLPF

SAMPLE&HOLDO/P

O/POF4THORDERLPF

CONCLUSION:
From the above observations we conclude that as the Sampling Frequency is increased, the reconstructed output is less distorted and almost original signal is reconstructed. For a sampling frequency of 2KHz, only 2 samples of the 1KHz signal are taken whereas that for a sampling frequency of 8KHz, 8 samples of 1KHz signal are taken. Hence, as the number of samples taken of the signal increases, the distortion of the reconstructed signal decreases. As per the Nyquist Criterion atleast two samples are required for the reconstruction of the signal. If the Nyquist Criterion is not satisfied, or if the signal is not band-limited, then spectral overlap, called "aliasing" occurs, causing higher frequencies to show up at lower frequencies in the recovered message, and specially in voice transmission intelligibility is seriously degraded Thus, universally for the voice band (300Hz to 3300Hz), the sampling frequency used is 8KHz, which satisfies the Nyquist Criterion.

ExperimentN0.2

AIM:
To study Amplitude Shift Keyed generation and detection.

INSTRUMENTS:
Bread board , 1C 555 ( 2 ), 74LS08, Resistors capacitors as per requirement, C.R.O. , etc.

THEORY:

Intro to Generation of ASK


Amplitude shift keying - ASK - in the context of digital communications is a modulation process, which imparts to a sinusoid two or more discrete amplitude levels. These are related to the number of levels adopted by the digital message. For a binary message sequence there are two levels, one of which is typically zero. Thus the modulated waveform consists of bursts of a sinusoid. Figure 1 illustrates a binary ASK signal (lower), together with the binary sequence which initiated it (upper). Neither signal has been bandlimited.

There are sharp discontinuities shown at the transition points. These result in the signal having an unnecessarily wide bandwidth. Bandlimiting is generally introduced before transmission, in which case these discontinuities would be rounded off. The bandlimiting may be applied to the digital message, or the modulated signal itself. The data rate is often made a sub-multiple of the carrier frequency. This has been done in the waveform of Figure 1. One of the disadvantages of ASK, compared with FSK and PSK, for example, is that it has not got a constant envelope. This makes its processing (eg, power

amplification) more difficult, since linearity becomes an important factor. However, it does make for ease of demodulation with an envelope detector. As already indicated, the sharp discontinuities in the ASK waveform of Figure 1 imply a wide bandwidth. A significant reduction can be accepted before errors at the receiver increase unacceptably. This can be brought about by bandlimiting (pulse shaping) the message before modulation, or bandlimiting the ASK signal itself after generation.

Figure 3 shows the signals present in a model of Figure 2, where the message has been bandlimited. The shape, after bandlimiting, depends naturally enough upon the amplitude and phase characteristics of the bandlimiting filter.

Intro to Demodulation
It is apparent from Figures 1 and 4 that the ASK signal has a well defined envelope. Thus it is amenable to demodulation by an envelope detector. With bandlimiting of the transmitted ASK neither of these demodulation methods (envelope detection or synchronous demodulation) would recover the original binary

sequence instead, their outputs would be a bandlimited version. Thus further processing - by some sort of decision-making circuitry for example - would be necessary. Thus demodulation is a two-stage process: 1. recovery of the bandlimited bit stream 2. regeneration of the binary bit stream

PROCEDURE :
1) For carrier frequency 10 KHz and modulation

multivibrators using 1C 555 2) Connect the circuit as per design then connect outputs of 1C 555 to the AND inputs 3) Observe the output at AND output .

RESULT:
Draw the observed waveform.

CONCLUSION:
In ASK modulation scheme the output contains carrier or zero signal for the presence of logic ( high) or logic 0 (low) respectively.

EXPERIMENTN0.3
AIM:
To study Frequency Shift Keying Generation/Detection

THEORY:
In Frequency Shift Keying modulation techniques, the modulated output shifts between two frequencies for all 'one' to 'zero' transitions. The carrier frequency chosen for FSK modulation are 2MHz and 1MHz . Note that the above frequencies are greater than twice the modulating frequency. CARRIER GENERATOR block on DCL-005 generates the carrier waves 2MHz and 1 MHz which are available at SIN1 and SIN2 post. The FSK modulator is also built around the 2 to 1 Analog Multiplexer which switches between the 2MHz and 1MHz signals for all 'one' to 'zero" transitions. FSK DEMODULATOR employs a PLL logic for the recovery of data, The digital phase locked loop CD4046BE forms the heart of this logic. The PLL center frequency and lock range are fixed around 2 MHz . So whenever the 2 MHz signal is transmitted, the phase detector output of the PLL goes high and whenever the I MHz signal is transmitted, then the phase detector output goes low. Thus the phase detector output at the PLL directly gives the detected data.

EQUIPMENTS
1. Data Conditioning And Carrier Modulation Transmitter Kit 2. Data Re-Conditioning And Carrier De-Modulation Receiver Kit 3. 20MHz Dual Trace Oscilloscope. 4. Patch Chords

PROCEDURE
1. Connect power supply in proper polarity to the kit DCL-005 and DCL-006 and switch on. 2. Connect S-CLOCK and S-DATA generated on DCL-005 to CODING CLOCK and INPUT DATA respectively by means of the patch-chords provided 3. Connect the NRZ-L data input to the CONTROL INPUT of the Carrier Modulator logic. 4. Connect carrier component SIN1 to INPUT-1 and SIN2 to the INPUT-2 of the Carrier Modulator logic.

CARRIER GENERA TOR

SIN1

SIN2

SIN3

SCLOCK CLOCK CODING LOGIC INPUT 2 NRZL FSK MODULA TOR INPUT 1 M ODULA TED FSK OUTPUT FSK I/P DA A T FSK DEM ODULA TOR O/P

D T A A SIMULA TOR LOGIC

SDA A T

INPUT

DA A T

CONTROL INPUT

BLOCKDIAGRAMFOR FERQUENCY SHIFTKEYINGM ODULA TIONTECHNIQUES

CLOCK

CARRIER SIN1

CARRIER SIN2

INPUT NRLL

FSK M ODLA TED O/P

FSK DEMODULA TED O/P

FREQUENCYSHIFTKEYINGTECHNIQUES

5.connect FSK modulated signal MODULATED OUTPUT on DCL-005 to the FSK


I/P of the FSK Demodulator on DCL-006.

6.Observe various waveform as mentioned


OBSERVATION:

below.

Observe the following waveforms on CRO and plot it on the paper.

ON KIT DCL-005
1. 2. 3. 1. 2. Input NRZ-L Data at CONTROL INPUT Carrier frequency SIN-1 and SIN2. FSK modulated signal at MODULATED OUTPUT ON KIT DCL-006 FSK Modulated signal at FSK I/P FSK Demodulated signal at DATA O/P.

ON KIT DCL-006
1. 2. FSK Modulated signal at FSK I/P. FSK Demodulated signal at DATA O/P.

CONCLUSION:
A small phase lag exist between the modulating data and the recovered data because of the limitation of tracking ability and the time response of PLL.

ExperimentNo.4
AIM:
To study Phase Shift Keyed generation and detection.

INSTRUMENTS:Phase Shift Keyed Generator kit, C.R.O., function generator, DMM etc

PROCEDURE:
1) Connect the mains cord to a.c. mains 2) Connect 100 Hz IV p-p sine wave signal to the input 3) Observe the output waveform of phase shifter and adjust its amplitude to 1 V with the help of adjust potentiometer . 4) Observe the PSK waveform on CRO. Trigger CRO to get Stable waveform. 5) Vary the control frequency by control frequency adjust potentiometer and observe its effect on the PSK output. .

Phase shift keyed modulator

RESULT:

1.Draw the observed waveform. 2.Record the different control frequency in the observed waveform.

CONCLUSION:
In PSK modulation scheme the output contains dc level either logic 1 ( high) or logic 0 (low) according to the input phase change.

ExperimentNo.5
AIM :Study of PCM transmission and detection

OBJECTIVE:
To study generation of PCM signal i.e. Sampling of analog signal, and its pulse code modulation in None parity mode in the transmitter section and to study the demultiplexing and the reconstruction of the analog signal in the receiver section.

THEORY:
The analog signal (sine wave) of the frequency 500 Hz and 1 KHz and variable amplitude DC Signal DC1 and DC2 are generated on board on DCL-003. These signals are fed to the input of the Sampling logic CH0 & CH1 and their samples are multiplexed by interleaving them properly in their assigned time slots. The crystal oscillator generates a clock of 6.4 MHz and from which all the transmitter data and timing signals are derived. For fast mode operation the transmitter clock is 240 KHz, and Sampling clock is 16 KHz. For slow mode operation the transmitter clock is 1.23 Hz and sampling clock is 0.088 Hz i.e. the sampling rate per channel is 11 seconds and serial data transmission rate is 813 milliseconds. The multiplexed data is Pulse Code Modulated before transmission. At the receiver after the Pulse Code Demodulation, the recovered multiplexed data is send to Demultiplexing logic. The two de-multiplexed samples are given to reconstruction unit. The reconstruction unit consists of Low Pass Filter, which filters the high frequency components to recover the original base-band signal at the receiver output CH0 and CH1.

EQUIPMENTS:
1.Pulse Code Modulation Transmitter kit. DCL-003. 2.Pulse Code De-Modulation Transmitter kit. DCO-004. 3.20 MHz Dual Trace Oscilloscope. 4.Patch chords.

PROCEDURE:
Connect power supply in proper polarity to the kit DCO-003 and switch on. Connect sine wave of frequency 500Hz and 1 KHz to the input CH0 and CH1 of the sampling and multiplexing logic. Set the speed selection switch to FAST mode. Select parity selection switch to NONE mode on both the kit DCL-003 and DCL-004. Connect PCM OUTPUT, TxCLK and Tx SYNC of the transmitter section DCL-003 to the corresponding RxDATA, RxCLOCK, and RxSYNC of the receiver section DCL-004. Ensure that no faults are introduced by FAULT SWITCH. Take the observations as mentioned below. Repeat the above experiment with DC Signal at the inputs of the Channel CH0 and CH1.

OBSERVATION:
Observe the following signal on CRO and plot it on the paper.

ON KIT DCL-003
1. Input signal CH0 and CH1.

2. Sampling Clock. 3. Multiplexed data. ON KIT DCL-004 1. De-multiplexed Data

2. Received signal CH0 and CH1 3. Sampling Clock

SWITCH SETTING FOR DCL-003 AND DCL-004 SW3 : NONE PARITY EVEN PARITY ODD PARITY HAMMING PARITY 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 1

SW1 : NONE PARITY ODD PARITY EVEN PARITY HAMMING PARITY 1 1 1 1 0 1 1 1 1 0 1 1 0 0 1 1

CONCLUSION:
The sampling clock is 16KHz satisfying the Nyquist Criteria for both 500Hz (fs=32xfm) and 1000 Hz (fs=16xfm) inputs. The multiplexed output shows the proper alignment of samples in their respective time slots. Also verify that the amplitude of the samples at any time is equal to the amplitude of the sampled signal at that instant of time. The sine waves are reconstructed without any distortion from the samples. The sine waves can be observed to have good linearity. The DC levels are also reconstructed without any distortion. The reconstruction units are second order butter-worth low pass filters. The output waveforms are exact replicas of input, except for a finite phase lag.

ExperimentNo.6

AIM:
To Study of Delta Modulation and demodulation.

THEORY:
DELTA MODULATION: Delta modulation is the differential pulse code modulation scheme in which the difference signal is encoded into just a single bit. In digital modulation system, the analog signal is sampled and digitally coded This code represents the sampled amplitude of the analog signal. The digital signal sent to the receiver through any channel in serial form. At the receiver the digital signal is decoded and filtered to the reconstructed analog signal. A sufficient number of samples are required to allow the analog signal to be re-constructed accurately. Delta modulation is a process of converting analog signal in to one bit code, means only one bit is sent per sample. This bit indicates whether the signal is larger or smaller than the previous samples. The advantage of DM is that the modulator and demodulator circuits are much simpler than those used in traditional PCM. Delta modulation is an encoding process where the logic levels of the transmitted pulses indicate whether the decoded output should rise or fall at each pulse. This is a true digital ..encoding process compared to PAM, PWM and PPM. If signal amplitude has increased in DM then modulated output is a logic level 1. If the signal amplitude has decreased the modulator output is logic level 0. Thus the output from the modulator is a series of zeroes and ones to indicate rise and fall of the waveform since the previous value. The block diagram of Delta Modulation illustrates the components at the transmitter end of channel and receiver the baseband signal a(t) and its quantized approximation i(t) are applied as inputs to the comparator. A comparator as its name suggests simply makes a comparison between inputs. The comparator has one fixed \ output c(t) when a(t) > i(t) and the different output when a(t)<i(t) The comparator output is then latched in to a D-flip/flop which is clocked by the selected transmitter clock Thus the output of the D-flip/flop is latched 1 or 0 synchronous with the clock edge. This binary data stream is transmitted to the receiver and is also fed to unipolar to bipolar converter This block converts logic '0' to positive voltage level and logic T to negative voltage level. Then unipolar to bipolar output is fed to the input of integrator. The integrator output is then connected to the negative terminal of voltage comparator. Thus completing the modulator circuit. The waveform of the Delta Modulator is as shown in the figure.

The practical use of Delta Modulation is limited due to following drawbacks: i) NOISE: A noise is defined, as any unwanted random waveform accompanying the information signal. When the signal is received at the receiver irrespective of any channel it is always accompanied by noise. ii) DISTORTION: Distortion means that the receiver output is not the true copy of the analog input signal at the transmitter. In Delta modulation, when the analog signal is greater than the integrator output the integrator ramps up to meet the analog signal. The ramping rate of integrator is constant. Therefore if the rate of change of analog input is faster than the ramping rate, the modulator is enable to catch up with the input signal. This causes a large disparity between the information signal and it's quantised approximation. This error phenomenon is known as Slope over loading and causes the loss of rapidly changing information. The slope overloading waveform is as shown in figure. The problem of slope overloading can be solved by increasing the ramping rate of the integrator. But as it can be seen from the figure the effect of the large step size is to add large sharp edges at the integrator output and hence it adds to noise. iii) Another problem of Delta Modulation is that it is enable to pass DC information. This is not a serious limitation of the speech communication. But the system like Video transmission DC level does not provide information about brightness level of the picture.

EQUIPMENTS:
1) DCL - 007 KIT. 2) 20MHz CRO with probe. 3) Connecting links

PROCEDURE:
DELTA MODULATION: 1) Connect the power supply with the proper polarity to the Kit and. turn it ON 2) Select 250Hz sine wave input of 0V through pot P8 and fed it to input buffer section. Then give buffer output to Delta modulator input. 3) Then select clock rate of 8 KHz by pressing SW1. 4) Then observe the Delta modulated output and compare it with the clock rate selected. These waveforms are as shown in figure It is half the frequency of clock rate selected 5) Observe the integrator output test point . It can be observe that as the clock rate is increased amplitude of triangle waveform decreases. This is called minimum step size. Signal approximating 250Hz. is available at the integrator

output. This signal is obtained by integrating the digital output resulting from Delta modulation. 6) Then go on increasing the amplitude of selected signal through the respective pots. It can be observed that the digital high makes the integrator output to go upward and digital low makes the integrator output to go downwards. Observe that the integrator output follow the input signal. Adjust PI2 to gate a stable waveform if required. The waveforms are as shown in the figure. Observe the various test-points in the Delta modulator section. Increase the amplitude of 250Hz sine wave through pot P8 further high and observe that the integrator output cannot follow the input signal. State the reason. Repeat the above mention procedures with different signal sources and selecting the different clock rates and observe the response of Delta Modulator.

7)

8)

Fq(t)

Fq(t)

Pi(t) C(t)

D(t)

Pe(t) F(t) a(t) Fq(t)

ExperimentNo.7
AIM:
To study Time Division Multiplexing and De-multiplexing, using Pulse Amplitude Modulation and Demodulation and to reconstruct the signals at the Receiver, using Filters.

THEORY:
This module basically consists of the following sections : a. The Onboard Function Generator, b. The Transmitter. c. The Receiver with the associated synchronization circuitry. Onboard Function Generator : This basically provides four amplitude Variable (0-5V - PP) synchronized sinewaves, each 250Hz, 500Hz, 1KHz, and 2Khz and an amplitude variable DC level (05V). The 6.4 MHz crystal oscillator generates a 6.4 MHz clock. It is divided by 2 decade counters and 2 ripple counters to get the 32KHz, 16KHz 8Khz 4 Khz frequencies. This signal is fed to serial to parallel register which generates the sine-wave by serial shift operations. The serial to shift register(IC 74LS1164) have resistive ladder network at the output. For 16 shifts of the register, one sine wave is produced. So if a 16KHz clock is fed to the shift register, 1KHz sine-wave is generated. Thus by using the clock 32Khz, 16Hz, 8Khz. 4KHz, sine wave of 2KHz, 1Khz, 500Hz, 500Hz, and 250Hz are generated respectively. The active filter at the output suppresses the ripple and also takes care of the impedance matching. DC level is regulated by the 4.7V zener. Also 32KHz clock is used as a Sampling Clock and 8KHz clock is used for Channel Identification.

Transmitter: The Transmitter Section consists of a four Analog Input Channels with 4 -pole Integrated Circuit Analog Switch, that provides Sampling and Time Division Multiplexing of each channel, using Pulse Amplitude Modulation signals. The 32KHz sampling clock is fed to the cascade of two counters. The two counters are configured in such a way that the outputs vary from 00 to 11 As the control input of the decoder varies from 00 to 11, the signal C1.C2,C3,C4 selects the channel of the analog switch (CD4016BE) and the information of that channel is transmitted. Thus TDM is achieved effectively. The unity gain amplifiers are provided to give proper impedance matching. Receiver: The Receiver Section consists of a 4 pole Analog Switch, that demultiplexes the 4 Channels and the reconstruction unit. The receiver timing logic is very similar to the transmitter timing logic. The demultiplexer based on the control signals CO, Cl, C2, C3 assigns the information to the corresponding channels. The success of the demultiplexer operation is fully dependent on how exactly, RXCHO, RXCH1, RXCH2, RXCH3 signals match with the TXCHO, TXCH1, TXCH2, TXCH3 signals. Thus, to ensure the proper demultiplexing, the two dividers are reset by the RXCHO signals which corresponds with the TXCHO. The demultiplexed signals are then given to foe corresponding reconstruction units. The signal reconstruction unit is a 4th order Active Low Pass Filter provided for each receiver channel They filter out the sampling frequency and their harmonics from the demultiplexed signal and recover the base band by en integrate action. The cut-off frequency of the 4th Order Low Pass Filter is 3.4KHz.

EQUIPMENTS:
1. TDM Pulse Amplitude Modulation and Demodulation Kit. 2. 20 Mhz Dual Trace Oscilloscope 3. Patch Chords.

PROCEDURE:
1. 2. Connect power supply in proper polarity to the kit & switch on. Connect the 250HZ, 500Hz, 1KHz, and 2KHz sinewave signal to the multiplexer input channel CHO, CH1,CH2, CH3.by moans of the patch-cords provided. Connect the multiplexer output TXD of the transmitter section to the demultiplexer input RXD of the receiver section

3.

4.

5. 6.

Connect the sampling clock TX CLK and Channel Identification Clock TXCHO of the transmitter section to & corresponding RX CLK and RX CHO of the receiver section respectively. Set the amplitude of the input sine wave as desire. Take observations as mentioned below.

(a)

(c)

(c) Figure(1)Pulseamplitudemodulation(a)Signal(b)double polarityP AM(c)SinglepolarityP AM>

1 2Ts

Ts (a) f2(t) 2 2 1

2 (b) TIME SLO T1 1 N 2 2Ts 0 3 2 Figure2:Tim edivisionmultiplexingofnaturalsampledmessage. Pulsetrainsof:(a)message1,(b)m essage2and(c)themultiplexedtrain. GU ARD TIME 1 2

FRAME

OBSERVATIONS:
Observe the following waveforms on CRO and plot it on the paper. a. Input Channel CHO, CH1, CH2, CH3 b. Channel Selection Signal CO,Ci,C2,C3 c. Sampling Clock TX CLK and RX CLK. d. Channel Identification Signal TX CHO. And RXCHO e. Multiplexer Output TXD f. Demultiplexer Input RXD g. Reconstructed signal CHO, CHK CH2, CH3.

CONCLUSION:
In this experiment, the transmitter clock and the channel identification clock are directly linked to the receiver section Hence transmitter and receiver are synchronize and proper reconstruction of the signal is achieved.

ExperimentNo.8
AIM:
To study DPSK generation and detection.

THEORY:
Differentially-Encoded Phase-Shift Keying A form of PSK that can act as its own synchronous reference for detection Purposes is differentially-encoded phase shift keying, hereafter referred to simply as DPSK. To accomplish this process, the digital signal is first converted to either NRZ-M or NRZ-S. The signal at the receiver is delayed by one bit width and multiplied by itself. The result is the original base band digital signal. In the presence of noise, the error rate is slightly higher than BPSK since errors tend to occur in pairs. DPSK Generation A circuit that can be used to generate DPSK is shown in the following fig. The NRZ-L signal is first converted to NRZ-S format in this particular implementation. The EXCLUSIVE-NOR circuit produces a 1 when both inputs are the same and a 0 when the inputs are different. The output is delayed by one pulse width and compared with the input. We arbitrarily assume an initial value of 1 at the output.

DPSK modulator:-

DPSK Demodulator:
A method of recovering the data bit stream from the DPSK signal is shown in fig. Here the received signal and the received signal delayed by the bit time t are applied to a multiplier. o/p of multiplier is passed through low pass filter or integrator to obtain the signal transmitted.

WaveformsforDPSKgeneration.

ExperimentNo.9
AIM:
To study QPSK generation

THEORY: Quadrature Phase-Shift Keying:


We know that a data stream whose bit duration is Tb is to be transmitted by BPSK the channel bandwidth must be nominally 2Fb where Fb=1/Tb.QPSK allows bit to be transmitted using half the bandwidth. In describing th QPSK system we will use the type D flip-flop as a one bit storage device. The mechanism by which a bit stream b(t) generates a QPSK signal is shown in following fig. And relevant waveforms are also shown in the fig. fig:-

In these waveforms we have assumed that the active edge of the waveform is the Downward edge. The toggle flip-flop is driven by the clock waveform whose period is the bit time Tb. The toggle flip flop generates the odd clock waveform. These clocks have period 2Tb.The bit stream b(t)is applied as the data input to both The type D flip-flop, one driven by the odd and one driven by the even clock waveform . flip-flop register alternate bits in the bit stream b(t) and hold each such

registered bit for two bit intervals that is for a time 2Tb.Note that the bit stream

b0(t)(which is the o/p

of the flip flop driven by odd clock)registers bit 1 and holds

that bit for time period 2Tb.The even bit stream The bit stream

be(t)holds , for times 2Tb each.

be(t) is superimposed on a carrierPs cos W0 t and the bit stream

b0(t ) is superimposed on carrier Ps sin W0 t by the use of two multipliers to


generate two signals. These signals are then added to generate the transmitted o/p signal which is Vm(t)=(Ps

b0(t ) cos W0 t)+( Ps be(t)

sin W0 t)

WAVEFORMS:

QUIZ
DIGITAL COMMUNICATION Chapter 1: 1. Give the statistical averages of random variables.,

2. Explain the functions of random variables. 3. What are the types of random variables? Explain. 4. Give and explain the probability distributions models for random variables. 5. Explian following in detail. a) Binomial distribution b) Gussian distribution c) Poisson distribution

6. What is mean by stochastic process and stationary stocahstic process? 7. Give the statstical averages for stochastic process. 8. Explain power density spectrum for stochastic process. Chapter 2 (Digital transmission of analog signals) 1. State & prove sampling Theorem, Explain sampling process in detail. 2. State a prove sampling Theorem in Time Domain what is its practical application. 3. What are the different techniques used for sampling? 4. Explain uniform sampling theorem for band pass signals. 5. Explain ideal sampling and reconstruction of low pass signals.. 6. Distinguish between ideal and practical sampling.? 7. The signal X(t)=10 cos (60 t) cos2(160 t) is sampled at the rate of 400 samples per second. Determine the range of permissible frequencies for the ideal reconstruction filter that may be used to recover X(t) from the sampled version.

8. Find the Nyquist rate and Nyquist interval for the following signals i. m(t)=1/2 cos (4000 t) .cos (1000t)

ii. m(t)= (sin(500 t))/ t

Chapter 3(Digital coding of analog waveforms) 1. 2. 3. With neat block diagram explain DPCM system transmitter and receiver. With neat Block diagram, explain DM system transmitter and receiver. Write short notes on :

a)DPCM b) Quantization Noise. 4. What is quantization ?Explain uniform and nonuniform quantization. 5. Write short note on Pulse Code Modulation (PCM). 6. write short notes on a)uniform quantization b) nonuniform quantization 7. Explain the basic principle of Differential pulse code modulation (DPCM)in

detail. 8. 9. 10. 11. Explain the working of delta modulator. What is campanding? Explain time division multiplexing. Explain the T1 (TDM)digital multiplexing scheme in detail.

Chapter 4: Intersymbol interference and its cures. 1. Discuss the intersymbol interference.Discuss the measures taken in order to reduce ISI. 2. Explain correlative level coding. 3. Give and explain the block diagram of baseband binary data transmission system. 4. Explain in detail the M-Ary signalling scheme. 5. What is the solution for removal of ISI? explain Raised cosine spectrum in detail.

Chapter 5: Introduction to Spread Spectrum Techniques. 1. Explain the necessity of spread spectrum modulation. 2. What are pseudo noise sequences? Why they are used in spread spectrum modulation. 3. How spread spectrum methods are classified? What is the basis of classification? 4. Explain with block diagram direct sequence spread spectrum techniques. 5. Explain the operation of frequency hop spread spectrum technique with the help of block diagram. 6. Explain the difference between fast frequency hopping and slow frequency hopping. 7. Give the advantages and disadvantages of direct sequence and frequency hop spread spectrum techniques. 8. List the applications of spread spectrum techniques.

4.ConductionofVivaVoceExaminations:
Teacher should oral exams of the students with full preparation. Normally, the objective questions with guess are to be avoided. To make it meaningful, the questions should be such that depth of the students in the subject is tested Oral examinations are to be conducted in co-cordial environment amongst the teachers taking the examination. Teachers taking such examinations should not have ill thoughts about each other and courtesies should be offered to each other in case of difference of opinion, which should be critically suppressed in front of the students.

5.Evaluationandmarkingsystem:
Basic honesty in the evaluation and marking system is absolutely essential and in the process impartial nature of the evaluator is required in the examination system to become popular amongst the students. It is a wrong approach or concept to award the students by way of easy marking to get cheap popularity among the students to which they do not deserve. It is a primary responsibility of the teacher that right students who are really putting up lot of hard work with right kind of intelligence are correctly awarded. The marking patterns should be justifiable to the students without any ambiguity and teacher should see that students are faced with unjust circumstances.

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