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i. ii. Explain schematic design using CPLD Explain function clocks (wave form) in digital computer.
iii. Use schematic CPLD to simulate digital output for SR, D, master slave and JK flip-flop. iv. Design shift register using flip-flop JK.
0 1 0 1
0 0 0 0 0 1
1 0 1 1 1 1
Input S 1 0 0 0 1 1 0 R 0 0 1 0 0 1 0 Q 1 1 0 0 1 0 0
Output Operation
Q
0 0 1 1 0 1 1 Set Hold Reset Hold Set Invalid Hold
INPUT S 1 0 0 0 1 1 0 R 0 0 1 0 0 1 0 Q 1 1 0 0 1 0 0
JK FLIP FLOP
INPUT S 1 0 0 0 1 1 0 R 0 0 1 0 0 1 0 Q 0 1 1 1 0 0 1
OUTPUT Q 1 0 0 0 1 1 0
D FLIP FLOP
CLK J 1 0 0 1 0 0 0
INPUT K 0 0 1 1 0 1 0 Q 1 1 0 1 1 0 0
OUTPUT Q 0 0 1 0 0 1 1
MASTER SLAVE
CLK
Input S 0 0 1 1 0 0 0 R 0 1 0 1 0 0 1 Q 1 1 1 1 X 1 1
Output Q 1 1 1 1 X 1 1 Y 1 1 0 X 1 1 1 1 0 1 X 1 1 0 Y
Operation
QUESTION.. 1. Basic Flip-flop I. Draw the logic circuit for an unclocked NOR gate flip-flop.
II.
Enter the expected timing diagram for signals Q and Q' in Figure 26.
IV.
V.
Enter the expected timing diagram for signals Q and Q' in Figure 27.
2. Master Slave Flip-flop i. Draw the logic circuit implemented with gates for the SR master-slave flipflop in Figure 24. Use NOR gate flip-flops.
ii.
Enter the expected timing diagram for the signals Y, Y', Q, and Q' in Figure 28.
3. Edge triggered flip-flop i. Draw the logic circuit for the D-type positive-edge triggered flip-flop in Figure 5.
ii.
Enter the expected timing diagram for the signals S, R, Q, and Q' in Figure 29.
CONCLUSION What we can conclude in this practical lab ,we be able to explain the schematic design using CPL. After that ,we be able to explain the function clocks(waveform) in digital computer. Then , we can use the schematic CPLD to stimulate digital output for SR flip-flop,D flip-flop ,Master Slave flip-flop and JK flip-flop . More than that ,we know how to design shift register using flip-flop JK . We learn that a digital system can be represented at different levels of abstraction . This keeps the description and design of complex system manageable.Lastly, we managed to understand that the highest level of abstraction is the behavional level that describes a system in terms of what it does(or how it behaves) rather than in terms of its components and interconnection between them.