Study Report

On

VHDL
And

Field Programmable Gate Arrays

Submitted By Siddhartha Kumar B.Tech Undergraduate Student, NITK Surathkal

I would like to thank Professor Kuruvilla Varghese, CEDT Department, IISc, for giving me this opportunity to work under his guidance and support, and for providing the facilities to learn.

Acknowledgement

Objective
The objective of the study of programmable logic, VHDL and implementation on an FPGA, is to understand the advantages of Hardware Descriptive Language and Programmable logic over a system that uses a Processor to run a program. It is to allow one to understand how ASICs designed and how actual logic arrays are implemented to perform simple to complex processing tasks.

Introduction
VHDL:- VHSIC hardware description language, is a hardware description language used to design digital and mixed signal systems such as field programmable gate arrays( FPGAs) and integrated circuits. VHDL is used to write text models that describe a logic circuit. It is then simulated by a Simulation program, which is used to test the model. The model then can be synthesised and implemented as an ASIC or on an FPGA. The difference between a software language like C and VHDL is that, VHDL describes actual hardware, implementation has to take in to account of the restrictions of the hardware provided. Also while executing or simulating the code one has to take into consideration that in a hardware description the processes are executed in parallel unlike the sequential flow in a software language. One has to understand that when a VHDL model is translated into the gates and wires that are mapped into a programmable logic device such as CPLD or FPGA then it is actual hardware being configured and not a code being executed on a processor chip. The advantages of VHDL is that it allows us to model an ASIC device before actually constructing one it allows us to simulate it and understand the behaviour of the device. Also as VHDL is concurrent system unlike the sequential glow of C or BASIC, it allows for much faster execution. VHDL is a very portable language and can be used to describe any logic system the same VHDL code can be ported on to any device.

FPGA:- Field Programmable Gate Arrays, is an integrated circuit designed to be configured by the customer after manufacture multiple times. The configuration is done using a Hardware Description Language. FPGAs can be used to implement any logic design. The FPGA is made of several programmable logic blocks, which are present as slices. These slices contain Look-up Tables, Flip Flops, Multiplier Circuits and Multiplexers. By programming each of these slices and connecting them in a certain fashion one can implement and logic design. The Look-Up Tables are essentially small memory blocks that allow one to store a truth table. Using the address lines as input and output signals one can configure any truth table into these LUTs. These along with the multiplexers allow us to configure any Combinational Logic Block. The Flip Flops allow us to combine the CLBs with the sequential circuit and allow us to program any Sequential Logic Block, like shift registers, counters, Finite State Machines etc. The Multiplier, usually a 16 x 16 multiplier, allows us to perform simple arithmetic operations quickly, without implementing our own adder and multiplier. As one can see there is a lot of flexibility in programming an FPGA, to perform the same task we can go through many channels and this allows us to really optimize on time and real estate that we require to perform the required task, and this the real advantage of FPGAs over microcontrollers, though FPGA programming is a more tedious and long process.

Tasks Completed
Binary Multiplier: Implemented a multiplier using a shift registers and a finite state machine. Drew the Level 0 and Level 1 diagram of the multiplier, and designed the finite state machine, was able to reduce the number of states to 3 in the Finite State Machine. Modelled the design the in VHDL and simulated it using the Xilinx ISE. Also implemented the code on the Xilinx Spartan 3E FPGA on the starter kit board with hardcoded input values. Binary Divide: Designed a Divider using shift registers and a finite state machine. Drew the level 0 and level 1 diagrams of the divider, and designed the state machine. Used a 2s complement adder for subtraction and comparison. Implemented the same design in VHDL, simulated and synthesised the design and performed timing analysis on the simulated model. Implemented the code on the Xilinx Spartan Starter Kit, by giving the 4 bit divisor input from the switches and getting the output on the 8 LEDs. Binary Non Restoring Divider : Designed a Non Restoring dividers FSM and Block diagram, drew the Level 0 and Level 1 block diagram on paper.

VHDL: Learnt the syntax of VHDL and implemented simple logic codes like adders and shift registers. Then performed simulations using test benches, and verified the results. Implemented codes for dividers, clock dividers, multipliers etc., and simulated the models in ISim using test benches. Then performed Implementation steps, analysed timing constraints and performed post-route simulation. Also analysed the RTL Schematic and the Technical Schematic, to understand how the circuits are modelled and implemented on the FPGA. Made the Users Constraint Files for the programs that were implemented on the Starter Kit. Clock Divider and BCD Counter: Designed a 50 Mhz Clock divider to give a 1Hz output to a BCD counter that counted up to 99. Ran all three counters on the same 50 Mhz clock but controlled the increment via an enable bit. Implemented this simple circuit on the Xilinx Starter kit and viewed the display on the LEDs. Made a start switch, which was implemented as latch to latch on to the start signal once given by the push button. Modified the Circuit to make the counter up-down and implement a hold switch to hold the value displayed. For both Switches for Up-Down and Hold, a switch de-bouncer was implemented to avoid any false samples. Keyboard Interface: Designed a FSM on the FPGA to take ASCII values from a keyboard input through a PS/2 port and display it in binary on the LEDS. This required the study of how a keyboard transmits data. A Keyboard has two output signals one is the Keyboard Clock and Keyboard Data. The Keyboard Clock is signal that is always high till a key is pressed, once a key is pressed it starts to clock at 20 to 30 KHz. When the Key is pressed the keyboard data stream transmits a bit at every falling edge of the keyboard clock. The data stream is as follows, first the start bit which is 0 and the scan code of the key pressed, an odd parity bit and a high stop bit. This is in an ideal situation, usually we keep the key pressed for at least a few seconds before releasing it. In this case the scan code is transmitted every 100milliseconds before the key is released. On the release of the key, an F0 code is transmitted , followed by the scan code, parity bit and Stop bit. Thats why when reading the values from a keyboard it is read after the release of the key. The FSM reads the keyboard data stream at every falling edge of the keyboard clock, and fills a temporary shift register with this data, then it checks for the F0 code. When this code is read it stores the next 8 bits and displays it as the scan code. This program was implemented on the Xilinx starter kit and was successfully tried out.

Conclusion
By completing these simple tasks, I have now gained an understanding about programmable logic and implementation of Hardware Descriptive Language. I have understood how digital systems work, and how they are implemented as ASICs. I am now interested to use this knowledge and further studies, to design ASICs and VHDL models for Digital Signal Processing and other applications.