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PIC18MICROCONTROLLER {Interrupts} {I }
MohamadFauziZakaria http://fkee.uthm.edu.my/mfauzi

Interrupts vs. Polling vs


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Interrupt method: The microcontroller stops whatever it is doing upon receiving an interrupt signal and serves the device. The program associated with the interrupt is called the interrupt service ( ) p routine (ISR) or interrupt handler. Polling method: The microcontroller continuously monitors the status of a given device; when the status condition is met it met, performs the service. The advantage of interrupts: microcontroller can serve many devices which each device can get the attention based on the priority. Interrupts are used to avoid tying down the microcontroller. The polling method cannot assign priority because it checks all devices in a round-robin fashion.

Interrupt S i Routine I t t Service R ti


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For every interrupt, there must be an interrupt service routine (ISR), or iinterrupt h dl t t handler. The microcontroller gets the address of ISR form interrupt vector table. g p In the PlC18, there are only two locations for the interrupt vector table, locations 0008h (High Priority Interrupt) and 0018h (Low Priority Interrupt). Sources of Interrupts (most widely used)
Timers (0 3) ( ) External INT0 (RB0), INT1 (RB1), and INT2 (RB2) ADC PORTB-Change Interrupt g p Two interrupts of Serial Comm. (USART) CCP

Interrupt R i t I t t Registers
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Therearetenregisterswhichareusedtocontrol interruptoperation.Theseregistersare:
INTCON,INTCON2,andINTCON3:INTERRUPTCONTROL , , REGISTER PIR1andPIR2:PERIPHERALINTERRUPTREQUEST(FLAG) PIR1 and PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER PIE1andPIE2:PERIPHERALINTERRUPTENABLEREGISTER PIE1 and PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER IPR1andIPR2:PERIPHERALINTERRUPTPRIORITYREGISTER RCON:RESETCONTROLREGISTER RCON: RESET CONTROL REGISTER

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Enabling and disabling an interrupt


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Upon reset, all interrupts are disabled (masked) The t Th iinterrupts must b enabled ( t t be bl d (unmasked) by software in order for the k d) b ft i d f th microcontroller to respond to them. INTCON Register

PICI8 interrupt programming in C


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C18 does not place an ISR at the interrupt vector table automatically. Use Assembly language instruction instr ction GOTO at the interrupt vector to transfer control to the ISR.

#pragma code high_vector =0x0008 // High-priority interrupt addr void high_vector(void) { _asm GOTO my_isr _endasm } #pragma code // End of code #pragma interrupt my isr //interrupt is reserved keyword p g p y_ p y void my_isr (void) //used for high-priority interrupt { //C18 places RETFIE here automatically due to //interrupt keyword }

Programming Timer I t P i Ti Interrupts t


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Interrupt Timer0 Timer1 Timer2 Timer3

Flag Bit TMR0IF TMR1IF TMR2IF TMR3IF

Register INTCON PIR1 PIR1 PIR3

Enable Bit TMR0IE TMR1IE TMR2IE TMR3IE

Register INTCON PIE1 PIE1 PIE2

External Hardware Interrupts E t lH d I t t


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Interrupt INT0 (RB0) INT1 (RB1) INT2 (RB2)

Flag Bit INT0IF INT1IF INT2IF

Register INTCON INTCON3 INTCON3

Enable Bit INT0IE INT1IE INT2IE

Register INTCON INTCON3 INTCON3

Negative edge-triggered interrupts


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Upon power-on reset, INT0, INT1, and INT2 are in positive (rising) edgetriggered interrupts interrupts. To make any of them a negative (falling) edge-triggered interrupt, we must program the INTEDGx (where x can be 0 1, or 2) in INTCON2 register 0, 1 register.

PORTB-Change Interrupt
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The PORTB (RB4 -RB7) can cause an interrupt when any changes are detected on any one of them. Widely used in KEYPAD Interfacing

Comparison C i
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INT0 INT2 Has independent pin Has its own interrupt flag Each interrupt pins can be configured to negative or p g positive edge g

PORTB-Change PORTB Ch Uses all four pins and considered as a single interrupt pin pin. A single flag for the PORTB-Change interrupt All pins could cause an interrupt if occur status changing from H-L or L-H. g g

Interrupt Priority
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Upon power-on reset, all interrupts are automatically designated as high priority and will go to address 00008H. This is done to make the PlC18 compatible with the earlier generation of PlC microcontrollers such as PlC16xxx. We can make the PlC18 a two level priority system by way of programming the two-level IPEN (interrupt priority enable) bit in the RCON register.

Interrupt Priority Selection


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To make the PlC18 a two-level priority system, we must first set the IPEN bit to HIGH. Then, we can assign a low priority to any of the interrupts by programming the bits called IP (interrupt priority).

Register in IPR1

Interrupt Priority Selection


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All the PlC18 interrupts can be assigned a low or high priority level, except the external hardware interrupt of INTO. To set the priority, we have to make IPEN =1. Then, set two bits of GIEH (also referred as GIE) and GIEL in INTCON:
GIEH = 1 Th GIEH bit iis the same as GIE which used in previous section. 1. The th hi h di i ti GIEL = 1. This will enable all the interrupts whose IP = 0 (low priority).

Low and High priority Interrupt programming in C


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Interrupt High-priority Low-priority Low priority

ROM Location 0x0008 (Default) 0x0018 (Selected with IP bit)

C18 keyword interrupt interruptlow

Example: //used for high-priority #pragma interrupt test1 void test1 (void) { } //used for low-priority #pragma interruptlow test2 void test2 (void) { }

3 Condition for Interrupt Inside an Interrupt


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When a high-priority interrupt is vectored into address 0x0008, the GIE bit is disabled (GIEH = 0), thereby blocking another (high or low-priority) interrupt from coming in. During the return from ISR, the GIE (GIE = 1) enabled automatically, which allows others interrupts to come in again. If we want to allow another high-priority p g , interrupt to come in during the execution of the current ISR, we must make GIE = 1 at the beginning in the current ISR. When a low-priority interrupt is vectored into address 0x0018, the GIEL bit is disabled (GIEL = 0), thereby blocking another low-priority interrupt from coming in. During the return from ISR, the GIEL (GIEL=1) enabled automatically, which allows low priority low-priority interrupts to come in again. Notice that the low priority interrupt cannot again low-priority block a high-priority interrupt from coming in during the execution of the current lowpriority ISR because GIEH is still set to high (GIEH=1). When two or more interrupts have the same priority level, they are serviced according to the sequence of the program them in the interrupt vector table.

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