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Freeha Azmat, 2Nazar Abbas Saqib, Sara Shakil Qureshi, and 2Sadia Rehman

A Secure, Configurable and Customized Multimode Bulk Encryptor

Department of Electrical Engineering, School of Electrical Engineering and Computer Sciences, National University of Sciences (NUST), Sector H-12, Islamabad, Pakistan. {nazar.abbas, sara.shakil, sadia.rehman}@seecs.edu.pk
2

Department of Computer and Software Engineering, Bahria University, Sector E-8, Islamabad, Pakistan. freehaazmat@bahria.edu.pk

AbstractThis paper describes the indigenous development of a secure, inter-department Bulk Encryption Unit in enterprise network systems, which is a special purpose device for securing the data communication between two parties in a VPN/ enterprise network. It is a hardware which will help organizations, institutes and enterprises to protect data against eaves-droppers and will protect sensitive information against unauthorized access. The services provided by encryption equipment can be summarized as data security, traffic flow security and authentication. The equipment provides information and communication security by encrypting/ decrypting data over E1 links in the tactical area. It operates in duplex traffic working mode at transmission rates over 2 Mbps. It is a very flexible encryption unit that supports direct key loading via Key Gun device. Key management and authentication is controlled by the configuration module which allows only authorized users to program the device and change keys.
Keywords - encryption/ decryption; security; remote configuration; cryptographic engine, Bulk Encryption Unit (BEU)

I.

INTRODUCTION

Layer 2 (Data Link layer) of OSI model offers high speed/ high-bandwidth and virtually zero latency to network and it operates one layer below the network. The security at Layer 2 provides an effective solution to protect converged voice, video and data applications over Wide Area Networks (E1/ T1 links etc) to large number of government and commercial enterprise customers. Bulk Encryption devices at layer 2 are independent of protocol changes and network configurations, therefore simpler and less expensive to manage [5] as shown in Figure 1.

Our proposed Bulk Encryption Unit (BEU) is a special purpose device for securing converged voice, video and data applications on E1/ T1 links. It is comprised of several modules: a line interface unit (LIU) to de-frame and frame incoming and outgoing bit streams respectively; a Crypto Card to encrypt/ decrypt data on both sending/ receiving ends; a Key-Gun module to generate, store and transfer keys to all BEUs in the same network and a configuration module which provides an application that allows only an authenticated user to access the BEUs and send the key references to change the key for all BEUs simultaneously. Configuration module also ensures the synchronization among all BEUs. In this paper we present a compact design by integrating LIU and a Crypto Card of BEU in a single FPGA that avoids circuit delays due to wiring overheads as well as compatibility issues due to interfacing of various modules from different vendors. The Key-gun module is separately designed to generate a set of random keys at the centralized location and then to transfer them through a serial interface to all BEUs. The correctness of our design is verified for E1 links. It fulfils all timing requirements and in addition it offers zero latency by consuming minimum hardware resources. The proposed BEU design in FPGAs provides a customized solution for securing government, military and civil applications. This is a holistic solution which includes cryptographic algorithm design, key management, access control, tamper proofing etc. The device offer customers to change encryption algorithms and other key parameters according to their own security requirements. This is one the reasons to choose FPGA platform for building customized and reliable security solutions. Several high speed implementations of security functions like Advanced Encryption Standard [3][4][12], Hash functions[11][13][14], and Key management schemes[10][15][16] can be implemented in FPGAs efficiently . The Bulk Encryptor implementation in FPGAs could be even more cost effective as its various components like source coding, framing/ deframing; encryption/ decryption and key management can be simply integrated into a single chip. It could be also simpler to introduce algorithmic and parametric changes through a local or remote control station.

Figure 1: BEUs in Network

Another question to answer is to build a new BEU design in presence of already available BEU products in the market. In fact it is due to the two main reasons. The first is that the available BEU product in the market becomes ineffective once the encryption algorithm is required to be changed/ broken. Hence, customer has to suffer in terms of cost and reliability. The proposed BEU design facilitates the companies to introduce the desired changes whenever they need. It will ensure faster repair and will save their money and efforts in buying a new product every time. In case of an algorithmic breakdown, only the encryption/ decryption algorithm needs to be replaced, rest everything remains unaffected. Moreover it is cheap as involves less hardware equipment. The rest of the paper is organized as follows. Section 2 provides a brief explanation of our proposed architecture of BEU. Performance and simulation results are presented in Section 3. Finally conclusion is drawn in Section 4. References are presented at the end. II. PROPOSED BEU ARCHITECTURE IN FPGAs The proposed BEU architecture is composed of four modules i.e. LIU, Crypto Card, Key Gun and Remote Configuration Unit. Moreover a controller to control the flow of data between these units is designed as shown in Figure 2. A short descripton of each module is provided below.

in Figure 3. In order to extract data in its proper sequence, TS0 and TS16 slots must be detected and separated. Therefore, a finite state machine has been designed to detect FAS and then to verify whether it is the actual FAS and not the data bits. To ensure FAS actual bits, FSM checks for FAS sequence thrice i.e. if same FAS will come after 192 bytes (64 bytes * 3) in ideal case, a flag FAS Detected will be high.

Figure 3: Frame Alignment Sequence (FAS) in alternate Frame

After FAS is detected, separation of TS0 and TS16th channels from data channels has been made resulting in a total of 240 data bits out of 256 frame bits. This process is called de-framing. The data is passed to Crypto Card in two chunks of 120 bits each. The values of TS0 and TS16 channels are stored into two 8-bit registers to be further used during framing process. Frame structure is produced by concatenating processed (encrypted/ decrypted) data chunks of 120 bits taken from Crypto Card and placing TS0 and TS16 channels at their right place in the frame structure. This process is called framing. C. CRYPTO CARD

Figure 2: Block Diagram of Bulk Encryption unit

A. Controller Controller is the nucleus of BEU. It controls communication of BEU with outer world, that takes place through serial interface. Controller has set of defined modes i.e. 0001 for system lock, 0010 for encryption/ decryption, 0011 for transferring keys, 0010 for framing/ deframing, 0101 for a user to access BEU remotely and 0110 for receiving key references. B. The Line Interface Unit (LIU) LIU consists of framer/ de-framer unit. De-framer means extracting the data out of E1 frame after separating special slots which are used for signaling and synchronization. The E1 frame (comprising of total of 32 bytes having data in 30 bytes) contains two special time slots; TS0 (1st time slot) and TS16 (17th time slot). The TS0 also called as Frame Alignment Sequence (FAS) which contain a fix bit pattern that is repeated in every alternate frame i.e. after 64 bytes as shown

The Crypto Card implements Advanced Encryption Standard (AES) for encrypting/ decrypting data channels. We use an iterative approach for implementing AES in FPGAs. For an iterative approach, instead of implementing n iterations of the algorithm, only a single iteration of the algorithm is implemented and n clock cycles are consumed to achieve final output as shown in Figure 4. The encryption process is presented in Figure 4, where RND0 is ARK (Add round key) step: the userkey and plain-text are added. The RND1-9 block includes the four AES steps, namely BS (Byte substitution), SR (Shift Rows), MC (Mix Columns) and ARK. Round keys are generated for all iterations of algorithm.

Figure 4: Block Diagram for AES Algorithm

A multiplexer selects RND0 output at the first cycle and then selects the latch output for RND1-9 during the next nine clock cycles [2].

D.

KEY GUN

In order to encrypt/ decrypt data, keys are required which are generated from the Key Gun module in our proposed system. Keys are generated through true random number generator by using an operational amplifier with LM555 timer in a stable mode. To avoid minimum chances of similarity the output of LM555 acts like an input to hash function (MD5). The output of MD5 detects a change of even a single bit and generates a totally different and unique output. A set of keys is generated through this process and stored into an EEPROM (Electrically Erasable Programmable Read Only Memories) through the microcontroller. The sequence of steps for key generation process is depicted in Figure 5.

For Online Security; we have designed an architecture called System Network Management Center known as SNMC in the computer of remote user. All BEUs in a network are connected to SNMC application that allows only authenticated user to access and monitor the working status and setting parameters for the BEUs. This application runs on PC of user and asks for username and password. If the username and password matches with the pattern stored in database, only then a user is allowed to access one or more BEUs in network and consequently will be able to send key references. New authorized users can be added into the system with the help of this application.

Figure7: Online Configuration via SNMC application Offline security is provided with the help of Dongle circuit in configuration unit which is shown in Figure 8. It asks for password whenever a BEU is switched on. The Bulk Encryptor starts working if correct password is provided via keypad of Dongle which matches the pattern stored in FPGA.

Figure5: Block Diagram for Key Gun

Keys once generated and stored in local memory are then transferred to memory on FPGA board via serial interface. A variable value at the address inputs of memory act as an index number to select any key for a particular session. The snapshot of key gun module and random number generator setup is provided in Figure 6.

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Figure 8: Dongle Circuit

III. PERFORMANCE RESULTS

Figure 6: (a) Implementation of Key Gun (b) Circuit for Random Number Generation

E.

CONFIGURATION UNIT

As Key Gun generates and transfers random keys to BEUs however the decision to use a particular key in the network at a specific time is made on the basis of key index which is transferred through the configuration unit. Every BEU in a network is assigned a unique code which distinguishes it from other BEUs. With the help of this unique code, we will be sending the key index to specific BEUs in the network when required. The configuration unit provides both Online and Offline security to our system.

The proposed BEU design has been implemented on Xilinx Spartan3 FPGA device (XC3S200) by using Xilinx Synthesis tool ISE 10.1. It utilizes 31/173 IOBs (17%), BRAMs 261/960(27%) and CLB slices 1873/1920(97%). Figure 9 shows simulation results of our line interface unit (LIU) where Clk is a self created clock to show the system simulation of the LIU, RxD is the data that is received serially. Fas1, Fas2 and Fas3 are declared variables which becomes high only when first, second and third FAS sequences are detected correctly. TxD (transmitting line) is a single bit variable, which will be activated once data is ready to be serially transmitted. RxD_Data is an 8 bit register, which store the values of

serially coming data from TxD line while RxD-data-ready is a single bit variable, which gets high each time when 8 bits are stored in RxD_Data and Sixteenframe is an 8 bit variable which stores the value of the TS16 so that it can be concatenated with data channels after encryption.

Figure 11 shows the SNMC application form that sends key reference. The user will be able to see this interface after proving his authentication by giving username and password. The green color in this form shows that application is connected to BEU successfully. IV. CONCLUSION In this paper we have presented a single chip FPGA implementation of Bulk Encryptor device which integrates framing/ de-framing for line coding, encryption/ decryption, storage for keys and an interface for Offline or Online configuration of security parameters through a remote station. The system also implements a secure mechanism to access the BEU device and also to configure the security parameters remotely for high density secure data communication applications. That is a cost effective solution as it uses the smallest and cheapest FPGA chip (Spartan 3). That is a kind of application which well suits to applied re-configurable computing where features like algorithmic modifications and updating of keys can be easily incorporated. The future work includes those strategies by which the chances of eavesdropping the network in the middle to get key references will be minimized. V. REFERENCES
Arturo Diaz Perez, N.A.Saqib, Francisco Rodriguez-Henriquez and Cetin Kaya Koc. Cryptographic Algorithms on Reconfigurable Hardware. Springer science (2006). 2. T.Good and M.Benaissa.: AES on FPGA from the Fastest to the smallest. InJ.R Rao and B.Sunar. Cryptographic Hardware and Embedded Systems-CHES 2005 7th International Workshop, Edinburgh, UK, August 29 september1, 2005, Proceedings, Volume 3659 of lecture Notes in Computer Science, pages 427-440. Springer, 2005. 3. J. Zambreno, D.Nguyen, and A.Choudhary, Exploring Area/Delay Trade-offs in an AES FPGA Implementation. In Proc. Of Field Programmable Logic and Applications (FPL, volume 3203 of lecture Notes in Computer Science, pages 575-585. Springer-Verlag, 2004. 4. Layer 2 Network Security on different layers , http://www.thalesesec.com/Products/Layer1and2link.shtml 5. National Institute of Standards and Technology. NIST Special Publication 800-57, Recommendation for Key management Part -1: General, August 2005. 6. NIST. FIPS 186-3, Digital Signature Standard DSS. Federal Information Processing Standards Publication, 186-3, march 2006. http://csrc.nist.gov/publications/drafts/. 7. F.X.Standaert, G.Rouvroy, J.J.Quisquater, and J.D.Legat, Efficient Implementation of Rijindael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs. In C.D. Walter, C.K.Koc and C.Paar, editors, Cryptographic Hardware and Embedded Systems-CHES 2003, 5th International Workshop, Cologne, Germany, September 8-10 2003, Proceedings, volume 2779 of lecture notes in Computer Science, pages 334-350 Springer, 2003. 8. NIST, FIPS 186-2: Digital Signature Standard DSS. Federal Information Processing Standards Publication 186-3, March 2006, http://csrc.nist.gov/publications/drafts/. 9. RSA Laboratories. The Public Key Cryptography Standards (PKCS), June 2002, http://www.rsasecurity.com/rsalabs/node.asp?id=2124. 10. Merkle R.C., One Way Hash Functions and DES, Proceedings of CRYPTO89, Springer-Verlag, LNCS 435, 1989, PP. 428-446. 11. Damgard,I.B, A design Principle for Hash Functions, Proceedings of CRYPTO89, Springer-verlag, LNCS 435, 1989, pp 416-427. 1.

Figure 9: LIU simulation Results

The simulation results of our encryption/ decryption module has been shown in Figure 10.

Figure 10: Crypto Card Simulation Results

The encryption starts when key load signal ld is low and the signal reset rst is high. When encryption process finishes, the signal done will be high. text_in is the input signal of 128 bits which undergoes 10 rounds of encryption and produces text_out of 128 bits at the positive edge of done signal.

Figure 11: SNMC application running on PC