System Software

Introduction to System Software

Kuldeep Sharma ,Assistant Professor, CSED, Chitkara University, Himachal Pradesh
1

System Software
Application software
used by end-user

System software
text editor, compiler, debugger machine dependent A system software programmer must know the target machine structure

www.chitkara.edu

Basic Features and Design Options

Fundamental features

regardless of what machine is being used. Major design options

a software designer needs to be aware of the available options in order to make intelligent decisions

www.chitkara.edu

System Software and Machine Architecture

Machine dependent system software
Machine code Instruction formats Addressing mode Registers

Machine independent system software

Code optimization General design and logic of an assembler

www.chitkara.edu

System Software

Simplified Instructional Computer

Kuldeep Sharma ,Assistant Professor, CSED, Chitkara University, Himachal Pradesh
5

The Simplified Instructional Computer (SIC)

SIC is a hypothetical computer that includes the hardware features most often found on real machines Two versions of SIC
standard model XE version

The two versions have been designed to be upward compatible.

www.chitkara.edu.in

SIC Machine Architecture - 1

Memory

8-bit bytes 3 consecutive bytes form a word 215 bytes in the computer memory
Registers(each register is 24 bits in length)
Mnemonic Number Special use A 0 Accumulator; used for arithmetic operations X 1 Index register; used for addressing L 2 Linkage register; JSUB PC 8 Program counter SW 9 Status word, including CC
7 www.chitkara.edu.in

SIC Machine Architecture - 2

Data Formats Integers are stored as 24-bit binary numbers; 2s complement used for negative values No floating-point hardware

Instruction Formats
opcode (8) x address (15)

Addressing Modes
Mode Direct Indexed
8

Indication x=0 x=1

Target address calculation TA=address TA=address+(X)

www.chitkara.edu.in

SIC Machine Architecture 3

Instruction Set load and store: LDA, LDX, STA, STX, etc. integer arithmetic operations: ADD, SUB, MUL, DIV, etc. comparison: COMP conditional jump instructions: JLT, JEQ, JGT subroutine linkage: JSUB, RSUB Input and Output Input and output are performed by transferring 1 byte at a time to or from the rightmost 8 bits of register A The Test Device (TD) instruction tests whether the addressed device is ready to send or receive a byte of data Read Data (RD) Write Data (WD)
9 www.chitkara.edu.in

SIC Programming Examples

10

www.chitkara.edu.in

SIC Programming Examples

Data movement
No memory-memory move instruction 3-byte word: LDA, STA, LDL, STL, LDX, STX 1-byte: LDCH, STCH Storage definition WORD, RESW BYTE, RESB

11

www.chitkara.edu.in

SIC Programming Examples

Arithmetic
Arithmetic operations are performed using register A, with the result being left in register A Looping (TIX) (X)=(X)+1 compare with operand set CC

12

www.chitkara.edu.in

SIC/XE
SIC is upwards compatible with SIC/XE. Memory arranged in bytes (Max = 220 bytes).

Can do floating point arithmetic.

Has more registers. Has additional addressing modes.

Can do I/O in parallel with computation.

Registers
Mnemonic 3 4 5 6 Register B S T F Comment Base Register (for addressing) General Purpose Register General Purpose Register Floating point Accumulator (48-bits)

Data Formats
SIC/XE supports integers and characters in the same manner as SIC.

Introduces new 48-bit floating point type.

1-bit sign bit 11-bit exponent 36-bit fraction

Floating point format in SIC/XE

0 <= fraction <=1 Exponent is unsigned. Range = (0 2047) Subtract 1024 from exponent to get correct value. Value of any float will be. Fraction * (2exponent-1024) The sign of the number will be determined by the sign bit

Instruction Formats
Number of addresses is larger. (220 as compared to 215). Some instructions do not require operands.

Format 1:
Format 2: Format 3: Format 4:

Op (1 byte) Op (1 byte) R1 R2

Op (6 bit)
Op (6 bit)

n i x b p e
n i x b p e

Disp (12 bit)

Address(20 bit)

Formats (contd)
n=1, i=0: The word at the target address is the address of the operand. n=0,i=1: The address is used as the operand. n=i: value at address is taken as operand. (backward compatibility with SIC when used in Format 3)

x=0,1: enables/disables Indexed mode (as in SIC).

Formats (contd)
b=1,p=0: Implies Base Relative Mode . b=0,p=1: Implies Program Counter Relative Mode.

e determines whether mode 3 or mode 4 is in use.

e=0: Mode 3 is in use. e=1: Mode 4 is in use.

Addressing Modes
Base Relative: b=1, p=0
Target Address = B + disp

Program Counter Relative: b=0,p=1

Target Address = PC+disp

If b=p=0, then the address/disp field is taken as the address. Indexed addressing may be used with both these modes (x=0,1).

Instructions
Instructions to Load/Store new registers
LDB, STB,

Floating point Arithmetic

ADDF, SUBF, MULF, DIVF

Register Instructions
ADDR, SUBR, MULR, DIVR, RMO

I/O instructions
TIO, SIO, HIO

SIC/XE Machine Architecture

Input/Output SIO, TIO, HIO: start, test, halt the operation of I/O device .

data movement
immediate addressing for SIC/XE Looping (TIXR) (X)=(X)+1 compare with register specified set CC

22

www.chitkara.edu.in

SIC Programming Example

23

www.chitkara.edu.in

SIC Programming Example

24

www.chitkara.edu.in

SIC Programming Example

25

www.chitkara.edu.in

SIC Programming Example

26

www.chitkara.edu.in

System Software

Complex Instruction Set Computers

Kuldeep Sharma ,Assistant Professor, CSED, Chitkara University, Himachal Pradesh
27

Traditional (CISC) Machines

Complex Instruction Set Computers (CISC)
complicated instruction set different instruction formats and lengths different addressing modes e.gVAX (1978) or PDP-11(1970) from DEC(Digital Equipment Corporation) e.g. Intel x86 family

28

www.chitkara.edu.in

VAX Architecture - 1
Virtual Address EXtension
Memory

All addresses are byte address

word (2bytes), longword (4bytes), quadworad (8bytes), octaword (16bytes)

All VAX programs operate in a virtual address space of 232 bytes

One half is used for system space The other half is called process space, and is defined for each program

VAX Architecture - 2
16 general purpose registers: R0~R15 each register is 32-bit long R15 (PC): Program Counter R14 (SP): Stack Pointer R13 (FP): Frame Pointer R12 (AP): Argument Pointer R6~R11: general R0~R5: are used by some instructions PSL: process status longword

Registers

Data Formats
Integers: byte, word, longword, quadword, or octaword Negative integers: 2s complement representation

Floating-point: 4~16bytes
packed decimal: (C:positive, D:negative, F:unsigned)
4 4 4 4 4 S

zoned decimal: (digits are represented with ASCII codes)

0011 4 0011 4 S 4

e.g. +53842, 53842C (packed), 35333834C2 (zoned) e.g. -6071, 6071D(packed), 363037D1

numeric format: trailing numeric, leading separate numeric

VAX Architecture - 4
Instruction Formats
variable -length instruction format

Addressing Modes
register mode register deferred mode autoincrement and autodecrement modes several base relative addressing modes program-counter relative modes indirect addressing mode (called deferred modes) immediate operands

VAX Architecture -5
Instruction Set
Goal: symmetric with respect to data type The instruction mnemonics are formed by a prefix that specifies the type of operation a suffix that specifies the data type of the operands a modifier that gives the number of operands involved e.g. ADDW2, MULL3, CVTWL

A single instruction for

saves a designated set of registers passes a list of arguments to the procedure maintains the stack, frame, and argument pointers sets a mask to enable error traps for arithmetic operations

VAX Architecture -6 Input and Output

I/O device controllers Each controller has a set of control/status and data registers, which are assigned locations in the physical address space (called I/O space) No special instructions are required to access registers in I/O space The association of an address in I/O space with a physical register in a device controller is handled by the memory management routines

Pentium Pro Architecture - 1

Memory
physical level: byte addresses, word, doubleword logical level: segments and offsets The segment/offset address specified by the programmer is translated into a physical address by the x86 MMU (Memory Management Unit)

Pentium Pro Architecture - 2

Registers
General-purpose registers:( 32-bit Long) EAX, EBX, ECX, EDX: data manipulation ESI, EDI, EBP, ESP: address Special-purpose registers: EIP: pointer to next instruction FLAGS: status word CS: code segment register 16-bit segment registers CS contains the currently executing code SS: stack segment register SS contains address of current stack segment DS, ES, FS, and GS: Addresses of data segments Segment Registers are used to locate segments in memory Floating-point unit (FPU): it contains eight 80-bit data registers Registers reserved for system programs

Pentium Pro Architecture - 3

Data Formats
Integers: 8-, 16-, 32-bit binary numbers negative values: 2s complement FPU can also handle 64-bit signed integers The least significant part of a numeric value is stored at the lowest-numbered address (little-endian) binary coded decimal (BCD) unpacked: 0000____0000____0000____...0000____ packed: |____|____|____|____|____|____|..|____|____| Floating-point data formats single-precision: 32 bits=24+7-bit exponent+sign bit double-precision: 64 bits=53+10-bit exponent+sign bit extended-precision: 80 bits=64+15-bit exponent+sign bit

Pentium Pro Architecture - 4

Instruction Formats

prefix (optional) containing flags that modify the operation of instruction specify repetition count, segment register, etc. opcode (1 or 2 bytes) operands and addressing modes

Addressing Modes

TA=(base register)+(index register)*(scale factor)+displacement base register: any general-purpose registers index register: any general-purpose registers except ESP scale factor: 1, 2, 4, 8 displacement: 8-, 16-, 32- bit value eight addressing modes

Pentium Pro Architecture - 5

Instruction Set

400 different machine instructions

R-to-R instructions, R-to-M instructions, M-to-M instructions immediate values,

special purpose instructions for high-level programming language

entering and leaving procedures, checking subscript values against the bounds of an array

Input is performed by instructions that transfer one byte, word, or doubleword from an I/O register EAX Repetition prefixes allow these instructions to transfer an entire string in a single operation

Input and Output

System Software

Reduced Instruction Set Computers

Kuldeep Sharma ,Assistant Professor, CSED, Chitkara University, Himachal Pradesh
40

RISC Machines
instruction standard, fixed instruction format single-cycle execution of most instructions memory access is available only for load and store instruction other instructions are register-to-register operations a small number of machine instructions, and instruction format a large number of general-purpose registers a small number of addressing modes

RISC system

RISC Machines

Three RISC machines SPARC family PowerPC family

Cray T3E

UltraSPARC - 1
Sun Microsystems (1995) SPARC stands for scalable processor architecture SPARC, SuperSPARC, UltraSPARC
Memory Registers Data formats Instruction Formats Addressing Modes

UltraSPARC - 2
Byte addresses
two consecutive bytes form halfword four bytes form a word eight bytes form doubleword

Alignment
halfword are stored in memory beginning at byte address that are multiples of 2 words begin at addresses that are multiples of 4 doublewords at addresses that are multiples of 8

Virtual address space

UltraSPARC programs can be written using 264 bytes Memory Management Unit

UltraSPARC - 3
~100 general-purpose registers any procedure can access only 32 registers (r0~r31) first 8 registers (r0~r8) are global, i.e. they can be access by all procedures on the system (r0 is zero) other 24 registers can be visualized as a window through which part of the register file can be seen program counter (PC) the address of the next instruction to be executed condition code registers other control registers

Registers

UltraSPARC - 4
integers are 8-, 16-, 32-, 64-bit binary numbers 2s complement is used for negative values support both big-endian and little-endian byte orderings (big-endian means the most significant part of a numeric value is stored at the lowest-numbered address) three different floating-point data formats single-precision, 32 bits long (23 + 8 + 1) double-precision, 64 bits long (52 + 11 + 1) quad-precision, 78 bits long (63 + 16 + 1)

Data Formats

UltraSPARC - 5

Three Instruction Formats 32 bits long the first 2 bits identify which format is being used Format 1: call instruction Format 2: branch instructions Format 3: remaining instructions

UltraSPARC - 6
Addressing Modes
immediate mode register direct mode memory addressing Mode Target address calculation PC-relative* TA= (PC)+displacement {30 bits, signed} Register indirect TA= (register)+displacement {13 bits, signed} with displacement Register indirect indexed TA= (register1)+(register-2) *PC-relative is used only for branch instructions

UltraSPARC - 7
Instruction Set <100 instructions pipelined execution while one instruction is being executed, the next one is fetched from memory and decoded delayed branches the instruction immediately following the branch instruction is actually executed before the branch is taken special-purpose instructions high-bandwidth block load and store operations special atomic instructions to support multi-processor system

UltraSPARC - 8

Input and Output

a range of memory locations is logically replaced by device registers

each I/O device has a unique address, or set of addresses

no special I/O instructions are needed

PowerPC Architecture - 1
History POWER stands for Performance Optimization with Enhanced RISC
IBM (1990) introduced POWER in 1990 with RS/6000 IBM, Apple, and Motorola formed an alliance to develop PowerPC in 1991 The first products were delivered near the end of 1993 Recent implementations include PowerPC 601, 603, 604

PowerPC Architecture - 2
Memory halfword, word, doubleword, quadword may instructions may execute more efficiently if operands are aligned at a starting address that is a multiple of their length virtual space 264 bytes fixed-length segments, 256 MB fixed-length pages, 4KB MMU: virtual address -> physical address

PowerPC Architecture - 3

Registers
32 general-purpose registers, GPR0~GPR31 FPU condition code register reflects the result of certain operations, and can be used as a mechanism for testing and branching Link Register (LR) and Count Register (CR) are used by some branch instructions Machine Status Register (MSR)

PowerPC Architecture -4
Data Formats integers are 8-, 16-, 32-, 64-bit binary numbers 2s complement is used for negative values support both big-endian (default) and littleendian byte orderings three different floating-point data formats single-precision, 32 bits long (23 + 8 + 1) double-precision, 64 bits long (52 + 11 + 1) characters are stored using 8-bit ASCII codes

PowerPC Architecture - 5

Seven Instruction Formats 32 bits long the first 6 bits identify specify the opcode some instruction have an additional extended opcode the complexity is greater than SPARC fixed-length makes decoding faster and simple than VAX and x86

PowerPC Architecture - 6
Addressing Modes immediate mode, register direct mode memory addressing Mode Target address calculation Register indirect TA=(register) Register indirect with indexed TA=(register-1)+(register-2) Register indirect with TA=(register)+displacement {16 bits, signed} immediate indexed branch instruction Mode Target address calculation Absolute TA= actual address Relative TA= current instruction address + displacement {25 bits, signed} Link Register TA= (LR) Count Register TA= (CR)

PowerPC Architecture- 7
Instruction Set 200 machine instructions more complex than most RISC machines e.g. floating-point multiply and add instructions that take three input operands e.g. load and store instructions may automatically update the index register to contain the justcomputed target address pipelined execution more sophisticated than SPARC branch prediction

PowerPC Architecture - 8

Input and Output

two different modes direct-store segment: map virtual address space to an external address space normal virtual memory access

Cray T3E Architecture - 1

Cray Research, Inc. (1995) Massively parallel processing system (MPP)

Scientific computing
T3E
16~2048 processing elements (PE) three-dimensional network each PE consists of a DEC Alpha EV5 RISC microprocessor, local memory, and performanceaccelerating control logic

Cray T3E Architecture - 2

Local Memory
64MB ~ 2GB physically distributed, logically shared memory byte, word, longword, quadword 64-bit virtual addresses

Cray T3E Architecture - 3

32 general-purpose registers, GPR0~GPR31 32 floating-point registers, F0~F31 F31 always contain the value zero program counter PC other status and control registers

Registers

Cray T3E Architecture - 4

Data Formats
two different types of floating-point data formats one for compatibility with VAX the other for IEEE standard formats characters are stored using 8-bit ASCII codes since there are no byte load or store operations, characters that are to be manipulated separately are usually stored one per longword

Cray T3E Architecture - 5

Five Basic Instruction Formats 32 bits long the first 6 bits identify specify the opcode some instruction have an additional function field

Cray T3E Architecture- 6

Addressing Modes immediate mode, register direct mode memory addressing Mode Target address calculation PC-relative TA=(PC)+displacement {23 bits, signed} Register indirect with TA=(register)+displacement {16 bits, signed} displacement register indirect with displacement mode is used for load and store operations and for subrountine jumps PC-relative mode is used for conditional and unconditional branches

Cray T3E Architecture - 7

Instruction Set
130 machine instructions
no byte or word load and store instructions

System Software

CISC vs RISC
Kuldeep Sharma ,Assistant Professor, CSED, Chitkara University, Himachal Pradesh
66

CISC
Complex Instruction Set Computer

Large number of complex instructions

Low level Facilitate the extensive manipulation of low-level computational elements and events such as memory, binary arithmetic, and addressing.

CISC Examples
Examples of CISC processors are the System/360(excluding the 'scientific' Model 44), VAX, PDP-11, Motorola 68000 family Intel x86 architecture based processors.

Pros
Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory:"LOAD" and "STORE are incorporated in instructions Small code sizes, high cycles per second

Transistors used for storing complex instructions

Cons
That is, the incorporation of older instruction sets into new generations of processors tended to force growing complexity.

Many specialized CISC instructions were not used frequently enough to justify their existence. Because each CISC command must be translated by the processor into tens or even hundreds of lines of microcode, it tends to run slower than an equivalent series of simpler commands that do not require so much translation.

The CISC Approach

MULT 2:3, 5:2

RISC
Reduced Instruction Set Computer Small number of instructions instruction size constant bans the indirect addressing mode retains only those instructions that can be overlapped and made to execute in one machine cycle or less.

RISC Examples
Apple iPods (custom ARM7TDMI SoC) Apple iPhone (Samsung ARM1176JZF) Palm and PocketPC PDAs and smartphones (Intel XScale family, Samsung SC32442 - ARM9) Nintendo Game Boy Advance (ARM7) Nintendo DS (ARM7, ARM9)

Sony Network Walkman (Sony in-house ARM based chip)

Some Nokia and Sony Ericsson mobile phones

Pros
Emphasis on software
Single-clock, reduced instruction only Register to register:"LOAD" and "STORE are independent instructions Low cycles per second, large code sizes

Spends more transistors on memory registers

The RISC Approach

LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A

Performance

Performance
The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.