5.

Analog-to-Digital (AD) Conversion[G-1, J-2, W-2]

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Note that the currents owing in the resistors are kept constant since the digital input diverts the current either to ground or to the input (virtual ground) of the operational amplier functioning as a current-to-voltage converter.

5.2 Analog-to-Digital (AD) Conversion[G-1, J-2, W-2]

An analog-to-digital converter (ADC) takes an unknown analog input signal, most often a voltage Vx , and converts it into an N -bit binary number D representing the ratio of Vx to the converters full-scale voltage VF S . Most ADCs use a DAC to vary the reference voltage Vr and use a logic circuit including one or more comparators to deteremine one of the 2 N possible binary numbers D = d1 d2 d N (di s: binary coefcients) which can represent the unknown voltage Vx . The reference voltage Vr can have 2 N different values as Vr = VF S
N i=1

di 2i

(5.2.1)

where VF S is the DC reference voltage. The basic difference in converters consists in how to vary Vr to determine the binary coefcients di s such that the error |Vx Vr | is minimized.

5.2.1 Counter (Stair-Step) Ramp ADC

The counter ramp ADC illustrated in Fig. 5.2(a) starts to increment the N -bit counter value from zero by one per clock period on the SOC (start of conversion) pulse till the reference voltage Vr exceeds the unknown input voltage Vx .
Analog input Vx Clock pulse Vr of period 1/fc N-bit DAC +
AND

Comparator Inverter EOC (End of conversion)

Vx Vr t SOC Tc EOC Tc t t 1/fc (b) Timing diagram t

VFS

N-bit Counter

D = d 1d 2 d N SOC Digital output (Start of conversion) (a) Block diagram 1 : One clock period (f : the clock frequency) c fc

Analog input Vx Reference voltage Vr Conversion time Digital output D

TC,1

TC,2

TC,3

TC,4

TC,5

TC,6

TC,7

TC,8

TC,9

TC,10

TC,11

Time
1001

1000

0111 0101 0101 0100 0100 0100 0101 0101

0110

(c) A typical variation of the analog input, reference voltage,digital output, and conversion time

Fig. 5.2 Counter ramp ADC

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Sampling and Reconstruction

The sequentially increasing counter output is applied to the N -bit DAC, making its output Vr go up like a staircase as depicted in Fig. 5.2(b). The reference voltage Vr is applied to the input terminal of the comparator and compared against Vx (applied to the + input terminal) by the comparator. The comparator output keeps to be 1 so that the counter will continue to increase normally till Vr exceeds Vx . When Vr Vx , the comparator output will be switched to 0 so that no further clock pulse can increment the counter value and the EOC (end of conversion) signal becomes high to tell other devices that an A/D conversion cycle is completed and the counter value represents the converted (digital) value of the unknown analog voltage Vx . Fig. 5.2(c) shows typical variations of the analog input, reference voltage, digital output, and conversion time. Some features of this converter should be noted: <Advantage> The simple hardware makes the counter ramp ADC inexpensive to implement. <Disadvantages> The conversion time is proportional to the value of Vx . In the worst case where Vx is equal to or greater than the value of the maximum binary number, i.e., Vx (1 2N )VF S , it becomes TC = 2 N / f c (2 N clock periods) (5.2.2)

where f c is the clock frequency and VF S is the full-scale DAC output voltage. The DAC output is not necessarily the closest to Vx , but the smallest just over Vx among the 2 N possible binary numbers.

5.2.2 Tracking ADC

The tracking ADC tries to improve the conversion performance by using an up-down counter with logic to force the DAC output Vr to track changes in the analog input Vx (see Fig. 5.3). Depending on whether Vr < Vx or Vr > Vx (as indicated by the comparator output), the counter value is incremented or decremented by the clock pulse so that the DAC output will alternate between two values differing by one LSB value (2N ) when Vx is constant. When the analog input Vx varies, Vr changes in the proper direction towards Vx so that Vr follows Vx . Consequently, if Vx varies slowly enough, the DAC output Vr is continuously close to Vx and the A/D converted value may be read from the counter at any time. However, if Vx varies too rapidly, the DAC output Vr will not be able to catch up with Vx quickly enough to make the counter value represent Vx closely at any time. The main drawback is the