Experiment No.

9
Aim:To study SR,D,JK Flip flop CONCEPTS
Truth table, symbol NAND & NOR gate. Combinational circuit,sequential,memory,multivibrator,latch. A flip-flop is also called a bistable mulivibrator which gives two stable states. Flip-flop is sequential circuit whose output depends on present state of input as well as on the privious histry of inputs.

Preposition:Brodaly FF are classified as FF

SR

JK

M/S JK

Layout.
Equipments:Bread Board,connecting wires, power supply,LEDs,IC 7400

SR-FF(using NOR gates)

Case I- S=0,R=0,Since 0 at the input of NOR gate has no effect on its output,the flipflop remains in present state i.e. Q remains unchanged . Thefore Q=last value(no change). Case II-S=1,R=0, this output of NOR B is low & output of NOR A is high. Therefore 1 at S input sets the flip flop Therefore Q=1. Case III- S=0,R=1, This forces NOR A output to low & NOR B output to high, Therefore Q=0 CaseIV-S=1,R=1,it is forbidden condition, because for this condition Q= =0.This Violates the basic defination at the flip flop.

Figure(A):RS flip flop using NOR gate

SR-FF(using NAND gates)

Case I- S=0,R=0,Since 0 at the inputboth the NAND gates give output Q= =1 Thefore this is forbidden condition. Case II-S=1,R=0, this forces output of NAND B to 1,input of NAND A to 1, Therefore Q=0 & =1 Case III- S=0,R=1 this gives NAND A output as 1& input B is 1, Therefore Q=1 & =0 Case IV-S=1,R=1,since 1at the input of NAND gate has no effects on its output,the FF Remains in its present state. Therefore Q equals the last value (no change).

Figure(B):RS flip flop using NAND gate

Observation table For Figure (A) INPUT S 0 0 1 1 For Figure (B) INPUT S 0 0 1 1 R 0 1 0 1 1 0 OUTPUT (Theoretical) Q OUTPUT (Practical) LED1(Q) LED2( ) R 0 1 0 1 0 1 OUTPUT (Theoretical) Q OUTPUT (Practical) LED1(Q) LED2( )

Last Value 1 0 Forbidden

Forbidden 0 1 Last Value

Result:

Conclusion:

D Flip-Flop

Observation table

INPUT clock 1 1 D 0 1

OUTPUT (Theoretical) Q

OUTPUT (Practical) LED1(Q) LED2( )

Result:

0 1

1 0

Conclusion:

JK Flip-Flop

Case-I J=K=0
When both J and K are 0, the clock pulse has no effect on the output and the output of flip-flop is same as its previous value.

Case-II J=0 ,K=1

When J=0 and K=1 the flipflop reset at positive going edge of clock pulse.

Case-III J=1 ,K=0

When J=1 and K=0 the flipflop set at positive going edge of clock pulse.

Case-IV J=K=1
When J=K=1, the flipflop toggles,i.e.goes to the opposite state at the positive- going edge of the clock pulse.In this mode, the flip-flop toggles or changes state for each occurrence of the positive going edge of the clock pulse.

Observation table

CLK J 1 1 1 1 0 0 1 1

INPUT K 0 1 0 1

OUTPUT (Theoretical) Q Last Value 0 1 1 0 Toggle

OUTPUT (Practical) LED1(Q) LED2( )

Result :

Conclusion: