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University of Birmingham
University of Birmingham
Recall . . .
Each peripheral has interrupt request line (IRQ)
instead of a program polling peripheral for completion . . . peripheral tells the CPU when it is nished
peripheral raises interrupt on its IRQ line
A
Issue read command to I/O controller
Status = Ready?
Ready
No
University of Birmingham
Notes on Interrupts
Interrupt-driven I/O requires special programming style
the programmer writes code that
1 installs a handler (subroutine) for the interrupt (IRQ) 2 initiates I/O (e.g. send write cmd to I/O controller)
CPU jumps to handler, PC saved, registers saved to stack as handler nishes, it restores registers, jumps back to PC
PC saved in special extra EPC register in MIPS execution resumes at fetch of next instr at address in PC
University of Birmingham
Things to remember . . .
interrupt checked only after an instruction nishes
University of Birmingham
with IRQ and IACK down, peripherals may assert IRQ anew
University of Birmingham
University of Birmingham
University of Birmingham
Bus
Bus
Main memory
DMA
I/O Controller
I/O Controller
I/O Controller
Disk
Graphics
Network
University of Birmingham
DMA controller
DMA controller is a mini-processor dedicated to I/O
specialises in transferring data between mem locations
includes I/O devices
the DMA unit then does the I/O and raises interrupt when nished meanwhile, the CPU goes on processing DMA controller uses system bus for transfers
exerts control over memory and other I/O devices most useful and ecient in large (block) transfers
University of Birmingham
DMA functions
University of Birmingham
Notes on DMA
DMA doesnt tie up CPU; ecient for large transfers But it is dicult to coordinate with cache memory
a copy of memory recently accessed by the CPU is cached and buered in special high-speed memory close to the CPU DMA bypasses this cache:
it is possible that the CPU will have written to memory but the data only have reached cache/buers and not yet reached main memory if DMA reads main memory it will read the old data, not the data the CPU has written conversely, DMA may have written to memory and the CPU may see the old data still in the cache
University of Birmingham
Summary
University of Birmingham