MEGA8

8 AVR
RISC
130
32 8

16 MHz 16 MIPS

8K Flash
: 10,000
Boot
Boot
512 EEPROM
: 100,000
1K SRAM

8 / ,
16 /
RTC
PWM
TQFP MLF 8 ADC
8 10 ADC
PDIP 6 ADC
8 10 ADC

USART
/ SPI

RC
/
5 : ADC Standby
I/O
23 I/O
28 PDIP ,32 TQFP ,32 MLF
2.7 - 5.5V (ATmega8L)

4.5 - 5.5V (ATmega8)
0 - 8 MHz (ATmega8L)
0 - 16 MHz (ATmega8)
4 Mhz , 3V, 25C
: 3.6 mA
: 1.0 mA
: 0.5 A
8KB
Flash
8
ATmega8
ATmega8L
2486NAVR07/04

PDIP
(RESET) PC6
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(XCK/T0) PD4
VCC
GND
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
GND
AREF
AVCC
PB5 (SCK)
PB4 (MISO)
PB3 (MOSI/OC2)
PB2 (SS/OC1B)
PB1 (OC1A)
32
31
30
29
28
27
26
25
PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
TQFP Top View
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)
24
23
22
21
20
19
18
17
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
(OC1A) PB1
(SS/OC1B) PB2
(MOSI/OC2) PB3
(MISO) PB4
9
10
11
12
13
14
15
16
(INT1) PD3
(XCK/T0) PD4
GND
VCC
GND
VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
32
31
30
29
28
27
26
25
PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
MLF Top View
1
2
3
4
5
6
7
8
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
(OC1A) PB1
(SS/OC1B) PB2
(MOSI/OC2) PB3
(MISO) PB4
9
10
11
12
13
14
15
16
(INT1) PD3
(XCK/T0) PD4
GND
VCC
GND
VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
NOTE:
The large center pad underneath the MLF
packages is made of metal and internally
connected to GND. It should be soldered
or glued to the PCB to ensure good
mechanical stability. If the center pad is
left unconneted, the package might
loosen from the PCB.
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ATmega8AVR RISC8CMOS
ATmega8 1 MIPS/MHz
Figure 1.
XTAL1
RESET
PC0 - PC6
PB0 - PB7
VCC
XTAL2
GND
PORTC DRIVERS/BUFFERS
PORTB DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
PORTB DIGITAL INTERFACE
MUX &
ADC
ADC
INTERFACE
PROGRAM
COUNTER
STACK
POINTER
PROGRAM
FLASH
SRAM
TWI
AGND
AREF
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
TIMERS/
COUNTERS
OSCILLATOR
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
OSCILLATOR
X
INSTRUCTION
DECODER
MCU CTRL.
& TIMING
CONTROL
LINES
ALU
INTERRUPT
UNIT
AVR CPU
STATUS
REGISTER
EEPROM
PROGRAMMING
LOGIC
SPI
USART
+
-
COMP.
INTERFACE
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
PD0 - PD7
3
2486NAVR07/04
AVR 32
(ALU)
CISC 10
ATmega8 :8K Flash( RWW)
512 EEPROM1K SRAM32 I/O 32
/ (T/C), / USART
10 6 (8 TQFP MLF )ADC
SPI
CPU SRAM T/C SPI
ADC CPU ADC I/O

ADC Standby
Atmel ISP Flash

ISP AVR
Flash(Application
Flash Memory)FlashFlash(Boot Flash Memory)
RWW 8 RISC CPU Flash
ATmega8
ATmega8 C
/
AVR
ATmega8(L)
2486NAVR07/04
ATmega8(L)
VCC
GND
B(PB7..PB0)
XTAL1/XTAL2/TOSC1/TOSC2
B 8 I/O
B
PB6
PB7
RC ASSR AS2 PB7..6
T/C2 TOSC2..1
B P 55 B P 22
C(PC5..PC0)
C 7 I/O
PC6/RESET
RSTDISBL PC6 I/O PC6 C
RSTDISBL PC6
P 35Table 15
D(PD7..PD0)
D 8 I/O
D
D
RESET
P
35Table 15
5
2486NAVR07/04
AVCC
AVCC A/D C (3..0) ADC (7..6) ADC

VCC ADC VCC C (5..4)
VCC
AREF
A/D
ADC7..6(TQFP MLF )
TQFPMLFADC7..6A/D 10ADC
C
C
ATmega8(L)
2486NAVR07/04
ATmega8(L)
AVR CPU
AVR CPU
Figure 2. AVR MCU

Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
Control Lines
Direct Addressing
Instruction
Decoder
Indirect Addressing
Instruction
Register
Interrupt
Unit
SPI
Unit
Watchdog
Timer
ALU
Analog
Comparator
i/O Module1
Data
SRAM
i/O Module 2
i/O Module n
EEPROM
I/O Lines
AVR Harvard
CPU
( )
Flash
32 8
ALU ALU
6 3 16
16 X Y Z
ALUALU
7
2486NAVR07/04
/
16 16 32
(Boot )
/ SPM
(PC)
SRAM SRAM
SP I/O SRAM 5
AVR
AVRI/O
I/O 64 CPU SPI

I/O 0x20 - 0x5F
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ALU
AVR ALU 32
ALU ALU 3
/
ALU
AVR SREG
Bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SREG
Bit 7 I:
I I
I RETI
I I SEI CLI
Bit 6 T:
BLD BST T BST T
BLD T
Bit 5 H:
H BCD
Bit 4 S: , S = N
S N 2 V
Bit 3 V:2
2
Bit 2 N:
Bit 1 Z:
Bit 0 C:
AVR RISC
/
8 8
8 8
8 16
16 16
Figure 3 CPU 32
9
2486NAVR07/04
Figure 3. AVR CPU

7
Addr.
R0
0x00
R1
0x01
R2
0x02
R13
0x0D
R14
0x0E
R15
0x0F
R16
0x10
R17
0x11
R26
0x1A
R27
0x1B
R28
0x1C
R29
0x1D
R30
0x1E
R31
0x1F
Figure 3
32 SRAM
X Y Z
10
ATmega8(L)
2486NAVR07/04
ATmega8(L)
XYZ
R26..R31
Figure 4
Figure 4. X Y Z
15
X
XH
XL
R27 (0x1B)
YH
YL
R29 (0x1D)
R26 (0x1A)
15
Y
R28 (0x1C)
15
ZH
ZL
7
R31 (0x1F)
0
0
R30 (0x1E)
/
AVR
SRAM
0x60 PUSH
POP RET RETI
AVRI/O8
AVR SPL SPH
Bit
15
14
13
12
11
10
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AVR CPU clkCPU
Figure 5 Harvard
1 MIPS/MHz
/ /
11
2486NAVR07/04
Figure 5.
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 6 ALU
Figure 6. ALU
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
AVR
I
PC BLB02 BLB12
P 209
P 43
RESET
INT0 0 (GICR)
IVSELFlashP 43 BOOTRST
Flash P 196
(RWW, Read-While-Write)
I
I
RETI I
1
"0"
I
12
ATmega8(L)
2486NAVR07/04
ATmega8(L)
AVR
CLI CLI
CLI EEPROM
EEPROM
in
; SREG
r16, SREG
;
cli
; EEPROM
sbi EECR, EEMWE

sbi EECR, EEWE
; SREG (I )
out SREG, r16
C
char cSREG;
cSREG = SREG;
/* SREG */
/* */
_CLI();
EECR |= (1<<EEMWE); /* EEPROM */
EECR |= (1<<EEWE);
SREG = cSREG; /* SREG (I ) */
SEI
sei
sleep ;
; : MCU
C
_SEI(); /* */
_SLEEP(); /* */
/* : MCU */
AVR 4 4
4 PC
3
MCU MCU
4
4 PC( )
SREG I
13
2486NAVR07/04
AVR ATmega8
ATmega8 AVR
ATmega8 EEPROM
Flash ATmega88KFlashAVR
1632Flash4K x 16Flash
(Boot)
Flash 10,000 ATmega8 (PC) 12

4K P 196
(RWW, Read-While-Write) P 209
SPI Flash
( LPM )
P 11
Figure 7.
$000
Application Flash Section
Boot Flash Section

$FFF
14
ATmega8(L)
2486NAVR07/04
ATmega8(L)
SRAM
Figure 8 ATmega8 SRAM

1120 I/O SRAM 96
I/O 1024 SRAM
5
R26 R31
Y Z 63
X Y Z
ATmega8 32 64 I/O 1024 SRAM
P 9
Figure 8.
Register File
Data Address Space
R0
R1
R2
...
$0000
$0001
$0002
...
R29
R30
R31
I/O Registers
$00
$01
$02
...
$001D
$001E
$001F
$3D
$3E
$3F
$005D
$005E
$005F
Internal SRAM
$0060
$0061
...
$0020
$0021
$0022
...
$045E
$045F
15
2486NAVR07/04
SRAM clkCPU Figure

9
Figure 9. SRAM
T1
T2
T3
clkCPU
Address
Compute Address
Address Valid
Write
Data
WR
Read
Data
RD
Memory Vccess Instruction
EEPROM
Next Instruction
ATmega8 512 EEPROM

EEPROM 100,000 EEPROM
P 209 SPI EEPROM
EEPROM /
EEPROM I/O
EEPROM Table 1
EEPROM
/ VCC / CPU
P 20 EEPROM EEPROM
EEPROM EEPROM
EEPROM CPU 4
EEPROM CPU 2
16
ATmega8(L)
2486NAVR07/04
ATmega8(L)
EEPROM EEARH
EEARL
Bit
15
14
13
12
11
10
EEAR8
EEARH
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15..9 Res:
Bits 8..0 EEAR8..0: EEPROM

EEPROM EEARHEEARL512EEPROMEEPROM
0 511EEAR EEPROM
EEPROM EEDR
Bit
MSB
0
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EEDR
Bits 7..0 EEDR7..0: EEPROM

EEPROM EEDR EEAR EEDR
EEAR
EEPROM EECR
Bit
EERIE
EEMWE
EEWE
EERE
R/W
R/W
R/W
R/W
EECR
Bits 7..4 Res:
Bit 3 EERIE: EEPROM

SREG I "1" EERIE EEPROM EERIE
EEWE EEPROM
Bit 2 EEMWE: EEPROM
EEMWEEEWEEEPROMEEMWE"1"4
EEWE EEPROM EEMWE "0
EEWE EEMWE 4 EEPROM
EEWE
Bit 1 EEWE: EEPROM
EEWE EEPROM EEPROM
EEWE EEPROM EEMWE EEPROM
( 3 4 )
1. EEWE
2. SPMCSR SPMEN
3. EEPROM EEAR( )
17
2486NAVR07/04
4. EEPROM EEDR( )
5. EECR EEMWE "1" EEWE
6. EEMWE 4 EEWE
CPU Flash EEPROM EEPROM
Flash (2) CPU
Flash CPU Flash (2) P
196 (RWW, Read-While-Write)
5 6 EEPROM
EEPROM EEPROM EEAR EEDR
EEPROM I
EEWE
EEWE CPU
Bit 0 EERE: EEPROM
EEREEEPROMEEPROMEERE
EEAR EEPROM EEPROM
CPU 4
EEPROM EEWE
EEPROM EEAR
EEPROM Table 1 CPU EEPROM
Table 1. EEPROM
EEPROM (CPU)
Note:
18
RC (1)
8448
8.5 ms
1. 1 MHz CKSEL
ATmega8(L)
2486NAVR07/04
ATmega8(L)
C EEPROM
Boot Loader Boot Loader
EEPROM SPM
EEPROM_write:
;
sbic EECR,EEWE
rjmp EEPROM_write
; (r18:r17)
out
EEARH, r18
out
EEARL, r17
; (r16)
out
EEDR,r16
; EEMWE
sbi
EECR,EEMWE
; EEWE
sbi
EECR,EEWE
ret
C
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* */
while(EECR & (1<<EEWE))
;
/* */
EEAR = uiAddress;
EEDR = ucData;
/* EEMWE */
EECR |= (1<<EEMWE);
/* EEWE */
EECR |= (1<<EEWE);
}
19
2486NAVR07/04
C EEPROM
EEPROM_read:
;
sbic EECR,EEWE
rjmp EEPROM_read
; (r18:r17)
out
EEARH, r18
out
EEARL, r17
; EERE
sbi
EECR,EERE
;
in
r16,EEDR
ret
C
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* */
while(EECR & (1<<EEWE))
;
/* */
EEAR = uiAddress;
/* EERE */
EECR |= (1<<EERE);
/* */
return EEDR;
}
EEPROM
EEPROM EEPROM
EEPROM
EEPROM
CPU EEPROM EEPROM (

) EEPROM
EEPROM EEPROM
CPU
EEPROM
AVR RESET BOD
BOD
I/O
ATmega8 I/O P 271

ATmega8I/OI/OI/OIN OUT
32 I/O 0x00 - 0x1F I/O
SBI CBI SBIS SBIC
IN OUT 0x00 - 0x3F SRAM
LD ST I/O 0x20
20
ATmega8(L)
2486NAVR07/04
ATmega8(L)
"0" I/O
"1" AVR
CBI SBI
CBI SBI 0x00 0x1F
I/O
21
2486NAVR07/04
Figure 10AVR
P 30
Figure 10
Figure 10.
Asynchronous
Timer/Counter
General I/O
Modules
ADC
CPU Core
RAM
Flash and
EEPROM
clkADC
clkI/O
AVR Clock
Control Unit
clkASY
clkCPU
clkFLASH
Reset Logic
Source Clock
Watchdog Clock
Clock
Multiplexer
Timer/Counter
Oscillator
External RC
Oscillator
External Clock
Watchdog Timer
Watchdog
Oscillator
Crystal
Oscillator
Low-Frequency
Crystal Oscillator
Calibrated RC
Oscillator
CPU clkCPU
CPUAVR
CPU
I/O clkI/O
I/O I/O / SPI USARTI/O

I/O
USI clkI/O
Flash clkFLASH
Flash Flash CPU
22
ATmega8(L)
2486NAVR07/04
ATmega8(L)
clkASY
/ 32 kHz
/ /
CPU XTAL
ADC clkADC
ADCADCCPUI/O
ADC
ATmega8FlashAVR
Table 2. (1)
CKSEL3..0
1111 - 1010
1001
RC
1000 - 0101
RC
0100 - 0001
Note:
0000
1. 1 0
CPU
CPU
MCU
WDT
Table 3 ATmega8
CKSEL = 0001 SUT = 10 (1 MHz RC )
Table 3.
(VCC = 5.0V)
(VCC = 3.0V)
4.1 ms
4.3 ms
4K (4,096)
65 ms
69 ms
64K (65,536)
23
2486NAVR07/04
XTAL1 XTAL2 Figure 11

CKOPT
CKOPT
XTAL2
CKOPT
CKOPT 8 MHz CKOPT 16 MHz C1

C2
Table 4
Figure 11.
C2
C1
XTAL2
XTAL1
GND
CKSEL3..1 Table 4
Table 4.
CKOPT
CKSEL3..1
(MHz)
C1 C2
(pF)
101(1)
0.4 - 0.9
110
0.9 - 3.0
12 - 22
111
3.0 - 8.0
12 - 22
101, 110, 111
1.0
12 - 22
Note:
1.
Table 5 CKSEL0 SUT1..0
24
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 5.
CKSEL0
SUT1..0
(VCC = 5.0V)
00
258 CK(1)
4.1 ms
01
258 CK(1)
65 ms
10
1K CK(2)
BOD
11
1K CK(2)
4.1 ms
00
1K CK(2)
65 ms
01
16K CK
BOD
10
16K CK
4.1 ms
11
16K CK
65 ms
Notes:
1.
2.
32.768 kHz CKSEL 1001

Figure 11 CKOPT
XTAL1 XTAL2
36 pF
SUT Table 6
Table 6.
SUT1..0
(VCC = 5.0V)
00
(1)
1K CK
4.1 ms
BOD
01
1K CK(1)
65 ms
10
32K CK
65 ms
11
Note:
RC
1.
Figure 12 Figure 12
RC f = 1/(3RC) C 22
pF CKOPT XTAL1 GND 36 pF
25
2486NAVR07/04
Figure 12. RC
VCC
NC
XTAL2
XTAL1
C
GND
CKSEL3..0 Table 7
Table 7. RC
CKSEL3..0
(MHz)
0101
0.9
0110
0.9 - 3.0
0111
3.0 - 8.0
1000
8.0 - 12.0
SUT Table 8
Table 8. RC
SUT1..0
(VCC = 5.0V)
00
18 CK
BOD
01
18 CK
4.1 ms
10
18 CK
65 ms
11
6 CK(1)
4.1 ms
BOD
Note:
26
1.
ATmega8(L)
2486NAVR07/04
ATmega8(L)
RC
RC 1.0 2.0 4.0 8.0 MHz

5V 25C Table 9
CKSEL(CKOPT)
OSCCAL RC
5V 25C 1.0 MHz 3%
www.atmel.com/avr 1%
P 211
Table 9. RC
CKSEL3..0
(MHz)
0001(1)
1.0
0010
2.0
0011
4.0
0100
8.0
1.
Note:
SUT Table 10 PB6

(XTAL1/TOSC1) PB7(XTAL2/TOSC2) I/O
Table 10. RC
SUT1..0
(VCC = 5.0V)
00
6 CK
BOD
01
6 CK
4.1 ms
6 CK
65 ms
(1)
10
11
Note:
1.
27
2486NAVR07/04
OSCCAL
Bit
/
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OSCCAL
Bits 7..0 CAL7..0:
1 MHz ( 0x00)
OSCCAL RC
Flash EEPROM
OSCCAL OSCCAL
0xFF
EEPROM Flash EEPROM Flash
10%
1.02.04.08.0 MHzTable 11
Table 11. RC
28
OSCCAL
(%)
(%)
0x00
50
100
0x7F
75
150
0xFF
100
200
ATmega8(L)
2486NAVR07/04
ATmega8(L)
XTAL1 Figure 13
CKSEL0000CKOPTXTAL1
GND 36 pF
Figure 13.
EXTERNAL
CLOCK
SIGNAL
SUT Table 12
Table 12.
SUT1..0
(VCC = 5.0V)
00
6 CK
BOD
01
6 CK
4.1 ms
10
6 CK
65 ms
11
MCU
2% MCU
/ (TOSC1 TOSC2) AVR

32.768 kHz
TOSC1
29
2486NAVR07/04
MCU AVR
MCUCR SE SLEEP
( ADC Standby ) MCUCR
SM2SM1 SM0 Table 13 MCU
4 MCU
SLEEPSRAM
MCU
TOSC XTAL AVR MCU Standby
ATmega8
P 22Figure 10 ATmega8
MCU MCUCR
MCU
Bit
SE
SM2
SM1
SM0
ISC11
ISC10
ISC01
ISC00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MCUCR
Bit 7 SE:
MCU SLEEP SE
SLEEP SEMCU
SE
Bits 6..4 SM2..0: 2 1 0
Table 13
Table 13.
Note:
30
SM2
SM1
SM0
ADC
Standby(1)
1. Standby
ATmega8(L)
2486NAVR07/04
ATmega8(L)
SM2..0 000 SLEEP MCU CPU

SPI USART ADC /
clkCPU clkFLASH
USART MCU
MCU
ACSR ACD ADC
ADC
SM2..0 001 SLEEP MCU CPU

ADC / 2
clkI/O clkCPU clkFLASH
ADC ADC
AD ADC BOD
/ 2 SPM/EEPROM
INT0 INT1 INT2 MCU ADC
SM2..0 010 SLEEP MCU

BOD INT0 INT1
INT2 MCU
MCU
P 62
CKSEL P 23
SM2..0 011 SLEEP MCU
/ 2 ASSR AS2 / 2
/ 2
MCU TIMSK SREG
I
AS2 0 MCU
clkASY
Standby
SM2..0 110 SLEEP MCU Standby

6
Table 14.
clkCPU clkFLASH clkIO clkADC clkASY
ADC
INT1 TWI
INT0
SPM/
EEPROM
ADC
X(2)
X(2)
X(3)
I/O
X
31
2486NAVR07/04
Table 14.
clkCPU clkFLASH clkIO clkADC clkASY
INT1 TWI
INT0
X(2)
Standby
(1)
Notes:
X(2)
X
X(3)
X(3)
X(3)
SPM/
EEPROM
ADC
I/O
X(2)
1.
2. ASSR AS2
3. INT1 INT0
AVR
(ADC)
ADC
ADC P 183
ADC
P
180
32
ATmega8(L)
2486NAVR07/04
ATmega8(L)
BOD
BOD BODEN
BOD
P 37 BOD
BOD ADC
P 39
P
40
I/O clkI/O ADC clkADC
P 52
VCC/2
33
2486NAVR07/04

AVR
I/O
JMP
Boot Figure 14
Table 15
I/O
MCU
SUT CKSEL P 23
ATmega8 4
VPOT MCU
RESET MCU
VBOT
MCU
Figure 14.
DATA BUS
PORF
BORF
EXTRF
WDRF
MCU Control and Status

Register (MCUCSR)
Brown-Out
Reset Circuit
BODEN
BODLEVEL
Pull-up Resistor
SPIKE
FILTER
Watchdog
Oscillator
Clock
Generator
CK
Delay Counters
TIMEOUT
CKSEL[3:0]
SUT[1:0]
34
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 15.
VPOT
(
)(1)
1.4
2.3
(
)
1.3
2.3
0.9
VCC
1.5
VRST
RESET
tRST
RESET
tBOD
VHYST
Notes:
0.1
(2)
VBOT
BODLEVEL = 1
2.4
2.6
2.9
BODLEVEL = 0
3.7
4.0
4.5
BODLEVEL = 1
BODLEVEL = 0
130
mV
1. VPOT
2. VBOT
VCC = VBOT VCC
ATmega8LBODLEVEL=1ATmega8BODLEVEL=0
BODLEVEL=1 ATmega8
(POR) Table 15 VCC

POR POR
POR VCC
VCC RESET
Figure 15. MCU RESET VCC

VCC
RESET
TIME-OUT
VPOT
VRST
tTOUT
INTERNAL
RESET
35
2486NAVR07/04
Figure 16. MCU RESET

VCC
RESET
TIME-OUT
VPOT
VRST
tTOUT
INTERNAL
RESET
36
ATmega8(L)
2486NAVR07/04
ATmega8(L)
RESET
( Table 15)
VRST( ) tTOUT MCU
Figure 17.
CC
ATmega8 BOD(Brown-out Detection)

VCCBODLEVEL2.7V (BODLEVEL
) 4.0V (BODLEVEL ) BOD
VBOT+ = VBOT + VHYST/2 VBOT- = VBOT - VHYST/2
BOD BODENBOD(BODEN)VCC
(VBOT- Figure 18) BOD VCC
(VBOT+Figure 18)tTOUTMCU
VCC Table 15 tBOD BOD
Figure 18.
VCC
VBOT-
VBOT+
RESET
TIME-OUT
tTOUT
INTERNAL
RESET
37
2486NAVR07/04
1 CK
tTOUT
Figure 19.
CC
CK
MCU
MCUCSR
MCU MCU
Bit
WDRF
BORF
EXTRF
PORF
R/W
R/W
R/W
R/W
MCUCSR
Bit 7..4 Res:

"0
Bit 3 WDRF:
0
Bit 2 BORF:
0
Bit 1 EXTRF:
0
Bit 0 PORF:
0
38
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ATmega8 ADC
ADC 2.56V
Table 16
1. BOD ( BODEN )
2. (ACSR ACBG )
3. ADC
BOD ACBG ADC
Table 16.
VBG
1.15
1.23
1.40
tBG
40
70
IBG
10
39
2486NAVR07/04
1 MHz VCC = 5V
VCC
P 41Table 17 WDR
8
ATmega8
P 38
Figure 20.
WATCHDOG
OSCILLATOR
WDTCR
Bit
WDCE
WDE
WDP2
WDP1
WDP0
R/W
R/W
R/W
R/W
R/W
WDTCR
Bits 7..5 Res:
Bit 4 WDCE:
WDE WDCE 4
WDE 1 2
WDCE
40
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Bit 3 WDE:
WDE"1WDCE"1WDE
1. WDCE WDE "1 WDE "1

2. 4 WDE "0
Bits 2..0 WDP2, WDP1, WDP0: 2, 1, 0
WDP2WDP1 WDP0
Table 17
Table 17.
WDP2
WDP1
WDP0
WDT
VCC = 3.0V
VCC = 5.0V
16K (16,384)
17.1 ms
16.3 ms
32K (32,768)
34.3 ms
32.5 ms
64K (65,536)
68.5 ms
65 ms
128K (131,072)
0.14 s
0.13 s
256K (262,144)
0.27 s
0.26 s
512K (524,288)
0.55 s
0.52 s
1,024K (1,048,576)
1.1 s
1.0 s
2,048K (2,097,152)
2.2 s
2.1 s
C WDT (
)
41
2486NAVR07/04
WDT_off:
; WDT
wdr
; WDCE WDE
in
r16, WDTCR
ori
r16, (1<<WDCE)|(1<<WDE)
out WDTCR, r16

; WDT
ldi
r16, (0<<WDE)
out WDTCR, r16

ret
C
void WDT_off(void)
{
/* WDT */
_WDR()
/* WDCE WDE */
WDTCR |= (1<<WDCE) | (1<<WDE);
/* WDT */
WDTCR = 0x00;
}
1(WDTON
)
WDE
( )
1. WDCE WDE "1 WDE "1

2. 4 WDE WDP WDCE
"0
2(WDTON
)
WDE "1
1. WDCEWDE"1WDE"1
4 WDCE "0 WDP WDE
42
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ATmega8 AVR P 12
ATmega8
Table 18.
(2)
0x000
(1)
RESET
0x001
INT0
0x002
INT1
0x003
TIMER2 COMP
/ 2
0x004
TIMER2 OVF
/ 2
0x005
TIMER1 CAPT
/ 1
0x006
TIMER1 COMPA
/ 1 A
0x007
TIMER1 COMPB
/ 1 B
0x008
TIMER1 OVF
/ 1
10
0x009
TIMER0 OVF
/ 0
11
0x00A
SPI, STC
SPI
12
0x00B
USART, RXC
USART, Rx
13
0x00C
USART, UDRE
USART
14
0x00D
USART, TXC
USART, Tx
15
0x00E
ADC
ADC
16
0x00F
EE_RDY
EEPROM
17
0x010
ANA_COMP
18
0x011
TWI
19
0x012
SPM_RDY
1. BOOTRSTMCUBoot LoaderP 196

(RWW, Read-While-Write)
2. GICRIVSELBoot
Boot
Notes:
Table 19BOOTRST/IVSEL
Boot
Table 19.
0x000
0x001
0x000
Boot + 0x001
Boot
0x001
Boot
Boot + 0x001
BOOTRST(1)
IVSEL
43
2486NAVR07/04
Note:
1. Boot P 207Table 82 BOOTRST1 0
ATmega8
0x000
rjmp
RESET
0x001
rjmp
EXT_INT0
; IRQ0
0x002
rjmp
EXT_INT1
; IRQ1
0x003
rjmp
TIM2_COMP
; Timer2
0x004
rjmp
TIM2_OVF
; Timer2
0x005
rjmp
TIM1_CAPT
; Timer1
0x006
rjmp
TIM1_COMPA
; Timer1 A
0x007
rjmp
TIM1_COMPB
; Timer1 B
0x008
rjmp
TIM1_OVF
; Timer1
0x009
rjmp
TIM0_OVF
; Timer0
0x00A
rjmp
SPI_STC
; SPI
0x00B
rjmp
USART_RXC
; USART RX
0x00C
rjmp
USART_UDRE
; UDR
0x00D
rjmp
USART_TXC
; USART TX
0x00E
rjmp
ADC
; ADC
0x00F
rjmp
EE_RDY
; EEPROM
0x010
rjmp
ANA_COMP
0x011
rjmp
TWSI
0x012
rjmp
EXT_INT2
; IRQ2
0x013
rjmp
TIM0_COMP
; Timer0
0x014
rjmp
SPM_RDY
; SPM
0x015 RESET:
ldi
r16,high(RAMEND) ;
0x016
out
SPH,r16
0x017
ldi
r16,low(RAMEND)
0x018
out
SPL,r16
0x019
sei
0x020
<instr> xxx
...
44
; RAM
...
...
ATmega8(L)
2486NAVR07/04
ATmega8(L)
BOOTRST Boot 2K GICR IVSEL
$000
;
$001
rjmp
RESET:ldi
RESET
r16,high(RAMEND);
; RAM
$002
out
SPH,r16
$003
ldi
r16,low(RAMEND)
$004
out
SPL,r16
$005
sei
$006
<instr>
;
xxx
;
.org $c01
$c01
rjmp
EXT_INT0
; IRQ0
$c02
rjmp
EXT_INT1
; IRQ1
...
...
... ;
$c12
rjmp
SPM_RDY
; SPM
BOOTRST Boot 2K
BOOTRST Boot 2K
.org 0x001
0x001
0x002
...
... .
0x014
rjmp
EXT_INT0
; IRQ0
rjmp
EXT_INT1
; IRQ1
..
rjmp
SPM_RDY
rjmp
RESET
; SPM
;
.org $c00
$c00
;
$c01
RESET:ldi
r16,high(RAMEND);
; RAM
$c02
out
SPH,r16
$c03
ldi
r16,low(RAMEND)
$c04
out
SPL,r16
$c05
sei
$c06
<instr>
;
xxx
45
2486NAVR07/04
BOOTRST Boot 2K GICR IVSEL
Boot
GICR
.org $c00
$c00
$c01
rjmp
rjmp
RESET
EXT_INT0
; Reset
; IRQ0
$c02
rjmp
EXT_INT1
; IRQ1
...
...
... ;
$c12
rjmp
SPM_RDY
; SPM
r16,high(RAMEND);
$c13
RESET: ldi
$c14
out
SPH,r16
$c15
ldi
r16,low(RAMEND)
$c16
out
SPL,r16
$c17
sei
$c18
<instr>
; RAM
;
xxx
Bit
INT1
INT0
IVSEL
IVCE
R/W
R/W
R/W
R/W
GICR
Bit 1 IVSEL:
IVSEL "0 Flash IVSEL "1
Boot Boot BOOTSZ
P 196 (RWW, Read-While-Write)
IVSEL
1. IVCE
2. 4 IVSEL IVCE 0
IVCE
IVSEL IVSEL IVCE
4 I
Boot Boot BLB02

Boot BLB12 Boot
Boot P 196 (RWW, Read-
While-Write)
46
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Bit 0 IVCE:
IVSEL IVCE IVCE IVSEL 4 IVCE
IVCE
Move_interrupts:
;
ldi
r16, (1<<IVCE)
out
GICR, r16
; boot Flash
ldi
r16, (1<<IVSEL)
out
GICR, r16
ret
C
void Move_interrupts(void)
{
/* */
GICR = (1<<IVCE);
/* boot Flash */
GICR = (1<<IVSEL);
}
47
2486NAVR07/04
I/O
I/O AVR I/O - -

SBI CBI ( / )
( / )
LED
VCC Figure 21 P 226

Figure 21. I/O
Rpu
Logic
Pxn
Cpin
See Figure
"General Digital I/O" for
Details
x n
PORTB3 B 3
PORTxn I/O P 61I/O
I/O PORTx DDRx
PINx /
PINx "1
"0 1 SFIOR PUD
I/O P 48 I/O
P 53
I/O
I/O
48
I/O Figure 22 I/O
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 22. I/O(1)
PUD
DDxn
Q CLR
RESET
WDx
Pxn
PORTxn
Q CLR
WPx
DATA BUS
RDx
RESET
RRx
SLEEP
SYNCHRONIZER
D
RPx
PINxn
Q
clk I/O
PUD:
SLEEP:
clkI/O:
Note:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
WDx:
RDx:
WPx:
RRx:
RPx:
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
1. WPx, WDx, RRx, RPx RDx clkI/O, SLEEP

PUD
DDxn PORTxn PINxn P 61I/O

DDxn DDRx PORTxn PORTx PINxn
PINx
DDxn DDxn "1 Pxn
PORTxn "1
PORTxn
PORTxn "1 ("1) (0)

( ) ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11)
({DDxn, PORTxn} = 0b01) ({DDxn,
PORTxn} = 0b10)
SFIOR PUD
({DDxn,
PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11)
49
2486NAVR07/04
Table 20
Table 20.
DDxn
PORTxn
PUD
(SFIOR)
I/O
No
(Hi-Z)
Yes
No
(Hi-Z)
No
( )
No
( )
DDxn PINxn Figure 22

PINxn
Figure 23 tpd,max
tpd,min
Figure 23.
SYSTEM CLK
INSTRUCTIONS
XXX
XXX
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
0xFF
t pd, max
t pd, min
SYNC LATCH
PINxn tpd,max
tpd,min ~ 1
Figure 24 out in
nop out SYNC LATCH
tpd
50
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 24.
SYSTEM CLK
r16
INSTRUCTIONS
0xFF
out PORTx, r16
nop
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
0xFF
t pd
51
2486NAVR07/04
B 0 1 2 3 4 7
6 7
nop
(1)
...
;
;
ldi
r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi
r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out
PORTB,r16
out
DDRB,r17
; nop
nop
;
in
r16,PINB
...
C (1)
unsigned char i;
...
/* */
/* */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* nop */
_NOP();
/* */
i = PINB;
...
Note:
1.
0 1 6 7 2 3 0
1
Figure 22 ( ) SLEEP
MCU Standby
VCC/2
SLEEP SLEEP
SLEEP P 53
(1) "
"
"1 "0
"0 1
( )
52
ATmega8(L)
2486NAVR07/04
ATmega8(L)
VCC GND
I/O Figure 25 Figure

22
AVR
Figure 25. (1)
PUOExn
PUOVxn
1
PUD
DDOExn
DDOVxn
1
Q D
DDxn
Q CLR
WDx
PVOExn
RESET
1
Pxn
Q
PORTxn
Q CLR
DIEOExn
WPx
DATA BUS
RDx
PVOVxn
RESET
DIEOVxn
1
0
RRx
SLEEP
SYNCHRONIZER
D
SET
RPx
PINxn
L
CLR
CLR
clk I/O
DIxn
AIOxn
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn:
DIEOVxn:
SLEEP:
Note:
Pxn PULL-UP OVERRIDE ENABLE

Pxn PULL-UP OVERRIDE VALUE
Pxn DATA DIRECTION OVERRIDE ENABLE
Pxn DATA DIRECTION OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP CONTROL
PUD:
WDx:
RDx:
RRx:
WPx:
RPx:
clkI/O:
DIxn:
AIOxn:
PULLUP DISABLE
WRITE DDRx
READ DDRx
READ PORTx REGISTER
WRITE PORTx
READ PORTx PIN
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
1. WPx, WDx, RRx, RPxRDxclkI/O, SLEEP

PUD
Table 21Figure 25
53
2486NAVR07/04
Table 21.
PUOE
PUOV
{DDxn, PORTxn, PUD} = 0b010
PUOV
PUOE DDxnPORTxn PUD

PUOV /
/
DDOE
DDOV
DDxn
DDOV
DDOE DDOV /
/ DDxn
PVOE
PVOV PVOE
PORTxn
PVOV
PVOE PVOV
PORTxn
DIEOE
DIEOV
DIEOE MCU (
)
DIEOV
DIEOE DIEOV / /
MCU (
)
DI
AIO
54
ATmega8(L)
2486NAVR07/04
ATmega8(L)
I/O SFIOR
Bit
ACME
PUD
PSR2
PSR10
R/W
R/W
R/W
R/W
SFIOR
Bit 2 PUD:
DDxn PORTxn ({DDxn, PORTxn} =
0b01) I/O P 49
B
B Table 22
Table 22. B
PB7
XTAL2 ( 2)
TOSC2 ( 2)
PB6
XTAL1 ( 1 )
TOSC1 ( 1)
PB5
SCK (SPI )
PB4
MISO (SPI / )
PB3
MOSI (SPI / )
OC2 (T/C2 )
PB2
SS (SPI )
OC1B (T/C1 B )
PB1
OC1A (T/C1 A )
PB0
ICP1 (T/C1 )
XTAL2/TOSC2 B, Bit 7
XTAL2 2
I/O
TOSC2 2 RC
ASSR AS2 "1 T/C2 PB7
I/O
PB7 DDB7 PORTB7 PINB7 0
XTAL1/TOSC1 B, Bit 6
XTAL1 1 ( RC )
I/O
TOSC1 1 RC
ASSR AS2 "1 T/C2 PB6
I/O
PB6 DDB6 PORTB6 PINB6 0
SCK B, Bit 5
55
2486NAVR07/04
SCKSPI DDB5
DDB5
PORTB5
MISO B, Bit 4
MISOSPI DDB4
DDB4
PORTB4
MOSI/OC2 B, Bit 3
MOSISPI DDB3
DDB3
PORTB3
OC2PB3 T/C2 PB3
OC2 PWM
SS/OC1B B, Bit 2
SS DDB2
SPI DDB2
PORTB2
OC1B PB2 T/C1 PB2
OC1B PWM
OC1A B, Bit 1
OC1APB1 T/C1 A PB1
OC1A PWM
ICP1 B, Bit 0
ICP1 PB0 T/C1
Table 23 Table 24 B P 53Figure 25 SPI
MSTR INPUT SPI SLAVE OUTPUT MISOMOSISPI MSTR
OUTPUT SPI SLAVE INPUT
Table 23. PB7..PB4
56
PB7/XTAL2/
TOSC2(1)(2)
PB6/XTAL1/
TOSC1(1)
PB5/SCK
PB4/MISO
PUOE
EXT (INTRC +
AS2)
INTRC + AS2
SPE MSTR
SPE MSTR
PUO
PORTB5 PUD
PORTB4 PUD
DDOE
EXT (INTRC +
AS2)
INTRC + AS2
SPE MSTR
SPE MSTR
DDOV
PVOE
SPE MSTR
SPE MSTR
PVOV
SCK
SPI
DIEOE
EXT (INTRC +
AS2)
INTRC + AS2
DIEOV
DI
SCK
SPI
AIO
ATmega8(L)
2486NAVR07/04
ATmega8(L)
1. INTRC RC ( CKSEL )
2. EXT RC ( CKSEL )
Notes:
Table 24. PB3..PB0
PB3/MOSI/OC2
PB2/SS/OC1B
PB1/OC1A
PB0/ICP1
PUOE
SPE MSTR
SPE MSTR
PUO
PORTB3 PUD
PORTB2 PUD
DDOE
SPE MSTR
SPE MSTR
DDOV
PVOE
SPE MSTR +
OC2
OC1B
OC1A
PVOV
SPI + OC2
OC1B
OC1A
DIEOE
DIEOV
DI
SPI
SPI SS
ICP1
AIO
C Table 25
Table 25. C
PC6
RESET ( )
PC5
ADC5 (ADC 5)
SCL ( )
PC4
ADC4 (ADC 4)
SDA ( / )
PC3
ADC3 (ADC 3)
PC2
ADC2 (ADC 2)
PC1
ADC1 (ADC 1)
PC0
ADC0 (ADC 0)
RESET C, Bit 6
RESET RSTDISBL I/O
RSTDISBL
I/O
PC6 DDC6 PORTC6 PINC6 0
SCL/ADC5 C, Bit 5
SCL TWCR TWEN 1 PC5
I/O
50 ns
PC5 ADC 5 ADC 5
SDA/ADC4 C, Bit 4
57
2486NAVR07/04
SDA TWCR TWEN 1 PC1

I/O
50 ns
PC4 ADC 4 ADC 4
ADC3 C, Bit 3
PC3 ADC 3 ADC 3
ADC2 C, Bit 2
PC2 ADC 2 ADC 2
ADC1 C, Bit 1
PC1 ADC 1 ADC 1
ADC0 C, Bit 0
PC0 ADC 0 ADC 0
Table 26 Table 27 C P 53Figure 25
Table 26. PC6..PC4
PC6/RESET
PC5/SCL/ADC5
PC4/SDA/ADC4
PUOE
RSTDISBL
TWEN
TWEN
PUOV
PORTC5 PUD
PORTC4 PUD
DDOE
RSTDISBL
TWEN
TWEN
DDOV
SCL_OUT
SDA_OUT
PVOE
TWEN
TWEN
PVOV
DIEOE
RSTDISBL
DIEOV
DI
AIO
ADC5 / SCL
ADC4 / SDA
Table 27. PC3..PC0 (1)
58
PC3/ADC3
PC2/ADC2
PC1/ADC1
PC0/ADC0
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
ADC3
ADC2
ADC1
ADC0
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Note:
1. PC4 PC5
AIO TWI
D Table 28
Table 28. D
PD7
AIN1 ( )
PD6
AIN0 ( )
PD5
T1 (T/C1 )
PD4
XCK (USART / )
T0 (T/C0 )
PD3
INT1 ( 1 )
PD2
INT0 ( 0 )
PD1
TXD (USART )
PD0
RXD (USART )
AIN1 D, Bit 7
AIN1
AIN0 D, Bit 6
AIN0
T1 D, Bit 5
T1 T/C1
XCK/T0 D, Bit 4
XCK USART
T0 T/C0
INT1 D, Bit 3
INT1 1PD3
INT0 D, Bit 2
INT0 0PD2
TXD D, Bit 1
TXDUSARTUSART
DDD1
RXD D, Bit 0
RXDUSARTUSART
DDD0 PORTD0
Table 29 Table 30 D P 53Figure 25
59
2486NAVR07/04
Table 29. PD7..PD4
PD7/AIN1
PD6/AIN0
PD5/T1
PD4/XCK/T0
PUOE
PUO
OOE
OO
PVOE
UMSEL
PVO
XCK
DIEOE
DIEO
DI
T1
XCK / T0
AIO
AIN1
AIN0
Table 30. PD3..PD0
60
PD3/INT1
PD2/INT0
PD1/TXD
PD0/RXD
PUOE
TXEN
RXEN
PUO
PORTD0 PUD
OOE
TXEN
RXEN
OO
PVOE
TXEN
PVO
TXD
DIEOE
INT1
INT0
DIEO
DI
INT1
INT0
RXD
AIO
ATmega8(L)
2486NAVR07/04
ATmega8(L)
I/O
B PORTB
B DDRB
B PINB
C PORTC
C DDRC
C PINC
D PORTD
D DDRD
D PIND
Bit
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Bit
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Bit
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PORTB
DDRB
PINB
PORTC
DDRC
PINC
PORTD
DDRD
PIND
61
2486NAVR07/04
INT0 INT1 INT0..1
MCU MCUCR
( INT0/INT1) INT0
INT1 I/O P 22
INT0/INT1
( ) I/O
MCU
MCU 5.0V 25C
1 s P 226
MCU
SUT P 22
MCU
MCU
MCU MCUCR
MCU MCU
Bit
SE
SM2
SM1
SM0
ISC11
ISC10
ISC01
ISC00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MCUCR
Bit 3, 2 ISC11, ISC10: 1 Bit1 Bit 0

SREG I 1 INT1
Table 31 MCU INT1
Table 31. 1
62
ISC11
ISC10
INT1
INT1
INT1
INT1
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Bit 1, 0 ISC01, ISC00: 0 Bit 1 Bit 0
SREG I Table 32
0 INT0 MCU INT0
Table 32. 0
GICR
ISC01
ISC00
INT0
INT0
INT0
INT0
Bit
INT1
INT0
IVSEL
IVCE
R/W
R/W
R/W
R/W
GICR
Bit 7 INT1: 1
INT1 '1 SREG I
MCU MCUCR1 1/0 (ISC11ISC10)
INT1 INT1
Bit 6 INT0: 0
INT0 '1 SREG I
MCU MCUCR0 1/0 (ISC01ISC00)
INT0 INT0
63
2486NAVR07/04
GIFR
Bit
INTF1
INTF0
R/W
R/W
GIFR
Bit 7 INTF1: 1
INT1 INTF1 SREG
I GICR INT1 1MCU
1
Bit 6 INTF0: 0
INT0 INTF0 SREG
I GICR INT0 1MCU
1 INT0
64
ATmega8(L)
2486NAVR07/04
ATmega8(L)
8 / 0
T/C0 8 /

10
Figure 268/P 2 CPU

I/O I/O P 688
/
Figure 26. 8 T/C
TCCRn
DATA BUS
count
TOVn
(Int.Req.)
Control Logic
clkTn
Edge
Detector
Timer/Counter
TCNTn
Clock Select
Tn
( From Prescaler )
= 0xFF
T/C(TCNT0) (OCR0) 8 ( Int.Req. )

TIFR
TIMSK TIFR TIMSK
T/CT0
( )T/C
T/C clkT0
n T/C
0 TCNT0 T/C0
Table 33
Table 33.
BOTTOM
0x00 BOTTOM
MAX
0xFF ( 255) MAX
T/C
T/C
T/C TCCR0 CS02:0 P 70T/C0
T/C1
8 T/C Figure 27
65
2486NAVR07/04
Figure 27.
TOVn
(Int. Req.)
DATA BUS
Clock Select
TCNTn
count
Control Logic
clkTn
max
Edge
Detector
Tn
( From Prescaler )
( )
count
TCNT0 1
clkTn
T/C clkT0
max
TCNT0
clkT0 clkT0
CS02:0 (CS02:0 = 0)
clkT0CPU TCNT0CPU ( )
66
( ) 8 (MAX
= 0xFF) 0x00 TCNT0 "0 T/C
(TOV0) TOV0 TOV0
ATmega8(L)
2486NAVR07/04
ATmega8(L)
T/C
T/C clkT0
Figure 28 T/C MAX
Figure 28. T/C
clkI/O
clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 29
Figure 29. T/C fclk_I/O/8
clkI/O
clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
67
2486NAVR07/04
8 /
T/C TCCR0
Bit
CS02
CS01
CS00
R/W
R/W
R/W
TCCR0
Bit 2:0 CS02:0:

T/C
Table 34.
CS02
CS01
CS00
T/C
clkI/O/1 ( )
clkI/O/8 ( )
clkI/O/64 ( )
clkI/O/256 ( )
clkI/O/1024 ( )
T0
T0
T/C0 T0
T/C TCNT0
Bit
TCNT0[7:0]
TCNT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
T/C 8
T/C TIMSK
Bit
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
TOIE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TIMSK
Bit 0 TOIE0: T/C0

TOIE0 I 1 T/C0 T/C0
TIFR TOV0
68
ATmega8(L)
2486NAVR07/04
ATmega8(L)
T/C TIFR
Bit
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
TOV0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TIFR
Bit 0 TOV0:T/C0
T/C0 TOV0 TOV0
1 SREG I TOIE0(T/C0 ) TOV0
69
2486NAVR07/04
T/C0 T/C1
T/C1 T/C0 T/C1

T/C0
CSn2:0 = 1 T/C T/C

fCLK_I/O 4 fCLK_I/O/8
fCLK_I/O/64 fCLK_I/O/256 fCLK_I/O/1024
T/C T/C1
T/C0 T/C
(6 >
CSn2:0 > 1) 1 N+1
N (8 64 256 1024)
T/C T/C
T/C
T1/T0 T/C clkT1/clkT0

T1/T0 ( ) Figure 30
T1/T0 clkI/O
CSn2:0 = 7 clkT1 CSn2:0 = 6

clkT0
Figure 30. T1/T0
Tn
D Q
Tn_sync
(To Clock
Select Logic)
D Q
LE
clk I/O
Synchronization
Edge Detector
T1/T0 2.5 3.5
T1/T0
T/C
50%
(fExtClk < fclk_I/O/2)
(Nyquist )
( )
fclk_I/O/2.5
70
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 31. T/C0 T/C1 (1)
clk I/O
Clear
PSR10
T0
Synchronization
T1
Synchronization
clkT1
Note:
IO SFIOR
Bit
clkT0
1. (T1/T0) Figure 30
ACME
PUD
PSR2
PSR10
R/W
R/W
R/W
R/W
SFIOR
Bit 0 PSR10:T/C1 T/C0

T/C1 T/C0
T/C1 T/C0
0
71
2486NAVR07/04
16 / 1
16 T/C ( )
16 ( 16 PWM)
2

( )
PWM
PWM

4 (TOV1OCF1A OCF1B ICF1)
n T/C x
TCNT1 T/C1
16 T/C Figure 32I/O P 2 CPU

I/O I/O I/O I/O
P 8916 /
Figure 32. 16 T/C (1)
Count
Clear
Direction
TOVn
(Int. Req.)
Control Logic
clkTn
Clock Select
Edge
Detector
TOP
Tn
BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=0
OCFnA
(Int. Req.)
Waveform
Generation
OCnA
DATA BUS
OCRnA
OCFnB
(Int.Req.)
Fixed
TOP
Values
Waveform
Generation
=
OCRnB
OCnB
( From Analog
Comparator Ouput )
ICFn (Int.Req.)
Edge
Detector
ICRn
Noise
Canceler
ICPn
TCCRnA
Note:
72
TCCRnB
1. P 2 P 55Table 22 P 59Table 28 T/C1
ATmega8(L)
2486NAVR07/04
ATmega8(L)
/ TCNT1 OCR1A/B ICR1 16

16 P 74 16 T/C
TCCR1A/B 8 CPU (
Int.Req.) TIFR
TIMSK TIFR TIMSK
T/CT1T/C(
) T/C
clkT1
OCR1A/B T/C
PWM OC1A/B P 79
OCF1A/B
ICP1 ( P 180 )
( ) T/C
( )
TOP T/C OCR1A ICR1
PWM OCR1A TOP OCR1A
PWM OCR1A TOP
TOP ICR1 OCR1A PWM
Table 35.
BOTTOM
0x0000 BOTTOM
MAX
0xFFFF ( 65535) MAX
TOP
TOP TOP 0x00FF

0x01FF 0x03FF OCR1A ICR1
16T/C16AVRT/C
16 T/C I/O
16 T/C
PWM10 WGM10
PWM11 WGM11
CTC1 WGM12
16 T/C
TCCR1A FOC1A FOC1B
TCCR1B WGM13
16 T/C
73
2486NAVR07/04
16
TCNT1OCR1A/B ICR1 AVR CPU 8 16

161688
16 16 16
CPU 16 8
8 16 16 CPU
16
16 OCR1A/B
16 16
16
OCR1A/B ICR1 C
16
(1)
...
; TCNT1 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNT1H,r17
out TCNT1L,r16
; TCNT1 r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
...
C (1)
unsigned int i;
...
/* TCNT1 0x01FF */
TCNT1 = 0x1FF;
/* TCNT1 i */
i = TCNT1;
...
Note:
1.
TCNT1 r17:r16
16 16
16
16
16
74
ATmega8(L)
2486NAVR07/04
ATmega8(L)
TCNT1 OCR1A/B ICR1
(1)
TIM16_ReadTCNT1:
;
in
r18,SREG
;
cli
; TCNT1 r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
;
out SREG,r18
ret
C (1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* */
sreg = SREG;
/* */
_CLI();
/* TCNT1 i */
i = TCNT1;
/* */
SREG = sreg;
return i;
}
Note:
1.
TCNT1 r17:r16
75
2486NAVR07/04
TCNT1 OCR1A/B ICR1
(1)
TIM16_WriteTCNT1:
;
in
r18,SREG
;
cli
; TCNT1 r17:r16
out TCNT1H,r17
out TCNT1L,r16
;
out SREG,r18
ret
C (1)
void TIM16_WriteTCNT1 ( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* */
sreg = SREG;
/* */
_CLI();
/* TCNT1 i */
TCNT1 = i;
/* */
SREG = sreg;
}
Note:
1.
r17:r16 TCNT1
76
16
ATmega8(L)
2486NAVR07/04
ATmega8(L)
T/C
T/C T/C B(TCCR1B)

(CS12:0) P 70T/C0 T/C1
16 T/C 16 Figure 33
Figure 33.
DATA BUS
(8-bit)
TOVn
(Int. Req.)
TEMP (8-bit)
Clock Select
count
TCNTnH (8-bit) TCNTnL (8-bit)
TCNTn (16-bit Counter)
clear
direction
Control Logic
clkTn
Edge
Detector
Tn
( From Prescaler )
TOP
BOTTOM
( )
Count
TCNT1 1 1
Direction
Clear
TCNT1
clkT1
TOP
TCNT1
BOTTOM
TCNT1 (0)
16 8 I/O TCNT1H 8 TCNT1L 8 CPU

TCNT1H CPU TCNT1H
(TEMP)TCNT1LTCNT1HTCNT1L
TCNT1H CPU
8 16
TCNT1
clkT1 1 1
clkT1 CS12:0 CS12:0= 0 CPU TCNT1
clkT1 CPU
TCCR1A TCCR1B WGM13:0
( ) OC1x
P 82
WGM13:0 TOV1 TOV1
CPU
T/C
ICP1
77
2486NAVR07/04
Figure 34
n /
Figure 34.
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit)
WRITE
ICRnL (8-bit)
TCNTnH (8-bit)
ICRn (16-bit Register)
ACO*
Analog
Comparator
ACIC*
TCNTnL (8-bit)
ICNC
ICES
Noise
Canceler
Edge
Detector
ICFn (Int. Req.)
ICPn
ICP1 ( ) ACO
16 TCNT1
ICR1 ICF1 ICIE1 = 1
ICF1
I/O "1
ICR1 ICR1L ICR1H
TEMP CPU ICR1H TEMP
ICR1 ICR1 TOP
ICR1 WGM13:0 ICR1
ICR1H I/O ICR1L
P 74 16 16
ICP1T/C1
ACSR ACIC
ICP1 ACO T1 (P 70Figure 30 ),

4
ICR1 TOP T/C
ICP1
78
4
4
ATmega8(L)
2486NAVR07/04
ATmega8(L)
TCCR1B ICNC1 ICR1
4
ICR1 ICR1
ICR1
TOP
ICR1
ICF1 ( I/O "1)
ICF1
16 TCNT1 OCR1x
OCF1x OCIE1x = 1 OCF1x
OCF1x I/O
"1 WGM13:0 COM1x1:0
TOP BOTTOM
(P 82 )
A T/C TOP ( ) TOP
Figure 35 n (n = 1
T/C1) x (A/B)
Figure 35.
DATA BUS (8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit)
OCRnxL Buf. (8-bit)
TCNTnH (8-bit)
OCRnx Buffer (16-bit Register)
OCRnxH (8-bit)
TCNTnL (8-bit)
OCRnxL (8-bit)
OCRnx (16-bit Register)
= (16-bit Comparator )
OCFnx (Int.Req.)
TOP
BOTTOM
Waveform Generator
WGMn3:0
OCnx
COMnx1:0
79
2486NAVR07/04
T/C 12 PWM OCR1x

(CTC) OCR1x
TOP BOTTOM PWM
OCR1x CPU OCR1x
CPU OCR1x OCR1x( )
(T/C TCNT1 ICR1
) OCR1x TEMP 16
OCR1x TEMP
OCR1xH CPU I/O
TEMP OCR1xL TEMP
OCR1x OCR1x
P 74 16 16
PWM FOC1x 1
OCF1x / OC1x
(COMx1:0 OC1x
)
TCNT1
CPUTCNT1OCR1x
TCNT1
TCNT1
TCNT1T/CTCNT1OCR1x
PWM TOP
TCNT1 TOP
0xFFFFTCNT1BOTTOM
OC1x OC1x
FOC1x OC1x
COM1x1:0 COM1x1:0
80
ATmega8(L)
2486NAVR07/04
ATmega8(L)
COM1x1:0 COM1x1:0
OC1x COM1x1:0 OC1x
Figure 36 COM1x1:0 I/O I/O I/O
COM1x1:0 I/O (DDR PORT)
OC1x OC1x OC1x OC1x
"0
Figure 36.
COMnx1
COMnx0
FOCnx
Waveform
Generator
Q
1
OCnx
DATABUS
OCnx
Pin
PORT
D
DDR
clk I/O
COM1x1:0 OC1x I/O

OC1x (DDR) OC1x
DDR_OC1x
Table 36Table 37 Table
38
OC1x COM1x1:0
P 89 16 /
COM1x1:0
81
2486NAVR07/04
COM1x1:0 CTC PWM

COM1x1:0 = 0 OC1x
PWM P 89Table 36 PWM P 90Table
37 PWM to P 90Table 38
COM1x1:0 PWM
FOC1x
- T/C - (WGM13:0)
(COM1x1:0)
COM1x1:0 PWM PWM COM1x1:0
P 81
P 87 /
(WGM13:0 = 0)
(TOP = 0xFFFF) 0x0000
TCNT1T/CTOV1TOV117
TOV1
CPU
CTC( )
CTC (WGM13:0 = 4 12) OCR1A ICR1

TCNT1 OCR1A(WGM13:0 = 4) ICR1 (WGM13:0 = 12)
OCR1A ICR1 TOP
CTCFigure 37TCNT1TCNT1OCR1A ICR1

TCNT1
Figure 37. CTC
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnA
(Toggle)
Period
82
(COMnA1:0 = 1)
ATmega8(L)
2486NAVR07/04
ATmega8(L)
OCF1A ICF1 TOP
TOP CTC
TOP BOTTOM OCR1A
ICR1 TCNT1
0xFFFF 0x0000 OCR1A
ICR1 PWM
OCR1A TOP (WGM13:0 = 15) OCR1A
CTC OC1A
COM1A1:0 = 1 OC1A
(DDR_OC1A = 1) fOC1A = fclk_I/O/2
(OCR1A = 0x0000)
f clk_I/O
f OCnA = ----------------------------------------------------2 N ( 1 + OCRnA )
N (1 8 64 256 1024)
TOV1 MAX 0x0000
PWM
PWM (WGM13:0 = 5 6 7 14 15) PWM

PWM PWM BOTTOM
TOP BOTTOM OC1x
TCNT1 OCR1x TOP OCR1x
PWM
PWM PWM
DAC ( )
PWM PWM 89 10 ICR1 OCR1A
2 (ICR1 OCR1A 0x0003) 16 (ICR1
OCR1A MAX) PWM
log ( TOP + 1 )
R FPWM = -----------------------------------log ( 2 )
PWM 0x00FF0x01FF0x03FF
(WGM13:0 = 5 6 7)ICR1 (WGM13:0 = 14) OCR1A (WGM13:0 = 15)
Figure 38 OCR1A ICR1
TOP PWM TCNT1
PWM PWM TCNT1
OCR1x TCNT1 OC1x
Figure 38. PWM
OCRnx / TOP Update
and TOVn Interrupt Flag
Set and OCnA Interrupt
Flag Set or ICFn
Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
83
2486NAVR07/04
TOP T/C TOV1 TOP OCR1A ICR1

OC1A ICF1 TOV1
TOP
TOPTOPTCNT1OCR1x
TOP OCR1x
"0
TOP ICR1 OCR1A ICR1
ICR1
ICR1 TCNT1
0xFFFF
0x0000 OCR1A
OCR1A OCR1A TCNT1 TOP
OCR1A
TCNT1 TOV1
TOP ICR1 TOP OCR1A OC1A
PWM PWM ( TOP ) OCR1A
PWM OC1x PWM COM1x1:0

2 PWM 3 PWM ( P 90Table 37
) OC1x DDR_OC1x
PWM OC1x OCR1x TCNT1 ( )
( TOP BOTTOM) ( )
PWM
f clk_I/O
f OCnxPWM = -----------------------------------N ( 1 + TOP )
N (1 8 64 256 1024)
OCR1x PWM OCR1x
BOTTOM(0x0000)TOP+1OCR1xTOP
COM1x1:0
OC1A (COM1A1:0 = 1)
50% OCR1A TOP (WGM13:0 = 15)OCR1A
0(0x0000) fOC1A = fclk_I/O/2 CTC OC1A
PWM
PWM
PWM (WGM13:0 = 1 2 310 11)

PWM
BOTTOM TOP TOP BOTTOM
TOP TCNT1 OCR1x OC1x
BOTTOM TCNT1 OCR1x OC1x
PWM PWM 8 9 10 ICR1 OCR1A

2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A
MAX) PWM
log ( TOP + 1 )
R PCPWM = -----------------------------------log ( 2 )
PWM 0x00FF 0x01FF
0x03FF (WGM13:0 = 12 3)ICR1 (WGM13:0 = 10) OCR1A (WGM13:0 = 11)
84
ATmega8(L)
2486NAVR07/04
ATmega8(L)
TCNT1 TOP Figure
39 OCR1A ICR1 TOP PWM
TCNT1 PWM PWM
TCNT1 OCR1x TCNT1 OC1x
Figure 39. PWM

OCRnx / TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
BOTTOM T/C TOV1 TOP OCR1A ICR1

OCR1x OC1A ICF1
TOPTOPTCNT1OCR1x
TOP OCR1x
"0 Figure 39 T/C
TOP OCR1x OCR1x
/ TOP PWM
TOP TOP
T/C TOP TOP
PWM OC1x PWM

COM1x1:0 2 PWM COM1x1:0 3 PWM ( P
90Table 38 ) OC1x DDR_OC1x
OCR1x TCNT1 OC1x
PWM PWM
f clk_I/O
f OCnxPCPWM = ----------------------------2 N TOP
N (1 8 64 256 1024)
OCR1x PWM PWM
OCR1x BOTTOM OCR1x TOP
PWM
85
2486NAVR07/04
OCR1A TOP (WGM13:0 = 11) COM1A1:0 = 1 OC1A

50%
PWM
PWM (WGM13:0 = 8 9) - PWM -

PWM PWM
BOTTOM TOP TOP
BOTTOM TOP TCNT1 OCR1x
OC1xBOTTOMTCNT1OCR1xOC1x
PWM PWM OCR1x

Figure 39 Figure 40
PWM PWM ICR1 OCR1A 2
(ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX)
PWM
log ( TOP + 1 )
R PFCPWM = -----------------------------------log ( 2 )
PWM ICR1 (WGM13:0 = 8) OCR1A
(WGM13:0 = 9)TCNT1 TOP
Figure 40 OCR1A ICR1 TOP
PWMTCNT1PWM
PWM TCNT1 OCR1x TCNT1
OC1x
Figure 40. PWM
OCnA Interrupt Flag Set or
ICFn Interrupt Flag Set
(Interrupt on TOP)
OCRnx / TOP Update and

(Interrupt on Bottom)
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
OCR1x T/C TOV1

TOP OCR1A ICR1 TCNT1 TOP OC1A CF1
TOP BOTTOM
TOPTOPTCNT1OCR1x
86
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 40 PWM
OCR1x BOTTOM
TOP ICR1 TOP OCR1A OC1A

PWM PWM ( TOP ) OCR1A
PWM OC1x PWM

COM1x1:0 2 PWM 3 PWM ( P
90Table 38 ) OC1x PWM
OC1x OCR1x TCNT1 ( )
TCNT1 ( ) PWM
f clk_I/O
f OCnxPFCPWM = ----------------------------2 N TOP
N (1 8 64 256 1024)
OCR1x PWM PWM
OCR1x BOTTOM OCR1x TOP
PWM
OCR1A TOP (WGM13:0 = 9) COM1A1:0 = 1OC1A
50%
/ clkT1
OCR1x OCR1x (
) Figure 41 OCF1x
Figure 41. T/C OCF1x
clkI/O
clkTn
(clkI/O /1)
TCNTn
OCRnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 42
87
2486NAVR07/04
Figure 42. T/C OCF1x fclk_I/O/8
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 43 TOP PWM

OCR1x BOTTOM TOP BOTTOM
BOTTOM+1 TOP-1 BOTTOM TOV1
Figure 43. T/C

clkI/O
clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
Figure 44
88
ATmega8(L)
2486NAVR07/04
ATmega8(L)
clkI/O
clkTn
(clkI/O /8)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
Old OCRnx Value
(Update at TOP)
New OCRnx Value
16 /
T/C1 A TCCR1A
Bit
COM1A1
COM1A0
COM1B1
COM1B0
FOC1A
FOC1B
WGM11
WGM10
R/W
R/W
R/W
R/W
R/W
R/W
TCCR1A
Bit 7:6 COM1A1:0: A

Bit 5:4 COM1B1:0: B
COM1A1:0 COM1B1:0 OC1A OC1B COM1A1:0(COM1B1:0)
"1OC1A(OC1B) I/O OC1A(OC1B)
OC1A(OC1B) COM1x1:0 WGM13:0 Table 36

WGM13:0 CTC ( PWM) COM1x1:0
Table 36. PWM
COM1A1/
COM1B1
COM1A0/
COM1B0
OC1A/OC1B
OC1A/OC1B
OC1A/OC1B( )
OC1A/OC1B ( )
89
2486NAVR07/04
Table 37 WGM13:0 PWM COM1x1:0

Table 37. PWM(1)
COM1A1/
COM1B1
COM1A0/
COM1B0
OC1A/OC1B
WGM13:0 = 15: OC1A

OC1B WGM13:0
OC1A/OC1B
OC1A/OC1B OC1A/OC1B
TOP
OC1A/OC1B OC1A/OC1B
TOP
1. OCR1A/OCR1B TOP COM1A1/COM1B1

OC1A/OC1B / P 83 PWM
Note:
Table 38WGM13:0PWMPWMCOM1x1:0
Table 38. PWM (1)

COM1A1/
COM1B1
COM1A0/
COM1B0
OC1A/OC1B
WGM13:0 = 9 14: OC1A

OC1B WGM13:0
OC1A/OC1B
OC1A/OC1B
OC1A/OC1B
OC1A/OC1B
OC1A/OC1B
Note:
1. OCR1A/OCR1B TOP COM1A1/COM1B1

P 84 PWM
Bit 3 FOC1A: A
Bit 2 FOC1B: B
FOC1A/FOC1BWGM13:0PWM
PWM TCCR1A FOC1A/FOC1B 1
COM1x1:0 OC1A/OC1B
FOC1A/FOC1B COM1x1:0
CTC OCR1A TOP FOC1A/FOC1B
FOC1A/FOC1B 0
Bit 1:0 WGM11:0:
TCCR1B WGM13:2
Table 39 T/C
( ) (CTC) (PWM)
P 82
90
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 39.
/ (1)
TOP
OCR1x
TOV1
0xFFFF
MAX
8 PWM
0x00FF
TOP
BOTTOM
9 PWM
0x01FF
TOP
BOTTOM
10 PWM
0x03FF
TOP
BOTTOM
CTC
OCR1A
MAX
8 PWM
0x00FF
TOP
TOP
9 PWM
0x01FF
TOP
TOP
10 PWM
0x03FF
TOP
TOP
PWM
ICR1
BOTTOM
BOTTOM
PWM
OCR1A
BOTTOM
BOTTOM
10
PWM
ICR1
TOP
BOTTOM
11
PWM
OCR1A
TOP
BOTTOM
12
CTC
ICR1
MAX
13
14
PWM
ICR1
TOP
TOP
15
PWM
OCR1A
TOP
TOP
WGM13
WGM12
(CTC1)
WGM11
(PWM11)
WGM10
(PWM10)
Note:
1. CTC1 PWM11:0 WGM12:0
91
2486NAVR07/04
T/C1 B TCCR1B
Bit
ICNC1
ICES1
WGM13
WGM12
CS12
CS11
CS10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCCR1B
Bit 7 ICNC1:
ICNC1 ICP1
ICP1 4 4
4
Bit 6 ICES1:
ICP1 ICES "0
ICES1 "1
ICES1 ICR1
ICF1
ICR1 TOP ( TCCR1A TCCR1B WGM13:0 ) ICP1
Bit 5
TCCR1B "0
Bit 4:3 WGM13:2:
TCCR1A
Bit 2:0 CS12:0:
3 T/C Figure 41 Figure 42
Table 40.
CS12
CS11
CS10
(T/C )
clkI/O/1 ( )
clkI/O/8 ( )
clkI/O/64 ( )
clkI/O/256 ( )
clkI/O/1024 ( )
T1
T1
T1
T/C1
T/C1 TCNT1H TCNT1L
Bit
TCNT1[15:8]
TCNT1H
TCNT1[7:0]
TCNT1L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCNT1HTCNT1LT/C1TCNT1/
16 CPU
92
ATmega8(L)
2486NAVR07/04
ATmega8(L)
8 TEMPTEMP 16 P 74
16
TCNT1TCNT1OCR1x
TCNT1
1A OCR1AH
OCR1AL
Bit
OCR1A[15:8]
OCR1AH
OCR1A[7:0]
1B OCR1BH
OCR1BL
OCR1AL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
OCR1B[15:8]
OCR1BH
OCR1B[7:0]
OCR1BL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16 TCNT1
OC1x
16 CPU
8 TEMPTEMP 16 P 74
16
93
2486NAVR07/04
1 ICR1H
ICR1L
Bit
ICR1[15:8]
ICR1H
ICR1[7:0]
ICR1L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICP1(T/C1)TCNT1
ICR1 ICR1 TOP
16 CPU 8
TEMP TEMP 16 P 74 16

T/C1
TIMSK(1)
Bit
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
TOIE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
TIMSK
1. T/CT1
Bit 5 TICIE1: T/C1

"1 I "1 T/C1
TIFR ICF1 CPU T/C1 ( P 43 )
Bit 4 OCIE1A:T/C1 A
"1 I "1 T/C1 A
TIFR OCF1A CPU T/C1 A
( P 43 )
Bit 3 OCIE1B:T/C1 B
"1 I "1 T/C1 B
TIFR OCF1B CPU T/C1 B
( P 43 )
Bit 2 TOIE1:T/C1
"1 I 1 T/C1
TIFR TOV1 CPU T/C1 ( P 43 )
T/C TIFR(1)
Bit
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
TOV0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
TIFR
1. T/CT1
Bit 5 ICF1: T/C1

ICP1 ICF1 ICR1 TOP
TOP ICF1
ICF1 "1
Bit 4 OCF1A: T/C1 A
TCNT1 OCR1A "1
94
ATmega8(L)
2486NAVR07/04
ATmega8(L)
(FOC1A) OCF1A
A OCF1A "1
Bit 3 OCF1B: T/C1 B

TCNT1 OCR1B "1
(FOC1B) OCF1B
B OCF1B "1
Bit 2 TOV1: T/C1

T/C1 CTC T/C1 TOV1
TOV1 P 91Table 39
TOV1 "1
95
2486NAVR07/04
8 PWM
/ 2
T/C2 8 /

( )
, (PWM)

10
(TOV2 OCF2)
32 kHz I/O
Figure 458T/C P 2 CPUI/O

I/O I/O I/O P 1088 T/C

Figure 45. 8 T/C
TCCRn
count
TOVn
(Int. Req.)
clear
Control Logic
direction
clkTn
TOSC1
BOTTOM
TOP
Prescaler
T/C
Oscillator
TOSC2
Timer/Counter
TCNTn
=0
= 0xFF
OCn
(Int. Req.)
Waveform
Generation
clkI/O
OCn
DATA BUS
OCRn
Synchronized Status Flags
clkI/O
Synchronization Unit
clkASY
Status Flags
ASSRn
asynchronous Mode
Select (ASn)
96
/ TCNT2 OCR2 8 (
Int.Req.) TIFR
TIMSK TIFR TIMSK
ATmega8(L)
2486NAVR07/04
ATmega8(L)
T/CTOSC1/2
ASSR T/C
( ) T/C
clkT2
OCR2 TCNT2
PWM OC2 P 99
OCF2
n /
2(TCNT2T/C2)
Table 41
Table 41.
T/C
BOTTOM
0x00 BOTTOM
MAX
0xFF ( 255) MAX
TOP
TOPTOP 0xFF
(MAX) OCR2
T/C clkT2 MCU clkI/O

ASSR AS2 TOSC1 TOSC2
P 110 ASSR
P 113 /
97
2486NAVR07/04
8T/CFigure 46
Figure 46.
TOVn
(Int. Req.)
DATA BUS
TOSC1
count
clear
TCNTn
Control Logic
clk Tn
Prescaler
T/C
Oscillator
direction
BOTTOM
TOSC2
TOP
clkI/O
( )
count
TCNT2 1 1
direction
clear
TCNT2 ( )
clkT2
T/C
top
TCNT2
bottom
TCNT2 (0)
clkT2 clkT2
CS22:0
(CS22:0 = 0) clkT2CPU TCNT2CPU
( )
T/C (TCCR2) WGM21 WGM20
OC2 P 102

T/CTOV2WGM21:0 TOV2CPU
98
ATmega8(L)
2486NAVR07/04
ATmega8(L)
8 TCNT2 OCR2 TCNT2

OCR2
OCF2 OCIE2 = 1 OCF2
1 WGM21:0 COM21:0
max
bottom ( P 102 )
Figure 47
Figure 47.
DATA BUS
OCRn
TCNTn
= (8-bit Comparator )
OCFn (Int. Req.)
TOP
BOTTOM
Waveform Generator
OCxy
FOCn
WGMn1:0
COMn1:0
PWM OCR2
OCR2 top bottom
PWM
OCR2 CPU OCR2
CPU OCR2
99
2486NAVR07/04
PWM FOC2 1
OCF2 / OC2
(COM21:0 OC2 )
TCNT2
CPU TCNT2
OCR2 TCNT2
TCNT2
TCNT2 T/C TCNT2
OCR2
TCNT2 BOTTOM
OC2 OC2
FOC2 OC2
COM21:0 COM21:0
100
ATmega8(L)
2486NAVR07/04
ATmega8(L)
COM21:0 COM21:0
(OC2) COM21:0 OC2
Figure 48 COM21:0 I/O I/O I/O
COM21:0 I/O (DDR PORT)
OC2 OC2 OC2
Figure 48.
COMn1
COMn0
FOCn
Waveform
Generator
Q
1
OCn
DATABUS
OCn
Pin
PORT
D
DDR
clk I/O
COM21:0 OC2 I/O

OC2 (DDR) OC2
DDR_OC2
OC2 COM21:0
P 108 8 T/C
101
2486NAVR07/04
COM21:0 CTC PWM

COM21:0 = 0 OC2 PWM
P 108Table 43 PWM P 109Table 44
PWM P 109Table 45
COM21:0 PWM
FOC2
- T/C - (WGM21:0)
(COM21:0)
COM21:0 PWM PWM COM21:0
(P 101 )
P 106T/C
(WGM21:0 = 0) 8
(TOP = 0xFF) 0x00
TCNT0 T/C TOV2 TOV2
9 TOV2
CPU
102
ATmega8(L)
2486NAVR07/04
ATmega8(L)
CTC( )
CTC (WGM21:0 = 2) OCR2

TCNT2 OCR2 OCR2 TOP
CTCFigure 49TCNT2TCNT2OCR2
TCNT2
Figure 49. CTC
OCn Interrupt Flag Set
TCNTn
OCn
(Toggle)
Period
(COMn1:0 = 1)
OCF2 TOP
TOPCTC
TOP BOTTOM OCR2
TCNT2
0xFF 0x00 OCR2
CTC OC2
COM21:0 = 1 OC2
fOC2 = fclk_I/O/2 (OCR2 = 0x00)
f clk_I/O
f OCn = ------------------------------------------------2 N ( 1 + OCRn )
N (1 8 32 64 128 256 1024)
TOV2 MAX 0x00
103
2486NAVR07/04
PWM
PWM (WGM21:0 = 3) PWM PWM

PWMBOTTOMMAX
BOTTOM OC2 TCNT2 OCR2
BOTTOM OC2
PWM PWM
PWM DAC
( )
PWM MAX
Figure 50 TCNT0
PWM PWM TCNT2 OCR2
TCNT2
Figure 50. PWM
OCRn Interrupt Flag Set
OCRn Update
and
TCNTn
OCn
(COMn1:0 = 2)
OCn
(COMn1:0 = 3)
Period
MAX T/C TOV2
PWM OC2 PWM COM21:0

2 PWM 3 PWM ( P 109Table 44
)OC2PWM
OC2 OCR2 TCNT2 ( ) ( MAX
BOTTOM) ( )
PWM
f clk_I/O
f OCnPWM = -----------------N 256
N (1 8 32 64 128 256 1024)
OCR2PWMOCR2ABOTTOM
MAX+1 OCR2 MAX COM21:0
104
ATmega8(L)
2486NAVR07/04
ATmega8(L)
OC2 (COM21:0 = 1) 50%
OCR2 0 foc2 = fclk_I/O/2 CTC
OC2 PWM
PWM
PWM (WGM21:0 = 1) PWM

BOTTOM MAX MAX
BOTTOM MAX TCNT2
OCR2 OC2 BOTTOM TCNT2
OCR2 OC2
PWM PWM 8 MAX

TCNT2 MAX Figure 51
TCNT2 PWM
PWM TCNT2 OCR2 TCNT2
Figure 51. PWM
OCn Interrupt Flag Set
OCRn Update
TCNTn
OCn
(COMn1:0 = 2)
OCn
(COMn1:0 = 3)
Period
BOTTOM T/C TOV2

PWM OC2 PWM COM21:0
2PWMCOM21:03PWM (P 109Table
45 )OC2OCR2 TCNT2
OC2 PWM
PWM
f clk_I/O
f OCnPCPWM = -----------------N 510
N (1 8 32 64 128 256 1024)
OCR2 PWM PWM
OCR2 BOTTOM OCR2 MAX
PWM
105
2486NAVR07/04
Figure 51 2 OCn
BOTTOM
T/C
Figure 51 OCR2A MAX OCR2A MAX

OCn BOTTOM
T/C MAX OCn
OCn
OCR2A
OCn
T/C clkT2
clkI/O T/C Figure 52
T/C PWM MAX
Figure 52. T/C
clkI/O
clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
BOTTOM
BOTTOM + 1
TOVn
Figure 53
clkI/O
clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
TOVn
Figure 54 ( CTC )OCF2
106
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 54. T/C OCF2 fclk_I/O/8
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRn - 1
OCRn
OCRn
OCRn + 1
OCRn + 2
OCRn Value
OCFn
Figure 55 CTC OCF2 TCNT2

Figure 55. T/C CTC fclk_I/O/8
clkI/O
clkTn
(clkI/O /8)
TCNTn
(CTC)
OCRn
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFn
107
2486NAVR07/04
8 T/C
T/C TCCR2
Bit
FOC2
WGM20
COM21
COM20
WGM21
CS22
CS21
CS20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCCR2
Bit 7 FOC2:
FOC2 WGM PWM
PWM TCCR2 1
OC2 COM21:0 FOC2
COM21:0
FOC2 OCR2 TOP CTC
FOC2 0
Bit 6,3 WGM21:0:
TOP T/C
(CTC) PWM
Table 42 and P 102
Table 42.
T/C
TOP
OCR2
TOV2
0xFF
MAX
PWM
0xFF
TOP
BOTTOM
CTC
OCR2
MAX
PWM
0xFF
TOP
MAX
WGM21
(CTC2)
WGM20
(PWM2)
1. CTC2 PWM2 WGM21:0
Note:
Bit 5:4 COM21:0:

OC0 COM01:0
OC0 1
OC0 COM01:0 WGM01:0 Table 43

WGM01:0 CTC COM01:0
Table 43. PWM
COM21
COM20
OC2
OC2
OC2
OC2
Table 44 WGM21:0 PWM COM21:0
108
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 44. PWM (1)
COM21
COM20
OC2
OC2 TOP OC0
OC2 TOP OC0
Note:
1. OCR2 TOP COM21

TOP P 104 PWM
Table 45 WGM21:0 PWM COM21:0

Table 45. PWM (1)
COM21
COM20
OC2
OC2
OC2
OC2
OC2
Note:
1. OCR2 TOP COM21

TOP P 105 PWM
109
2486NAVR07/04
Bit 2:0 CS22:0:

T/C Table 46
Table 46.
/ TCNT2
CS22
CS21
CS20
T/C
clkT2S/( )
clkT2S/8 ( )
clkT2S/32 ( )
clkT2S/64 ( )
clkT2S/128 ( )
clkT2S/256 ( )
clkT2S/1024 ( )
Bit
TCNT2[7:0]
TCNT2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
T/C 8 TCNT2
TCNT2
TCNT2 OCR2
OCR2
Bit
OCR2[7:0]
OCR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8 TCNT2
OC2
/
ASSR
Bit
AS2
TCN2UB
OCR2UB
TCR2UB
R/W
ASSR
Bit 3 AS2: T/C2

AS2"0T/C2I/OclkI/OAS2"1T/C2TOSC1
AS2 TCNT2 OCR2 TCCR2
Bit 2 TCN2UB:T/C2
T/C2TCNT2TCN2UBTCNT2
TCN2UB TCN2UB 0 TCNT2
Bit 1 OCR2UB: 2
T/C2OCR2OCR2UBOCR2
OCR2UB OCR2UB 0 OCR2
110
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Bit 0 TCR2UB:T/C2
T/C2TCCR2TCR2UBTCCR2
TCR2UB TCR2UB 0 TCCR2
TCNT2 OCR2 TCCR2 TCNT2

OCR2 TCCR2
/ 2
T/C2
TCNT2OCR2 TCCR2
1. OCIE2 TOIE2 T/C2

2. AS2
3. TCNT2 OCR2 TCCR2
4. TCN2UB OCR2UB TCR2UB
5. T/C2
6.
32.768 kHz TOSC1 T/C2

4
TCNT2OCR2 TCCR2 TOSC1
3 TCNT2 OCR2
ASSR
T/C2 MCU Standby TCNT2

OCR2ATCCR2AMCUT/C2
T/C2 MCU
OCR2 TCNT2 (OCR2UB
0)MCU MCU
T/C2Standby
TOSC1
TOSC1
1. TCCR2 TCNT2 OCR2

2. ASSR
3. Standby
T/C2 32.768 kHz

Standby 1
/Standby 1
T/C2 T/C2
Standby
MCU 4
SLEEP
TCNT2 TCNT2
TOSC TCNT2 I/O
TOSC1 I/O
111
2486NAVR07/04
TCNT2 TOSC1
TOSC1
TCNT2
1. OCR2 TCCR2
2.
3. TCNT2
112
ATmega8(L)
2486NAVR07/04
ATmega8(L)
/
TIMSK
Bit
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
TOIE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TIMSK
Bit 7 OCIE2:T/C2
OCIE2 I "1 T/C2 A
T/C2 TIFR OCF2
Bit 6 TOIE2: T/C2
TOIE2 I "1 T/C2 T/C2
TIFR TOV2
/
TIFR
Bit
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
TOV0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TIFR
Bit 7 OCF2: 2
T/C2 OCR2( 2) OCF2
1 SREG IOCIE2 OCF2
Bit 6 TOV2: T/C2

T/C2 TOV2 TOV2
1 SREG I TOIE2 TOV2
PWM T/C2 0x00 TOV2
Figure 56. T/C2
PSR2
clkT2S/1024
clkT2S/256
AS2
clkT2S/128
10-BIT T/C PRESCALER
Clear
clkT2S/64
TOSC1
clkT2S
clkT2S/32
clkI/O
clkT2S/8
CS20
CS21
CS22
TIMER/COUNTER2 CLOCK SOURCE

clkT2
113
2486NAVR07/04
T/C2 clkT2S clkT2S clkI/O

ASSR AS2T/C2 TOSC1 T/C2 RTC
TOSC1 TOSC2 C (
32.768 kHz ) TOSC1
T/C2 clkT2S/8 clkT2S/32 clkT2S/64 clkT2S/128 clkT2S/256
clkT2S/1024clkT2S 0 ()SFIORPSR2
IO SFIOR
Bit
ACME
PUD
PSR2
PSR10
R/W
R/W
R/W
R/W
SFIOR
Bit 1 PSR2: T/C2

1 T/C2 0
CPU T/C2 0 T/C2
1
114
ATmega8(L)
2486NAVR07/04
ATmega8(L)
SPI
SPI ATmega8 AVR

ATmega8 SPI
3

LSB MSB
7

(CK/2)
Figure 57. SPI (1)
SPI2X
SPI2X
DIVIDER
/2/4/8/16/32/64/128
Note:
1. SPI P 2 P 55Table 22
SPI Figure 58
SS
SCK
MOSI MOSI MISO
MISO SS
SPI SPI SS SPI
SPI 8 SPI
SPIF SPCR SPI SPIE
SPDR SS
115
2486NAVR07/04
SS SPI MISO
SPI SPDR SCK
SPDR SS
SPIFSPCRSPISPIE
SPDR
Figure 58. SPI -

MSB
MASTER
LSB
MISO
MISO
MSB
8 BIT SHIFT REGISTER
SLAVE
LSB
8 BIT SHIFT REGISTER

MOSI
MOSI
SHIFT
ENABLE
SPI
CLOCK GENERATOR
SCK
SS
VCC
SCK
SS
SPI
SPI
SPI
SPI SCK
SPI fosc/4
SPI MOSIMISOSCK SS Table 47
P 53
Table 47. SPI (1)
SPI
SPI
MOSI
MISO
SCK
SS
Note:
1. P 55 B SPI
SPI
DDR_SPIDD_MOSIDD_MISODD_SCK
116
ATmega8(L)
2486NAVR07/04
ATmega8(L)
MOSI PB5 DD_MOSI DDB5
DDR_SPI DDRB
(1)
SPI_MasterInit:
; MOSI SCK
ldi
r17,(1<<DD_MOSI)|(1<<DD_SCK)
out
DDR_SPI,r17
; SPI fck/16
ldi
r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
out
SPCR,r17
ret
SPI_MasterTransmit:
; (r16)
out
SPDR,r16
Wait_Transmit:
;
sbis SPSR,SPIF
rjmp Wait_Transmit
ret
C (1)
void SPI_MasterInit(void)
{
/* MOSI SCK */
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
/* SPI fck/16 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
void SPI_MasterTransmit(char cData)
{
/* */
SPDR = cData;
/* */
while(!(SPSR & (1<<SPIF)))
;
}
Note:
1.
117
2486NAVR07/04
SPI
(1)
SPI_SlaveInit:
; MISO
ldi
r17,(1<<DD_MISO)
out
DDR_SPI,r17
; SPI
ldi
r17,(1<<SPE)
out
SPCR,r17
ret
SPI_SlaveReceive:
;
sbis SPSR,SPIF
rjmp SPI_SlaveReceive
;
in
r16,SPDR
ret
C (1)
void SPI_SlaveInit(void)
{
/* MISO */
DDR_SPI = (1<<DD_MISO);
/* SPI */
SPCR = (1<<SPE);
}
char SPI_SlaveReceive(void)
{
/* */
while(!(SPSR & (1<<SPIF)))
;
/* */
return SPDR;
}
Note:
118
1.
ATmega8(L)
2486NAVR07/04
ATmega8(L)
SS
SPI SS SS SPI MISO

( ) SS
SPI
SS /
SS SPI
SPI (MSTR SPCR ) SS

SS I/O SPI
SS
SS SPI SS
SPI
SPI
1. SPCR MSTR SPI MOSI SCK
2. SPSR SPIF SPI
SPI SS
MSTR "1 SPI
SPI SPCR
Bit
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SPCR
Bit 7 SPIE: SPI

SPSR SPIF SREG
SPI
Bit 6 SPE: SPI
SPE SPI SPI SPE
Bit 5 DORD:
DORD LSB MSB
Bit 4 MSTR: /
MSTR MSTR "1SS
MSTR SPSR SPIF MSTR
Bit 3 CPOL:
CPOL SCK SCK Figure 59
Figure 60 CPOL
Table 48. CPOL
CPOL
Bit 2 CPHA:
119
2486NAVR07/04
CPHA SCK SCK Figure 59

Figure 60
Table 49. CPHA
CPHA
Bits 1, 0 SPR1, SPR0: SPI 1 0

SCK SPR1 SPR0 SCK fosc
Table 50. SCK
120
SPI2X
SPR1
SPR0
SCK
fosc/4
fosc/16
fosc/64
fosc/128
fosc/2
fosc/8
fosc/32
fosc/64
ATmega8(L)
2486NAVR07/04
ATmega8(L)
SPI SPSR
Bit
SPIF
WCOL
SPI2X
R/W
SPSR
Bit 7 SPIF: SPI

SPIF SPCR SPIE SPI
SPI SS SPIF
SPIFSPSRSPDRSPIF
Bit 6 WCOL:
SPI SPDR WCOLWCOL SPSR
SPDR
Bit 5..1 Res:
Bit 0 SPI2X: SPI

SPI ( Table 50) SCK CPU
fosc /4
ATmega8SPIEEPROMSPI
SPI SPDR
Bit
MSB
0
LSB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SPDR
SPI / SPI
121
2486NAVR07/04
SCK 4 CPHA CPOL

SPI Figure 59 Figure 60 SCK
Table 48 Table 49
Table 51. CPOL CPHA
SPI
CPOL = 0, CPHA = 0
( )
( )
CPOL = 0, CPHA = 1
( )
( )
CPOL = 1, CPHA = 0
( )
( )
CPOL = 1, CPHA = 1
( )
( )
Figure 59. CPHA = 0 SPI

SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)

LSB first (DORD = 1)
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
Figure 60. CPHA = 1 SPI

SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)

LSB first (DORD = 1)
122
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
ATmega8(L)
2486NAVR07/04
ATmega8(L)
USART
(USART)
( )

5, 6, 7, 8, 9 1 2

,

Figure 61 USART CPU I/O I/O

Figure 61. USART (1)
Clock Generator
UBRR[H:L]
OSC
BAUD RATE GENERATOR
SYNC LOGIC
PIN
CONTROL
XCK
Transmitter
TX
CONTROL
DATABUS
UDR (Transmit)
PARITY
GENERATOR
TxD
Receiver
UCSRA
Note:
PIN
CONTROL
TRANSMIT SHIFT REGISTER
CLOCK
RECOVERY
RX
CONTROL
RECEIVE SHIFT REGISTER
DATA
RECOVERY
PIN
CONTROL
UDR (Receive)
PARITY
CHECKER
UCSRB
RxD
UCSRC
1. P 2 P 60Table 30 P 60Table 29 USART
USART
123
2486NAVR07/04
XCK ( )
USART
UDR
AVR USART AVR UART
USART AVR UART
USART
FIFO
FE DOR 9 RXB8
UDR
( Figure 61)
USART (DOR)
CHR9 UCSZ2
OR DOR
USART 4
USART UMSEL
C (UCSRC) (
) UCSRA U2X (UMSEL = 1) XCK
(DDR_XCK)()()
XCK
Figure 62
124
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 62.
UBRR
U2X
fosc
Prescaling
Down-Counter
UBRR+1
/2
/4
/2
0
1
0
OSC
DDR_XCK
xcki
XCK
Pin
Sync
Register
Edge
Detector
UMSEL
xcko
UCPOL
DDR_XCK
txclk
1
0
rxclk
txclk
( )
rxclk
( )
xcki
XCK ( )
xcko
XCK ( )
fosc
XTAL ( )
Figure 62
USART UBRR
UBRRL
UBRR
fosc/(UBRR+1) 2 8
16
2816UMSEL
U2X DDR_XCK
Table 52(/)UBRR
Table 52.
Equation for Calculating
Baud Rate(1)
Equation for Calculating

UBRR Value
(U2X = 0)
f OSC
BAUD = ---------------------------------------16 ( UBRR + 1 )
f OSC
UBRR = ------------------------ 1
16BAUD
(U2X = 1)
f OSC
BAUD = -----------------------------------8 ( UBRR + 1 )
f OSC
UBRR = --------------------- 1
8BAUD
f OSC
BAUD = -----------------------------------2 ( UBRR + 1 )
f OSC
UBRR = --------------------- 1
2BAUD
Note:
1. (bps)
125
2486NAVR07/04
BAUD ( bps)
fOSC
UBRR UBRRH UBRRL (0-4095)

Table 60 UBRR
(U2X)
UCSRA U2X
"0
16 8
Figure 62
XCK
CPU
XCK
f OSC
f XCK < ------------4
fosc
126
ATmega8(L)
2486NAVR07/04
ATmega8(L)
(UMSEL = 1)XCK ( ) (
)
TxD XCK RxD
Figure 63. XCK
UCPOL = 1
XCK
RxD / TxD
Sample
UCPOL = 0
XCK
RxD / TxD
Sample
UCRSC UCPOL XCK

Figure 63 UCPOL=0 XCK XCK
UCPOL=1 XCK XCK
( )
USART 30
5 6 7 8 9
1 2
Figure
64
Figure 64.
FRAME
(IDLE)
St
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
(St / IDLE)
St
(n)
(0 8)
Sp
IDLE
(RxD TxD)
UCSRB UCSRC UCSZ2:0 UPM1:0 USBS
127
2486NAVR07/04
USART UCSZ2:0 UPM1:0

USBS
(FE) "0
P even = d n 1 d 3 d 2 d 1 d 0 0
P odd = d n 1 d 3 d 2 d 1 d 0 1
Peven
Podd
dn
USART
USART
USART
( )
USART TXC
RXC
( UDR )TXC
USART ( )
r17:r16
UCSRC UBRRH UCSRC I/O URSEL (MSB)
128
ATmega8(L)
2486NAVR07/04
ATmega8(L)
(1)
USART_Init:
;
out
UBRRH, r17
out
UBRRL, r16
;
ldi
r16, (1<<RXEN)|(1<<TXEN)
out
UCSRB,r16
; : 8 , 2
ldi
r16, (1<<URSEL)|(1<<USBS)|(3<<UCSZ0)
out
UCSRC,r16
ret
C (1)
void USART_Init( unsigned int baud )
{
/* */
UBRRH = (unsigned char)(baud>>8);
UBRRL = (unsigned char)baud;
/* */
UCSRB = (1<<RXEN)|(1<<TXEN);
/* : 8 , 2 */
UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0);
}
Note:
1.
I/O
129
2486NAVR07/04
USART UCSRB TXEN USART TxD
I/O USART
XCK
5 8
CPU UDR
( )
UDRE 8
UDR
USART R16
(1)
USART_Transmit:
;
sbis UCSRA,UDRE
rjmp USART_Transmit
;
out
UDR,r16
ret
C (1)
void USART_Transmit( unsigned char data )
{
/* */
while ( !( UCSRA & (1<<UDRE)) )
;
/* */
UDR = data;
}
Note:
1.
UDRE
130
ATmega8(L)
2486NAVR07/04
ATmega8(L)
9
9 (UCSZ = 7) 9 UCSRB
TXB88UDR9
R17:R16
(1)
USART_Transmit:
;
sbis UCSRA,UDRE
rjmp USART_Transmit
; 9 r17 TXB8
cbi
UCSRB,TXB8
sbrc r17,0
sbi
UCSRB,TXB8
; 8
out
UDR,r16
ret
C (1)
void USART_Transmit( unsigned int data )
{
/* */
while ( !( UCSRA & (1<<UDRE))) )
;
/* 9 TXB8 */
UCSRB &= ~(1<<TXB8);
if ( data & 0x0100 )
UCSRB |= (1<<TXB8);
/* */
UDR = data;
}
Note:
1. UCSRB
UCSRB TXB8
USART USART UDRE TXC
UDRE
"1
UCSRA "0
UCSRB UDRIE "1 UDRE (
) USART UDR
UDRE
UDR UDRE
TXC TXC "1 TXC

RS-485
131
2486NAVR07/04
UCSRB TXCIE "1 TXC

USART TXC
TXC
(UPM1 = 1)
TXEN
TxD I/O
132
ATmega8(L)
2486NAVR07/04
ATmega8(L)
USART UCSRB (RXEN) USART RxD
USART
XCK
5 8
XCK

UDR
RXC 8
UDR 0 USART
(1)
USART_Receive:
;
sbis UCSRA, RXC
rjmp USART_Receive
;
in
r16, UDR
ret
C (1)
unsigned char USART_Receive( void )
{
/* */
while ( !(UCSRA & (1<<RXC)) )
;
/* */
return UDR;
}
Note:
1.
RXC
133
2486NAVR07/04
9 (UCSZ=7) UDR 8
UCSRB RXB8 9 FE DOR
UPEUCSRA UDR UDR
FIFO FIFO TXB8 FE DOR UPE
USART9
(1)
USART_Receive:
;
sbis UCSRA, RXC
rjmp USART_Receive
; 9
in
r18, UCSRA
in
r17, UCSRB
in
r16, UDR
; -1
andi r18,(1<<FE)|(1<<DOR)|(1<<PE)
breq USART_ReceiveNoError
ldi
r17, HIGH(-1)
ldi
r16, LOW(-1)
USART_ReceiveNoError:
; 9
lsr
r17
andi r17, 0x01

ret
C (1)
unsigned int USART_Receive( void )
{
unsigned char status, resh, resl;
/* */
while ( !(UCSRA & (1<<RXC)) )
;
/* 9 */
/* from buffer */
status = UCSRA;
resh = UCSRB;
resl = UDR;
/* -1 */
if ( status & (1<<FE)|(1<<DOR)|(1<<PE) )
return -1;
/* 9 */
resh = (resh >> 1) & 0x01;
return ((resh << 8) | resl);
}
Note:
1.
I/O
134
USART
ATmega8(L)
2486NAVR07/04
ATmega8(L)
(RXC)
1 0( )
(RXEN = 0) RXC
UCSRB (RXCIE) RXC (
) USART
UDR RXC
USART (FE) (DOR) (UPE)

UCSRA UDR
UCSRA (UDR)

"0
(FE)
( 1) FE 0 FE 1
UCSRC USBS FE
UCSRA
0
(DOR) (
)
DOR UDR UDR
UCSRA 0
DOR
(PE)
UPE UCSRA
0 P 128 P 136
135
2486NAVR07/04
UPM1 ( ) UPM0

(UPE)
(UPM1 = 1)
UPE (UDR)
(RXEN
) RxD FIFO
FIFO
UDR RXC
(1)
USART_Flush:
sbis UCSRA, RXC
ret
in
r16, UDR
rjmp USART_Flush
C (1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRA & (1<<RXC) ) dummy = UDR;
}
Note:
1.
USART
RxD
Figure 65
16
8 (U2X = 1)
RxD ( ) 0
Figure 65.
RxD
IDLE
START
BIT 0
Sample
(U2X = 0)
10
11
12
13
14
15
16
Sample
(U2X = 1)
RxD ( ) ( )
1 0
136
ATmega8(L)
2486NAVR07/04
ATmega8(L)
8 9 10( ) 4 5 6( )
( )

16 8
Figure 66
Figure 66.
RxD
BIT n
Sample
(U2X = 0)
10
11
12
13
14
15
16
Sample
(U2X = 1)
2 3 1 2
30RxD

Figure 67
Figure 67.
RxD
STOP 1
(A)
(B)
(C)
Sample
(U2X = 0)
10
0/1
0/1
0/1
Sample
(U2X = 1)
0/1
0 FE

Figure 67 A
B C
(
Table 53)
137
2486NAVR07/04
( D + 1 )S
R slow = ---------------------------------------------S 1 + D S + SF
( D + 2 )S
R fast = -------------------------------------( D + 1 )S + S M
(D = 5 10 )
S = 16 S = 8
SF
SF = 8 SF = 4
SM
SM = 9 SM = 5
Rslow Rfast
Table 53 Table 54
Table 53. (U2X = 0)

D
# ( + )
Rslow %
Rfast %
(%)
(%)
93,20
106,67
+6.67/-6.8
3.0
94,12
105,79
+5.79/-5.88
2.0
94,81
105,11
+5.11/-5.19
2.0
95,36
104,58
+4.58/-4.54
2.0
95,81
104,14
+4.14/-4.19
1.5
10
96,17
103,78
+3.78/-3.83
1.5
Table 54. (U2X = 1)

D
# +
Rslow
(%)
Rfast
(%)
(%)
(%)
94,12
105,66
+5.66/-5.88
2.5
94,92
104,92
+4.92/-5.08
2.0
95,52
104,35
+4.35/-4.48
1.5
96,00
103,90
+3.90/-4.00
1.5
96,39
103,53
+3.53/-3.61
1.5
10
96,70
103,23
+3.23/-3.30
1.0
(XTAL)
2%

UBRR
138
ATmega8(L)
2486NAVR07/04
ATmega8(L)
UCSRA (MPCM) USART

CPU
MPCM
5 8
9 9 (RXB8)
( 9 ) 1
MPCM
9 (UCSZ = 7)
(TXB8 = 1) 9 (TXB8) 1 (TXB = 0)
9
1. (UCSRA MPCM )
2. UCSRA
RXC
3. UDR
UCSRA MPCM
MPCM 1
4.
MPCM 1
5. MPCM
2
5 8 n n+1
5 8 (USBS = 1)
- - (SBI CBI) MPCM MPCM TXC

I/O SBI CBI
139
2486NAVR07/04
UBRRH/ UCSRC
UBRRH UCSRC I/O
USART (URSEL)
URSEL 0 UBRRH URSEL 1 UCSRC
(1)
...
; UBRRH 2
ldi r16,0x02
out UBRRH,r16
...
; USBS UCSZ1 1 0
ldi r16,(1<<URSEL)|(1<<USBS)|(1<<UCSZ1)
out UCSRC,r16
...
C (1)
...
/* UBRRH 2*/
UBRRH = 0x02;
...
/* USBS UCSZ1 1 0*/
UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1);
...
Note:
1.
I/O
140
ATmega8(L)
2486NAVR07/04
ATmega8(L)
UBRRH UCSRC
UBRRH I/O
UCSRC
UCSRC ( )
UCSRC
(1)
USART_ReadUCSRC:
; UCSRC
in
r16,UBRRH
in
r16,UCSRC
ret
C (1)
unsigned char USART_ReadUCSRC( void )
{
unsigned char ucsrc;
/* UCSRC */
ucsrc = UBRRH;
ucsrc = UCSRC;
return ucsrc;
}
Note:
1.
r16 UCSRC
UBRRH
USART
USART I/O UDR
Bit
0
UDR ( )
RXB[7:0]
UDR ( )
TXB[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
USART USART I/O

USART UDR UDR
(TXB) UDR (RXB)
567 0
UCSRA UDRE UDRE
UDR USART
TxD
FIFO FIFO
- - (SBI CBI) (SBIC SBIS)
FIFO
141
2486NAVR07/04
USART A
UCSRA
Bit
RXC
TXC
UDRE
FE
DOR
PE
U2X
MPCM
R/W
R/W
R/W
UCSRA
Bit 7 RXC: USART

RXC
RXC RXC ( RXCIE )
Bit 6 TXC: USART
(UDR) TXC
TXC 1 TXC
( TXCIE )
Bit 5 UDRE: USART
UDRE(UDR)UDRE1
UDRE ( UDRIE )
UDRE
Bit 4 FE:
0 FE (UDR)
1 FE 0 UCSRA 0
Bit 3 DOR:
DOR ( )
(UDR) UCSRA 0
Bit 2 PE:
(UPM1 = 1)
UPE (UDR) UCSRA
0
Bit 1 U2X:
1 16 8
Bit 0 MPCM:
MPCM USART
MPCMP 139

USART B
UCSRB
Bit
RXCIE
TXCIE
UDRIE
RXEN
TXEN
UCSZ2
RXB8
TXB8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UCSRB
Bit 7 RXCIE:
RXC RXCIE 1 SREG UCSRA
RXC 1 USART
142
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Bit 6 TXCIE:
TXC TXCIE 1 SREG UCSRA
TXC 1 USART
Bit 5 UDRIE: USART
UDRE UDRIE 1 SREG UCSRA
UDRE 1 USART
Bit 4 RXEN:
USART RxD USART
FE DOR PE
Bit 3 TXEN:
USART TxD USART TXEN
TxD I/O
Bit 2 UCSZ2:
UCSZ2UCSRCUCSZ1:0(
)
Bit 1 RXB8: 8
9 RXB8 9 UDR
RXB8
Bit 0 TXB8: 8
9 TXB8 9 UDR
USART C
UCSRC
Bit
URSEL
UMSEL
UPM1
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UCSRC
UCSRC UBRRH I/O P 140
UBRRH/ UCSRC
Bit 7 URSEL:
UCSRC UBRRH UCSRC 1
UCSRC URSEL 1
Bit 6 UMSEL: USART
Table 55. UMSEL

UMSEL
143
2486NAVR07/04
Bit 5:4 UPM1:0:
UPM0 UCSRA PE
Table 56. UPM
UPM1
UPM0
Bit 3 USBS:
Table 57. USBS

USBS
Bit 2:1 UCSZ1:0:

UCSZ1:0UCSRB UCSZ2(
)
Table 58. UCSZ
UCSZ2
UCSZ1
UCSZ0
Bit 0 UCPOL:
UCPOL
XCK
Table 59. UCPOL
(TxD )
(RxD )
XCK
XCK
XCK
XCK
UCPOL
144
ATmega8(L)
2486NAVR07/04
ATmega8(L)
USART UBRRL
UBRRH
Bit
15
14
13
12
URSEL
11
10
UBRR[11:8]
UBRRH
UBRR[7:0]
7
/
UBRRL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UCSRC UBRRH I/O P 140
UBRRH/ UCSRC
Bit 15 URSEL:
UCSRC UBRRH UBRRH 0
UBRRH URSEL 0
Bit 14:12
UBRRH
Bit 11:0 UBRR11:0: USART
12 USART UBRRH USART
4 UBRRL 8
UBRRL
145
2486NAVR07/04
Table 60 UBRR
0.5%
(
P 137 )
BaudRate Closest Match
Error[%] = -------------------------------------------------------- 1 100%
BaudRate
Table 60. UBRR

fosc = 1.0000 MHz
(bps)
U2X = 0
UBRR
fosc = 1.8432 MHz
U2X = 1
UBRR
U2X = 0
UBRR
fosc = 2.0000 MHz
U2X = 1
UBRR
U2X = 0
UBRR
U2X = 1
UBRR
2400
25
0.2%
51
0.2%
47
0.0%
95
0.0%
51
0.2%
103
0.2%
4800
12
0.2%
25
0.2%
23
0.0%
47
0.0%
25
0.2%
51
0.2%
9600
-7.0%
12
0.2%
11
0.0%
23
0.0%
12
0.2%
25
0.2%
14.4k
8.5%
-3.5%
0.0%
15
0.0%
-3.5%
16
2.1%
19.2k
8.5%
-7.0%
0.0%
11
0.0%
-7.0%
12
0.2%
28.8k
8.5%
8.5%
0.0%
0.0%
8.5%
-3.5%
38.4k
-18.6%
8.5%
0.0%
0.0%
8.5%
-7.0%
57.6k
8.5%
8.5%
0.0%
0.0%
8.5%
8.5%
76.8k
-18.6%
-25.0%
0.0%
-18.6%
8.5%
115.2k
8.5%
0.0%
0.0%
8.5%
8.5%
230.4k
0.0%
250k
0.0%
1.
146
(1)
62.5 kbps
125 kbps
115.2 kbps
230.4 kbps
125 kbps
250 kbps
UBRR = 0, = 0.0%
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 61. UBRR
fosc = 3.6864 MHz
(bps)
U2X = 0
UBRR
fosc = 4.0000 MHz
U2X = 1
UBRR
U2X = 0
UBRR
fosc = 7.3728 MHz
U2X = 1
UBRR
U2X = 0
UBRR
U2X = 1
UBRR
2400
95
0.0%
191
0.0%
103
0.2%
207
0.2%
191
0.0%
383
0.0%
4800
47
0.0%
95
0.0%
51
0.2%
103
0.2%
95
0.0%
191
0.0%
9600
23
0.0%
47
0.0%
25
0.2%
51
0.2%
47
0.0%
95
0.0%
14.4k
15
0.0%
31
0.0%
16
2.1%
34
-0.8%
31
0.0%
63
0.0%
19.2k
11
0.0%
23
0.0%
12
0.2%
25
0.2%
23
0.0%
47
0.0%
28.8k
0.0%
15
0.0%
-3.5%
16
2.1%
15
0.0%
31
0.0%
38.4k
0.0%
11
0.0%
-7.0%
12
0.2%
11
0.0%
23
0.0%
57.6k
0.0%
0.0%
8.5%
-3.5%
0.0%
15
0.0%
76.8k
0.0%
0.0%
8.5%
-7.0%
0.0%
11
0.0%
115.2k
0.0%
0.0%
8.5%
8.5%
0.0%
0.0%
230.4k
0.0%
0.0%
8.5%
8.5%
0.0%
0.0%
250k
-7.8%
-7.8%
0.0%
0.0%
-7.8%
-7.8%
0.5M
-7.8%
0.0%
-7.8%
-7.8%
1M
-7.8%
1.
(1)
230.4 kbps
460.8 kbps
250 kbps
0.5 Mbps
460.8 kbps
921.6 kbps
UBRR = 0, = 0.0%
147
2486NAVR07/04
Table 62. UBRR

fosc = 11.0592 MHz
fosc = 8.0000 MHz
(bps)
U2X = 0
UBRR
U2X = 1
UBRR
U2X = 0
UBRR
fosc = 14.7456 MHz
U2X = 1
UBRR
U2X = 0
UBRR
U2X = 1
UBRR
2400
207
0.2%
416
-0.1%
287
0.0%
575
0.0%
383
0.0%
767
0.0%
4800
103
0.2%
207
0.2%
143
0.0%
287
0.0%
191
0.0%
383
0.0%
9600
51
0.2%
103
0.2%
71
0.0%
143
0.0%
95
0.0%
191
0.0%
14.4k
34
-0.8%
68
0.6%
47
0.0%
95
0.0%
63
0.0%
127
0.0%
19.2k
25
0.2%
51
0.2%
35
0.0%
71
0.0%
47
0.0%
95
0.0%
28.8k
16
2.1%
34
-0.8%
23
0.0%
47
0.0%
31
0.0%
63
0.0%
38.4k
12
0.2%
25
0.2%
17
0.0%
35
0.0%
23
0.0%
47
0.0%
57.6k
-3.5%
16
2.1%
11
0.0%
23
0.0%
15
0.0%
31
0.0%
76.8k
-7.0%
12
0.2%
0.0%
17
0.0%
11
0.0%
23
0.0%
115.2k
8.5%
-3.5%
0.0%
11
0.0%
0.0%
15
0.0%
230.4k
8.5%
8.5%
0.0%
0.0%
0.0%
0.0%
250k
0.0%
0.0%
-7.8%
-7.8%
-7.8%
5.3%
0.5M
0.0%
0.0%
-7.8%
-7.8%
-7.8%
1M
0.0%
-7.8%
-7.8%
1.
148
(1)
0.5 Mbps
1 Mbps
691.2 kbps
1.3824 Mbps
921.6 kbps
1.8432 Mbps
UBRR = 0, = 0.0%
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 63. UBRR
fosc = 16.0000 MHz
(bps)
U2X = 0
UBRR
fosc = 18.4320 MHz
U2X = 1
UBRR
U2X = 0
UBRR
fosc = 20.0000 MHz
U2X = 1
UBRR
U2X = 0
UBRR
U2X = 1
UBRR
2400
416
-0.1%
832
0.0%
479
0.0%
959
0.0%
520
0.0%
1041
0.0%
4800
207
0.2%
416
-0.1%
239
0.0%
479
0.0%
259
0.2%
520
0.0%
9600
103
0.2%
207
0.2%
119
0.0%
239
0.0%
129
0.2%
259
0.2%
14.4k
68
0.6%
138
-0.1%
79
0.0%
159
0.0%
86
-0.2%
173
-0.2%
19.2k
51
0.2%
103
0.2%
59
0.0%
119
0.0%
64
0.2%
129
0.2%
28.8k
34
-0.8%
68
0.6%
39
0.0%
79
0.0%
42
0.9%
86
-0.2%
38.4k
25
0.2%
51
0.2%
29
0.0%
59
0.0%
32
-1.4%
64
0.2%
57.6k
16
2.1%
34
-0.8%
19
0.0%
39
0.0%
21
-1.4%
42
0.9%
76.8k
12
0.2%
25
0.2%
14
0.0%
29
0.0%
15
1.7%
32
-1.4%
115.2k
-3.5%
16
2.1%
0.0%
19
0.0%
10
-1.4%
21
-1.4%
230.4k
8.5%
-3.5%
0.0%
0.0%
8.5%
10
-1.4%
250k
0.0%
0.0%
-7.8%
2.4%
0.0%
0.0%
0.5M
0.0%
0.0%
-7.8%
0.0%
1M
0.0%
0.0%
1.
(1)
1 Mbps
2 Mbps
1.152 Mbps
2.304 Mbps
1.25 Mbps
2.5 Mbps
UBRR = 0, = 0.0%
149
2486NAVR07/04
TWI
TWI TWI
128 SCL SDA
TWI
7 128
400 kHz
AVR
Figure 68. TWI

VCC
Device 1
Device 2
Device 3
........
Device n
R1
R2
SDA
SCL
TWI
Table 64. TWI
150
SCL
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 68 TWI
TWI "0 TWI TWI

TWI
AVR
400 pF 7
TWI P 229
100 kHz 400 kHz
( )
TWI
Figure 69.
SDA
SCL
Data Stable
Data Stable
Data Change
START/STOP
START
STOP START STOP
START STOP START
REPEATED START
REPEATED START STOP
START START REPEATED
START START START STOP SCL
SDA
Figure 70. START REPEATED START STOP
SDA
SCL
START
STOP
START
REPEATED START
STOP
151
2486NAVR07/04
TWI 9 7 1 READ/WRITE
1 READ/WRITE 1
SCL (ACK) SDA
ACK SDA STOP
REPEATED START SLA+R
SLA+W READ WRITE
MSB 0000 000
ACK SDA
Write
ACK SDA
Read
1111 xxx
Figure 71.
Addr MSB
Addr LSB
R/W
ACK
SDA
SCL
1
START
152
ATmega8(L)
2486NAVR07/04
ATmega8(L)
TWI 9 8 1
START STOP 9
SCL SDA SDA NACK
NACK
MSB
Figure 72.
Data MSB
Data LSB
ACK
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
1
SLA+R/W
STOP, REPEATED
START or Next
Data Byte
Data Byte
START SLA+R/W STOP START

STOP SCL
SCL SCL
SCL
SCL SCL
SCL TWI
Figure 73SLA+R/W STOP
Figure 73.
Addr MSB
Addr LSB
R/W
ACK
Data MSB
Data LSB
ACK
SDA
SCL
1
START
SLA+R/W
7
Data Byte
STOP
153
2486NAVR07/04
TWI
SCL
SCL / SCL /
Figure 74. SCL
TA low
TA high
SCL from
Master A
SCL from
Master B
SCL Bus
Line
TBlow
Masters Start
Counting Low Period
TBhigh
Masters Start
Counting High Period
SDA SDA
SDA
SDA
154
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 75.
START
SDA from
Master A
Master A Loses
Arbitration, SDAA SDA
SDA from
Master B
SDA Line
Synchronized
SCL Line
REPEATED START
STOP
REPEATED START STOP
SLA+R/W
155
2486NAVR07/04
TWI
TWIFigure 76AVR
Figure 76. TWI
Slew-rate
Control
SDA
Spike
Filter
Slew-rate
Control
Spike
Filter
Bus Interface Unit

START / STOP
Control
Spike Suppression
Arbitration detection
Address/Data Shift
Register (TWDR)
Address Match Unit

Address Register
(TWAR)
Address Comparator
SCL SDA
156
Bit Rate Generator

Prescaler
Bit Rate Register

(TWBR)
Ack
Control Unit
Status Register
(TWSR)
Control Register
(TWCR)
State Machine and

Status control
TWI Unit
SCL
SCL SDAMCU TWI

TWI 50 ns
SCL SDA I/O
ATmega8(L)
2486NAVR07/04
ATmega8(L)
TWI SCL TWI

TWSR TWBR TWI
CPU TWI SCL 16
SCL TWI
SCL
CPU Clock frequency
SCL frequency = ------------------------------------------------------------TWPS
16 + 2(TWBR) 4
TWBR = TWI
TWPS = TWI
Note:
TWI TWBR 10 SDA SCL

TWI Start + SLA + R/W
( )
TWDRSTART/STOP
TWDR 8 TWDR
(N)ACK (N)ACK
TWI TWCR
(N)ACK TWCR
START/STOP TWI START REPEATED START
STOP MCU START/STOP TWI
START/STOP TWI MCU
TWI
TWI
TWAR 7
TWAR TWI TWGCE "1
TWITWCRMCU
MCU
TWI TWI TWCR TWI

TWI TWINT
TWI TWSR
TWSR TWINT "1
SCL TWI
TWINT
TWI START/REPEATED START
TWI SLA+R/W
TWI
TWI
TWI ( )
TWI
TWI STOP REPEATED START
START STOP
157
2486NAVR07/04
TWI
TWI TWBR
Bit
TWBR7
TWBR6
TWBR5
TWBR4
TWBR3
TWBR2
TWBR1
TWBR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TWBR
Bits 7..0 TWI

TWBR SCL
P 157
TWI TWCR
Bit
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
R/W
R/W
R/W
R/W
R/W
R/W
TWCR
TWCR TWITWISTART
STOP TWDR
TWDR TWDR
Bit 7 TWINT: TWI

TWI TWINT SREG I TWCR
TWIE MCU TWI TWINT SCL
TWINT "1
"0 TWI
TWINT TWAR TWSR
TWDR
Bit 6 TWEA: TWI
TWEA TWEA ACK
1.
2. TWAR TWGCE
3. /
TWEA
Bit 5 TWSTA: TWI START
CPU TWSTA TWI
START
STOP START START
TWSTA
Bit 4 TWSTO: TWI STOP
TWSTOTWI STOP TWSTO
TWSTO
STOP TWI
SCL SDA
Bit 3 TWWC:TWI
TWINT TWDR TWWC TWINT
TWDR
158
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Bit 2 TWEN: TWI
TWEN TWITWITWEN"1TWII/O
SCL SDA TWI
TWI
Bit 1 Res:
0
Bit 0 TWIE: TWI
SREG I TWIE TWINT "1 TWI
159
2486NAVR07/04
TWI TWSR
Bit
TWS7
TWS6
TWS5
TWS4
TWS3
TWPS1
TWPS0
R/W
R/W
TWSR
Bits 7..3 TWS: TWI

5 TWI
TWSR 5 2
"0
Bit 2 Res:
"0
Bits 1..0 TWPS: TWI
/
Table 65. TWI
TWPS1
TWPS0
16
64
P 157 TWPS1..0
TWI TWDR
Bit
TWD7
TWD6
TWD5
TWD4
TWD3
TWD2
TWD1
TWD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TWDR
TWDR TWDR
TWI (TWINT )
TWINT TWDR
TWDR
MCU TWI TWDR
ACK TWI
CPU ACK
Bits 7..0 TWD: TWI
TWI( )
TWAR
Bit
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TWAR
TWAR 7 TWI
TWAR
160
ATmega8(L)
2486NAVR07/04
ATmega8(L)
TWAR LSB (0x00)
Bits 7..1 TWA: TWI
Bit 0 TWGCE: TWI

MCU TWI
TWI
AVR TWI
START TWI TWI TWI
TWCR TWI
TWIESREGTWINT
TWIE TWINT
TWI
TWINT "1 TWI
TWI TWSR TWI
TWCR TWCR TWDR
TWI TWI
Figure 77 TWI
Application
Action
Figure 77. TWI

1. Application
writes to TWCR to
initiate
transmission of
START
TWI
Hardware
Action
TWI bus
3. Check TWSR to see if START was

sent. Application loads SLA+W into
TWDR, and loads appropriate control
signals into TWCR, makin sure that
TWINT is written to one,
and TWSTA is written to zero.
START
2. TWINT set.
Status code indicates
START condition sent
SLA+W
5. Check TWSR to see if SLA+W was

sent and ACK received.
Application loads data into TWDR, and
loads appropriate control signals into
TWCR, making sure that TWINT is
written to one
4. TWINT set.
SLA+W sent, ACK
received
Data
7. Check TWSR to see if data was sent

and ACK received.
Application loads appropriate control
signals to send STOP into TWCR,
making sure that TWINT is written to one
6. TWINT set.
data sent, ACK received
STOP
Indicates
TWINT set
1. TWI START TWCR TWI

START TWINT
TWINT "1 TWCR TWINT TWI
TWINT TWI START
2. STARTTWCR TWINTTWCR
START
3. TWSR START TWSR
SLA+W TWDR TWDR

TWDRSLA+WTWCRTWISLA+W
TWINT TWINT
161
2486NAVR07/04
"1 TWCR TWINT TWI

TWINT TWI
4. TWCR TWINT TWDR
5. TWSRACK TWSR
TWDR TWCR
TWI TWDR
TWINT TWCR TWINT TWI
TWINT TWI
6. TWCR TWINT TWSR
7. TWSRACK TWSR
TWCR TWI STOP

TWINT TWINT "1
TWCR TWINT TWI
TWINT TWI STOP TWINT STOP
TWI
TWI TWINT TWINT

SCL
TWINT TWI TWI

TWDR
TWI TWCR
TWCR TWINT TWINT "1 TWI
TWCR
162
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ldi
r16, (1<<TWINT)|(1<<TWSTA)|
(1<<TWEN)
out TWCR, r16

wait1:
in
r16,TWCR
C
TWCR = (1<<TWINT)|(1<<TWSTA)|
START
(1<<TWEN)
while (!(TWCR & (1<<TWINT)))
;
TWINT TWINT
START
sbrs r16,TWINT
3
rjmp wait1
in
r16,TWSR
andi r16, 0xF8
cpi
if ((TWSR & 0xF8) != START)

ERROR();
r16, START
brne ERROR
ldi r16, SLA_W
TWDR = SLA_W;
out
TWDR, r16
TWCR = (1<<TWINT) | (1<<TWEN);
ldi
r16, (1<<TWINT) | (1<<TWEN)
out TWCR, r16

wait2:
in
r16,TWCR

;
sbrs r16,TWINT
5
rjmp wait2
in
r16,TWSR
andi r16, 0xF8
cpi
r16, MT_SLA_ACK
if ((TWSR & 0xF8) !=

MT_SLA_ACK)
ERROR();
brne ERROR
ldi r16, DATA
TWDR = DATA;
out
TWDR, r16
TWCR = (1<<TWINT) | (1<<TWEN);
ldi
r16, (1<<TWINT) | (1<<TWEN)
out TWCR, r16

wait3:
in
r16,TWCR

;
sbrs r16,TWINT
7
rjmp wait3
in
r16,TWSR
andi r16, 0xF8
cpi
r16, MT_DATA_ACK
brne ERROR
ldi r16, (1<<TWINT)|(1<<TWEN)|
(1<<TWSTO)
out
if ((TWSR & 0xF8) !=

MT_DATA_ACK)
ERROR();
TWCR = (1<<TWINT)|(1<<TWEN)|
TWI
START
SLA_W TWDR
TWINT
TWINT TWINT
SLA+W
ACK/NACK
TWI
MT_SLA_ACK
TWDR
TWINT
TWINT TWINT
DATA
ACK/NACK
TWI
MT_DATA_ACK
STOP
(1<<TWSTO);
TWCR, r16
163
2486NAVR07/04
TWI 4 (MT) (MR) (ST)

(SR) TWI MT TWI
EEPROM MR EEPROM
TWI SR
S START
RsREPEATED START
R (SDA )
W (SDA )
A (SDA )
A (SDA )
Data8
P STOP
SLA
Figure 79 Figure 85 TWINT
TWSR 0
/ TWI TWI TWINT
TWINT TWSR Table 66 Table 69.
164
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 78
START MT MR SLA+W
MT SLA+R MR
"0
Figure 78.
VCC
Device 1
Device 2
MASTER
TRANSMITTER
SLAVE
RECEIVER
Device 3
........
R1
Device n
R2
SDA
SCL
TWCR START
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
TWENTWSTA"1START TWINT
"1 TWINT TWI START
TWINT TWSR 0x08 ( Table 66) MT
SLA+W TWDR SLA+W TWINT
TWI TWCR
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
SLA+W TWINT TWSR

0x18 0x20 0x38 Table 66
SLA+W TWDR TWDR
TWINT TWCR TWWC
TWDR TWINT TWCR
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
STOP REPEATED
START STOP TWCR
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
REPEATED START TWCR

TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
165
2486NAVR07/04
REPEATED START ( 0x10)

STOP REPEATED START
Table 66.
TWCR
(TWSR)
"0
2 2
/ TWDR
STA
STO
TWIN
T
TWE
A
0x08
START
SLA+W
2
SLA+W
ACK NOT ACK
0x10
START
SLA+W
SLA+W
ACK NOT ACK
SLA+R
SLA+R
0x18
SLA+W
ACK
( )
TWDR
TWDR
1
0
0
1
1
1
X
X
ACK NOT ACK

START
STOP TWSTO
STOP START TWSTO
ACK NOT ACK
TWDR
1
0
0
1
1
1
X
X
TWDR
1
0
0
1
1
1
X
X
TWDR
0x20
SLA+W
NOT ACK
( )
START
STOP TWSTO
STOP START TWSTO
TWDR
0x28
ACK
( )
TWDR
TWDR
ACK NOT ACK

START
STOP TWSTO
STOP START TWSTO
ACK NOT ACK
TWDR
1
0
0
1
1
1
X
X
TWDR
TWDR
0x30
NOT ACK
( )
START
STOP TWSTO
STOP START TWSTO
TWDR
0x38
SLA+W
TWDR
2
START
TWDR
166
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 79.
MT
Successfull
transmission
to a slave
receiver
SLA
$08
DATA
$18
$28
Next transfer
started with a
repeated start
condition
RS
SLA
$10
Not acknowledge
received after the
slave address
$20
MR
Not acknowledge
received after a data
byte
$30
Arbitration lost in slave
address or data byte
A or A
Other master
continues
$38
Arbitration lost and
addressed as slave
$68
From master to slave
From slave to master
A or A
Other master
continues
$38
Other master
continues
$78
DATA
To corresponding
states in slave mode
$B0
Any number of data bytes

and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero
167
2486NAVR07/04
Figure 80
START MT MR SLA+W
MT SLA+R MR
"0
Figure 80.
VCC
Device 1
Device 2
MASTER
RECEIVER
SLAVE
TRANSMITTER
Device 3
........
R1
Device n
R2
SDA
SCL
TWCR START
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
TWENTWSTA"1START TWINT
"1 TWINT TWI START
TWINT TWSR 0x08 ( Table 66) MR
SLA+R TWDR SLA+R TWINT
TWI TWCR
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
SLA+R TWINT TWSR

0x380x40 0x48 Table 67 TWDR
TWINT
MR NACK STOP
REPEATED START STOP TWCR
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
REPEATED START TWCR

TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
REPEATED START ( 0x10)

STOP REPEATED START
Table 67.
(TWSR)
"0
168
TWCR
2 2
/ TWDR
STA
STO
TWIN
T
TWE
A
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 67.
0x08
START
SLA+R
SLA+R
ACK NOT ACK
0x10
START
SLA+R
SLA+R
ACK NOT ACK
SLA+W
SLA+W
0x38
SLA+R NOT ACK
TWDR
START
NOT ACK
TWDR
0x40
SLA+R
ACK
TWDR
TWDR
0x48
SLA+R
NOT ACK
TWDR
TWDR
ACK
1
0
0
1
1
1
X
X
TWDR
0x50
ACK
NOT ACK
STOP TWSTO
STOP START TWSTO
1
0
0
1
1
1
X
X
0x58
START
NOT ACK
ACK
START
STOP TWSTO
STOP START TWSTO
169
2486NAVR07/04
Figure 81.
MR
Successfull
reception
from a slave
receiver
SLA
DATA
$40
$08
DATA
$50
$58
Next transfer
started with a
repeated start
condition
RS
SLA
$10
Not acknowledge
received after the
slave address
$48
MT
Arbitration lost in slave

address or data byte
Other master
continues
A or A
$38
Arbitration lost and
addressed as slave
$38
Other master
continues
$68
$78
To corresponding
states in slave mode
$B0
DATA
Other master
continues

Figure 82
"0
Figure 82.
VCC
Device 1
Device 2
SLAVE
RECEIVER
MASTER
TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
TWAR TWCR
TWAR
170
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
ATmega8(L)
2486NAVR07/04
ATmega8(L)
7 TWI LSB TWI
0x00
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
TWENTWITWEA()
ACK TWSTA TWSTO
TWAR TWCR TWI (
TWAR TWGCE ) 0 (
) TWINT TWSR
Table 68 TWI ( 0x68 0x78) CPU
TWEA TWI SDA

TWEA TWI
TWEA TWEA TWI
TWI
/ CPU
TWISCLTWCINTAVRTWI
AVR SCL
MCU TWDR
171
2486NAVR07/04
Table 68.
(TWSR)
"0
0x60
TWCR
22
SLA+W
ACK
/ TWDR
TWDR
STA
STO
TWIN
T
TWE
A
TWDR
0x68
0x70
SLA+R/W
SLA+W
ACK
TWDR
ACK
TWDR
0x80
0x88
SLA+R/W
ACK
TWDR
SLA+W
ACK
SLA+W
NOT ACK
TWDR
NOT ACK
ACK
NOT ACK
ACK
TWDR
NOT ACK
ACK
TWDR
TWDR
NOT ACK
ACK
TWDR
0x78
NOT ACK
ACK
SLA
GCA
SLA
TWGCE = 1 GCA
SLA
GCA START
SLA
TWGCE = 1 GCA
START
172
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 68.
0x90
0x98
ACK
NOT ACK
ACK
0
STOP
START
SLA
GCA
SLA
TWGCE = 1 GCA
SLA
GCA START
SLA
TWGCE = 1 GCA
START
0xA0
NOT ACK
SLA
GCA
SLA
TWGCE = 1 GCA
SLA
GCA START
SLA
TWGCE = 1 GCA
START
173
2486NAVR07/04
Figure 83.
Reception of the own
slave address and one or
more data bytes. All are
acknowledged
SLA
DATA
$60
DATA
$80
Last data byte received

is not acknowledged
P or S
$80
$A0
P or S
$88
Arbitration lost as master
and addressed as slave
$68
Reception of the general call
address and one or more data
bytes
General Call
DATA
$70
DATA
$90
Last data byte received is

not acknowledged
P or S
$90
$A0
P or S
$98
Arbitration lost as master and
addressed as slave by general call
$78
174
DATA

ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 84
"0
Figure 84.
VCC
Device 1
Device 2
SLAVE
TRANSMITTER
MASTER
RECEIVER
........
Device 3
R1
Device n
R2
SDA
SCL
TWAR TWCR
TWAR
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
7 TWI LSB TWI

0x00
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
TWENTWITWEA()
ACK TWSTA TWSTO
TWAR TWCR TWI (
TWAR TWGCE ) "1
( ) TWI TWSR
Table 69 TWI ( 0xB0) CPU
TWEA TWI 0xC0 0xC8

1
( ACK) 0xC8
TWEA TWI TWEA
TWEA TWI
TWI
/ CPU
TWISCLTWCINTAVR
AVR SCL
MCU TWDR
175
2486NAVR07/04
Table 69.
(TWSR)
"0
0xA8
TWCR
22
/ TWDR
SLA+R
ACK
0xB0
0xB8
SLA+R/W
SLA+R
ACK
TWDR
ACK
0xC0
TWDR
NOT ACK
TWDR
TWDR
STA
STO
TWIN
T
TWE
A
TWDR
176
SLA
GCA
SLA
TWGCE = 1 GCA
SLA
GCA START
SLA
TWGCE = 1 GCA
START
TWDR
TWDR
NOT ACK
ACK
TWDR
TWDR
NOT ACK
ACK
TWDR
(TWAE = 0);
ACK
NOT ACK
ACK
TWDR
0xC8
SLA
GCA
SLA
TWGCE = 1 GCA
SLA
GCA START
SLA
TWGCE = 1 GCA
START
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 85.
Reception of the own
slave address and one or
more data bytes
SLA
DATA
$A8
Arbitration lost as master
and addressed as slave
DATA
$B8
P or S
$C0
$B0
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
All 1's
P or S
$C8
DATA

TWI Table 70
0xF8 TWINT "0
TWI
0x00 START STOP
ACKSTARTSTOP
TWINT TWSTO
"1 TWINT TWI TWSTO
(TWCR ) SDA SCL STOP
Table 70.
(TWSR)
0
TWCR
2 2
/ TWDR
0xF8
TWINT = 0
TWDR
0x00
START
STOP
TWDR
STA
STO
TWIN
T
TWE
A
No TWCR action
STOP
TWSTO
177
2486NAVR07/04
TWI
TWIEEPROM
1.
2. EEPROM
3.
4.
MT MR
EEPROM
REPEATED START REPEATED START
Figure 86. TWI EEPROM

Master Transmitter
SLA+W
ADDRESS
Master Receiver
S = START
SLA+R
DATA
Rs = REPEATED START
Transmitted from master to slave
Rs
P = STOP
Transmitted from slave to master
TWI
Figure 87.
VCC
Device 1
Device 2
Device 3
MASTER
TRANSMITTER
MASTER
TRANSMITTER
SLAVE
RECEIVER
........
Device n
R1
R2
SDA
SCL
178
READ/WRITE SDA
"0
START
ATmega8(L)
2486NAVR07/04
ATmega8(L)
SLA
SDA "0
SLA
SR ST SLA
READ/WRITE
START
Figure 88 TWI
Figure 88.
START
SLA
Data
Arbitration lost in SLA
Own
Address / General Call
received
No
STOP
Arbitration lost in Data
38
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Yes
Direction
Write
68/78
Read
B0
Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
179
2486NAVR07/04
AIN0 AIN1 AIN0 AIN1

ACO /
1
Figure 89
Figure 89. (2)

BANDGAP
REFERENCE
ACBG
ACME
ADEN
ADC MULTIPLEXER
OUTPUT (1)
Notes:
1. P 182Table 72
2. P 2 P 59Table 28
IO SFIOR
Bit
ACME
PUD
PSR2
PSR10
R/W
R/W
R/W
R/W
SFIOR
Bit 3 ACME:
"1 ADC (ADCSRA ADEN "0) ADC
"0 AIN1
P 181
180
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ACSR
Bit
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
ACSR
Bit 7 ACD:
ACD
ACD ACSR
ACIE ACD
Bit 6 ACBG:
ACBG AIN0
P 39
Bit 5 ACO:
ACO 1-2
Bit 4 ACI:
ACIS1 ACIS0 ACI ACIE
SREG I
ACI ACI "1
Bit 3 ACIE:
ACIE "1 I
Bit 2 ACIC:
ACIC T/C1
T/C1
ACIC "0
T/C1 TIMSK TICIE1
Bits 1,0 ACIS1, ACIS0:

Table 71
Table 71. ACIS1/ACIS0
ACIS1
ACIS0
ACIS1/ACIS0 ACSR
ADC7..0 ADC
ADC
(SFIOR ACME) ADC (ADCSRA ADEN 0)
181
2486NAVR07/04
ADMUX MUX2..0
Table 72 ACME ADEN AIN1
Table 72. (1)
ADEN
MUX2..0
xxx
AIN1
xxx
AIN1
000
ADC0
001
ADC1
010
ADC2
011
ADC3
100
ADC4
101
ADC5
110
ADC6
111
ADC7
Note:
182
ACME
1. TQFP MLF ADC7..6
ATmega8(L)
2486NAVR07/04
ATmega8(L)
10
0.5 LSB
2 LSB
13 - 260 s
15 kSPS
6
2 (TQFP MLF )
ADC
0 - VCC ADC
2.56V ADC
ADC
.ATmega8 10 ADCADC 8
C 8 0V (GND)
ADC ADC ADC
Figure 90
ADC AVCC AVCC VCC 0.3V P
188ADC
2.56V AVCC AREF
183
2486NAVR07/04
Figure 90.
ADC CONVERSION
COMPLETE IRQ
15
ADC[9:0]
ADPS1
ADPS0
ADPS2
ADIF
ADFR
ADEN
ADSC
0
ADC DATA REGISTER
(ADCH/ADCL)
ADC CTRL. & STATUS

REGISTER (ADCSRA)
MUX0
MUX2
MUX1
MUX3
ADLAR
REFS0
REFS1
ADC MULTIPLEXER
SELECT (ADMUX)
ADIE
ADIF
8-BIT DATA BUS
MUX DECODER
CHANNEL SELECTION
PRESCALER
AVCC
CONVERSION LOGIC
INTERNAL 2.56V
REFERENCE
SAMPLE & HOLD

COMPARATOR
AREF
10-BIT DAC
GND
BANDGAP
REFERENCE
ADC7
ADC6
ADC5
INPUT
MUX
ADC MULTIPLEXER
OUTPUT
ADC4
ADC3
ADC2
ADC1
ADC0
ADC 10
GND AREF 1 LSB ADMUX REFSn
AVCC 2.56V AREF AREF
ADMUX MUX ADC

GND ADC ADCSRA
ADEN ADC ADEN
ADEN ADC ADC
ADC10ADCADCHADCL
ADMUX ADLAR
8 ADCH
ADCL ADCH
ADCL ADC ADCL
184
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ADCH ADC
ADCH ADC ADCH ADCL
ADCADCHADCLADC
ADC ADSC "1

ADC
ADC ADC
ADC ADC
ADCSRA ADSC 1 ADC
ADC ADIF
ADC
Figure 91. ADC

ADEN
START
Reset
7-BIT ADC PRESCALER
CK/128
CK/64
CK/32
CK/16
CK/8
CK/4
CK/2
CK
ADPS0
ADPS1
ADPS2
ADC CLOCK SOURCE
50 kHz 200 kHz

10 200 kHz
ADC 100 kHz CPU

ADC ADCSRA ADPS ADCSRA
ADEN ADC ADEN 1
ADEN
ADCSRAADSCADC
13 ADC ADC (ADCSRA
ADEN ) 25 ADC
ADC 1.5 ADC
ADC 13.5 ADC ADC
ADC ADIF ADSC ( )
ADSC ADC
ADSC
Table 73
185
2486NAVR07/04
Figure 92. ADC ( )

Next
Conversion
First Conversion
Cycle Number
12
13
14
15
16
17
18
19
20
21
23
22
24
25
ADC Clock
ADEN
ADSC
ADIF
ADCH
MSB of Result
ADCL
LSB of Result
MUX and REFS

Update
Conversion
Complete
Sample & Hold
MUX and REFS

Update
Figure 93. ADC

One Conversion
Cycle Number
Next Conversion
10
11
12
13
ADC Clock
ADSC
ADIF
ADCH
MSB of Result
ADCL
LSB of Result
Sample & Hold
Conversion
Complete
MUX and REFS

Update
MUX and REFS

Update
Figure 94. ADC

One Conversion
Cycle Number
11
12
Next Conversion
13
ADC Clock
ADSC
ADIF
ADCH
MSB of Result
ADCL
LSB of Result
Conversion
Complete
186
Sample &Hold
MUX and REFS
Update
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 73. ADC
& (
)
( )
13.5
25
1.5
13
ADMUXMUXnREFS1:0CPU
ADC (ADCSRA ADIF )

ADSC
ADSC ADC
ADMUX
ADFR ADEN ADMUX
ADMUX
1. ADFR ADEN 0
2. ADC
3.
ADMUX ADC
187
2486NAVR07/04
ADC
ADSC ADC
ADSC ADC
ADC
ADC(VREF)ADCVREF
0x3FF VREF AVCC 2.56V AREF
AVCCADC2.56V(VBG)
AREF ADC AREF
VREF AREF
VREF
AREF
AREF
AVCC 2.56V ADC
ADC
ADCCPUI/O
ADC
1. ADC
ADC
2. ADC ( ) CPU ADC
3. ADC ADCCPU
ADC ADC
CPU ADC ADC
CPU
ADC ADC
ADEN
188
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 95. ADC ADCn

ADC
( ) (S/H)
ADC10 k
S/H
S/H
(fADC/2)
ADC
Figure 95.
IIH
ADCn
1..100 k
CS/H= 14 pF
IIL
VCC/2
(EMI)
1.
2. Figure 96 AVCC LC VCC

3. ADC CPU
4. ADC[3..0]
(ADC4 ADC5) ADC4 ADC5
ADC
189
2486NAVR07/04
Analog Ground Plane
PC2 (ADC2)
PC3 (ADC3)
PC4 (ADC4/SDA)
PC5 (ADC5/SCL)
VCC
GND
Figure 96. ADC
PC1 (ADC1)
PC0 (ADC0)
ADC7
10H
GND
AREF
100nF
ADC6
AVCC
PB5
ADC
n ADC GND VREF 2n (LSBs)

0 2n-1
(0x000 0x001) (0.5 LSB) 0

LSB
Figure 97.
Output Code
Ideal ADC
Actual ADC
Offset
Error
190
VREF Input Voltage
ATmega8(L)
2486NAVR07/04
ATmega8(L)
(0x3FE 0x3FF) (
1.5 LSB) 0 LSB
Figure 98.
Gain
Error
Output Code
Ideal ADC
Actual ADC
VREF Input Voltage
(INL)
INL0 LSB
Figure 99. (INL)

Output Code
INL
Ideal ADC
Actual ADC
VREF
Input Voltage
(DNL) ( ) (1 LSB)
0 LSB
191
2486NAVR07/04
Figure 100. (DNL)

Output Code
0x3FF
1 LSB
DNL
0x000
0
ADC
VREF Input Voltage
(1 LSB)
0.5 LSB
( )
0.5 LSB
(ADIF ) ADC (ADCL, ADCH)
V IN 1024
ADC = --------------------------V REF
VIN VREF (P 192Table 74 P 193Table
75 ) 0x000 0x3FF 1LSB
ADC ADMUX
Bit
REFS1
REFS0
ADLAR
MUX3
MUX2
MUX1
MUX0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADMUX
Bit 7:6 REFS1:0:

Table 74
(ADCSRA ADIF )
AREF
Table 74. ADC
192
REFS1
REFS0
AREF Vref
AVCC AREF
2.56V AREF
Bit 5 ADLAR: ADC
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ADLARADCADCADLAR
ADLAR ADC
P 195ADC ADCL ADCH
Bits 3:0 MUX3:0:
ADC Table 75
(ADCSRA ADIF )
Table 75.
MUX3..0
0000
ADC0
0001
ADC1
0010
ADC2
0011
ADC3
0100
ADC4
0101
ADC5
0110
ADC6
0111
ADC7
1000
1001
1010
1011
1100
1101
1110
1.23V (VBG)
1111
0V (GND)
193
2486NAVR07/04
ADC A
ADCSRA
Bit
ADEN
ADSC
ADFR
ADIF
ADIE
ADPS2
ADPS1
ADPS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADCSRA
Bit 7 ADEN: ADC

ADENADCADCADC
Bit 6 ADSC: ADC

ADSC ADC ADSC
( ADC ADSC ADC
ADSC) 25 ADC 13 ADC
ADSC "1ADSC
Bit 5 ADFR: ADC

ADC
Bit 4 ADIF: ADC

ADC ADIF ADIE SREG
I ADC ADIF
1 ADIF ADCSRA
SBI CBI
Bit 3 ADIE: ADC
ADIE SREG I ADC
194
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Bits 2:0 ADPS2:0: ADC
XTAL ADC
Table 76. ADC
ADPS2
ADPS1
ADPS0
16
32
64
128
ADC ADCL ADCH

ADLAR = 0
Bit
ADLAR = 1
Bit
15
14
13
12
11
10
ADC9
ADC8
ADCH
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
15
14
13
12
11
10
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
ADC1
ADC0
ADCL
ADC 2
ADCL ADC ADCH

8 ADCH
ADCL ADCH
ADMUX ADLAR MUXn
ADLAR 1 ( )
ADC9:0: ADC
ADC P 192ADC
195
2486NAVR07/04
(RWW, Read-WhileWrite)
Boot Loader MCU - (ReadWhile-Write RWW) MCU

Flash Boot Loader Boot Loader
( ) Flash
Boot Loader Flash Boot Loader
Boot Loader Boot Loader
Boot Loader
RWW
Boot
( Boot )
(1)
RWW
Note:
1. Flash ( P 213Table 93 )
Flash Flash Boot Loader ( Figure 102)

BOOTSZ P 207Table 82 Figure 102
Flash
Flash Boot (Boot

0) P 199Table 78 SPM
Boot Loader
(Boot Loader
Section) BLS
Boot Loader BLS BLS

SPM SPM Flash BLS Boot Loader
Boot Loader (Boot 1) P 199Table 79
RWW Flash RWW

Flash
CPU RWW CPU Boot Loader

BOOTSZ Flash
- (RWW) - (NRWW) RWW NRWW P 207Table 83 P 198Figure 102
RWW NRWW
NRWW CPU
Boot Loader RWW "RWW

( ) Boot Loader
RWW
196
Boot Loader RWW Flash

NRWW Flash RWW
RWW ( call/jmp/lpm
)
Boot Loader Boot Loader NRWW RWW
(SPMCSR) RWW
RWWSB RWW
RWWSBRWWSBP 200 SPMCR
ATmega8(L)
2486NAVR07/04
ATmega8(L)
RWW NRWW
Boot Loader RWW NRWW Boot

Loader NRWW CPU
Table 77. RWW
Z
?
CPU ?
RWW
?
RWW
NRWW
NRWW
Figure 101. RWW NRWW
Read-While-Write
(RWW) Section
Z-pointer
Addresses RWW
section
Z-pointer
Addresses NRWW
section
No Read-While-Write
(NRWW) Section
CPU is Halted
during the Operation
Code Located in
NRWW Section
Can be Read during
the Operation
197
2486NAVR07/04
Figure 102. (1)

Program Memory
BOOTSZ = '10'
Program Memory
BOOTSZ = '11'
$0000
No Read-While-Write Section
Read-While-Write Section
End RWW
Start NRWW
Boot Loader Flash Section
End Application
Start Boot Loader
Flashend
$0000
End RWW
Start NRWW
End Application
Start Boot Loader
Flashend
Program Memory
BOOTSZ = '01'
Program Memory
BOOTSZ = '00'
End RWW
Start NRWW
End Application
Start Boot Loader
Flashend
Note:
$0000
$0000
Application flash Section
End RWW, End Application

Start NRWW, Start Boot Loader
Flashend
1. P 207Table 82
Boot Loader Flash Boot Loader

Boot
Flash MCU
MCU Boot Loader Flash
MCU Flash
MCU Flash
Table 78 Table 79 Boot

( 2) SPM
Flash / ( 3)
LPM/SPM Flash /
198
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 78. Boot 0 ( )(1)
BLB0
BLB02
BLB01
SPM/LPM
SPM
SPM
Boot Loader LPM
Boot Loader
Boot Loader LPM

Boot Loader
Note:
1. 1 0
Table 79. Boot 1 (Boot Loader )(1)

BLB1
BLB12
BLB11
SPM/LPM Boot Loader
SPM Boot Loader
SPM Boot Loader

LPM Boot Loader
Boot Loader
LPM Boot Loader

Boot Loader
Note:
1. 1 0
Boot Loader
USART SPI Boot
Boot Boot Loader
MCU
Boot Boot
199
2486NAVR07/04
Table 80. Boot (1)
BOOTRST
Note:
SPMCR
= ( 0x0000)
=Boot Loader ( P 207Table 82 )
1. 1 , 0
Boot Loader
Bit
SPMIE
RWWSB
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
R/W
R/W
R/W
R/W
R/W
R/W
SPMCR
Bit 7 SPMIE: SPM

SPMIE I SPM SPMCSR
SPMEN SPM
Bit 6 RWWSB:RWW
RWW ( ) RWWSB 1 RWWSB
RWW RWWSRE 1 RWWSB
RWWSB
Bit 5 Res:
ATmega8 "0
Bit 4 RWWSRE:RWW
RWW()RWW(RWWSB"1)
(SPMEN)RWW RWWSRE
SPMEN"1SPMRWW
Flash (SPMEN ),RWW Flash
RWWSRE Flash
Bit 3 BLBSET: Boot
SPMEN SPM R0
Boot R1 Z
SPM BLBSET
SPMCSR BLBSET SPMEN LPM
( Z Z0) P 204

Bit 2 PGWRT:
SPMEN SPM
Flash Z R1 R0
SPM PGWRT
NRWW CPU
Bit 1 PGERS:
SPMEN SPM
Z R1 R0
SPMPGERSNRWW
CPU
Bit 0 SPMEN:
200
ATmega8(L)
2486NAVR07/04
ATmega8(L)
SPM RWWSRE
BLBSETPGWRT PGERS SPM
SPMEN SPM R1:R0
Z Z LSB SPM
SPM SPMEN SPMEN 1
10001 01001 00101 00011 00001
Flash
Z SPM
Bit
15
14
13
12
11
10
ZH (R31)
Z15
Z14
Z13
Z12
Z11
Z10
Z9
Z8
ZL (R30)
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
Flash ( P 213Table 93 )
Figure
103Boot Loader
Z
Z SPM Boot Loader Z LPM
Z Z LSB
( Z0)
Figure 103. SPM (1)
BIT
15
ZPCMSB
ZPAGEMSB
Z - REGISTER
1 0
0
PCMSB
PROGRAM
COUNTER
PAGEMSB
PCPAGE
PAGE ADDRESS
WITHIN THE FLASH
PROGRAM MEMORY
PAGE
PCWORD
WORD ADDRESS
WITHIN A PAGE
PAGE
INSTRUCTION WORD
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
Notes:
1. P 208Table 84
2. PCPAGE PCWORD P 213Table 93
201
2486NAVR07/04
Flash
SPM
(
) Flash 1 Boot Loader -
Flash 2
P 206
SPM
( )
Z RAMPZ X0000011
SPMCSR SPMR1 R0
Z PCPAGE Z
RWW NRWW
NRWW CPU
Z R1:R0
00000001 SPMCSR SPM Z
PCWORD SPMCSR
RWWSRE
Note:
EEPROM SPM
Z RAMPZ X0000101
SPMCSR SPMR1 R0
Z PCPAGE Z
RWW NRWW
NRWW CPU
SPM
SPM SPMCSR SPMEN

SPMCSR SPM
BLS RWW P 43
BLS
Boot 11 Boot Loader Boot

Loader Boot Loader
Boot Loader Boot 11 Boot Loader
RWW
( ) RWW
RWW SPMCSR RWWSB P 43
BLS RWW
202
ATmega8(L)
2486NAVR07/04
ATmega8(L)
RWWSRE 1 RWWSB P 206

203
2486NAVR07/04
SPM
Boot Loader R0X0001001SPMCSR

SPM Boot
Loader MCU Boot Loader
Bit
R0
BLB12
BLB11
BLB02
BLB01
Boot Loader Flash Table 78 Table 79

R0 5..2 0 SPMCSR BLBSET SPMEN
SPM Boot Z
Z 0x0001( lOck )
R0 7 6 1 0 "1
Flash
EEPROM SPMCR
EEPROM Flash
SPMCR EECR EEWE
0x0001 Z
SPMCSR BLBSET SPMEN SPMCR CPU
LPM CPU
LPM CPU SPM BLBSET SPMEN
BLBSET SPMEN LPM
Bit
Rd
BLB12
BLB11
BLB02
BLB01
LB2
LB1
0x0000ZSPMCRBLBSET SPMENSPMCSR
CPU LPM (FLB)
P 210Table 88
Bit
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
0x0003 Z SPMCR
BLBSET SPMEN SPMCSR CPU LPM
(FHB)
P 210Table 87
Bit
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
"0
"1
Flash
VCC CPU Flash Flash

Flash
Flash Flash
CPU
Flash ( )
204
ATmega8(L)
2486NAVR07/04
ATmega8(L)
1. Boot Loader Boot Loader Boot
Loader
2. AVR RESET
BOD
3. AVR CPU
SPMCR Flash
SPM Flash
RC Flash Table 81 CPU Flash
Table 81. SPM
Flash ( SPM
)
3.7 ms
4.5 ms
205
2486NAVR07/04
;- RAM Flash
; Y RAM
;Z Flash
;-
;- Boot ( Do_spm )
; ( ) NRWW
;- r0 r1 temp1 (r16) temp2 (r17) looplo (r24)
; loophi (r25) spmcrval (r20)
;
;
;- Boot loader ,
.equ PAGESIZEB = PAGESIZE*2
;PAGESIZEB
.org SMALLBOOTSTART
Write_page:
;
ldi
spmcrval, (1<<PGERS) | (1<<SPMEN)
rcall Do_spm
; RWW
ldi
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
rcall Do_spm
; RAM Flash
ldi
looplo, low(PAGESIZEB)
ldi
loophi, high(PAGESIZEB)
Wrloop:
ld
r0, Y+
ld
r1, Y+
ldi
spmcrval, (1<<SPMEN)
rcall Do_spm
adiw ZH:ZL, 2
sbiw loophi:looplo, 2
brne Wrloop
;
;PAGESIZEB<=256
;PAGESIZEB<=256 subi
subi
sbci
ldi
rcall
ZL, low(PAGESIZEB)
;
ZH, high(PAGESIZEB)
;PAGESIZEB<=256
spmcrval, (1<<PGWRT) | (1<<SPMEN)
Do_spm
; RWW
ldi
rcall Do_spm
;
ldi
looplo, low(PAGESIZEB)
ldi
loophi, high(PAGESIZEB)
subi YL, low(PAGESIZEB)
sbci YH, high(PAGESIZEB)
Rdloop:
lpm r0, Z+
ld
r1, Y+
cpse r0, r1
rjmp Error
sbiw loophi:looplo, 1
brne Rdloop
;
;PAGESIZEB<=256
;
;PAGESIZEB<=256 subi
; RWW
; RWW
206
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Return:
in
temp1, SPMCR
sbrs temp1, RWWSB
; RWWSB "1" RWW
ret
; RWW
ldi
rcall Do_spm
rjmp Return
Do_spm:
; SPM
Wait_spm:
in
temp1, SPMCR
sbrc temp1, SPMEN
rjmp Wait_spm
; spmcrval SPM
;
in
temp2, SREG
cli
; EEPROM
Wait_ee:
sbic EECR, EEWE
rjmp Wait_ee
; SPM
out
SPMCR, spmcrval
spm
; SREG ( )
out
SREG, temp2
ret
ATmega8
Table 82 Table 84
Table 82. Boot
0xF80 0xFFF
0xF7F
0xF80
0x000 0xEFF
0xF00 0xFFF
0xEFF
0xF00
16
0x000 0xDFF
0xE00 0xFFF
0xDFF
0xE00
32
0x000 0xBFF
0xC00 0xFFF
0xBFF
0xC00
Flash
0x000 0xF7F
256
512
102
BOOTSZ1
BOOTSZ0
128
0
0
Note:
Boot
( Boot
Loader
)
Boot
Loader
Flash
Boot
BOOTSZ Figure 102
Table 83. RWW

Flash
- (RWW)
96
0x000 - 0xBFF
- (NRWW)
32
0xC00 - 0xFFF
207
2486NAVR07/04
P 197 RWW NRWW P 196RWW
Table 84. Figure 103 Z

Z
(1)
PCMSB
11
( 12
PC[11:0])
PAGEMSB
( 64
5 PC [4:0])
ZPCMSB
Z12
Z PCMSB
Z0 ZPCMSB PCMSB + 1
ZPAGEMSB
Z5
Z PAGEMSB
Z0 ZPAGEMSB PAGEMSB + 1
PCPAGE
PC[11:5]
Z12:Z6
PCWORD
PC[4:0]
Z5:Z1
( 0)
Note:
208
1. Z15:Z13
Z0 SPM "0 LPM
Z P 201 Flash
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ATmega8 6 (0) (1)

Table 86 1
Table 85.
(1)
1 ( )
1 ( )
BLB12
Boot
1 ( )
BLB11
Boot
1 ( )
BLB02
Boot
1 ( )
BLB01
Boot
1 ( )
LB2
1 ( )
LB1
1 ( )
1. 1 0
Note:
Table 86. (2)
LB
LB2
LB1
Flash EEPROM
(1)
Flash EEPROM
(1)
BLB0
BLB02
BLB01
SPM LPM
SPM
SPM
Boot Loader LPM
Boot Loader
Boot Loader LPM

Boot Loader
BLB1
BLB12
BLB11
SPM/LPM Boot Loader
209
2486NAVR07/04
Table 86. (2)
SPM Boot Loader
SPM Boot Loader

LPM Boot Loader
Boot Loader
LPM Boot Loader

Boot Loader
Notes:
1.
2. 1 , 0
ATmega8 Table 87-Table 88

0
Table 87.
PC6 I/O RESET
1 ( PC6 RESET )
RSTDISBL(4)
WDTON
WDT
1 ( WDTCR
WDT )
SPIEN(1)
0 ( SPI )
CKOPT(2)
1 ( )
EESAVE
EEPROM
1 ( EEPROM
)
BOOTSZ1
Boot ( Table 82)
0 ( )(3)
BOOTSZ0
Boot ( Table 82 )
0 ( )(3)
BOOTRST
1 ( )
Notes:
1.
2.
3.
4.
SPI SPIEN
CKOPT CKSEL P 23
BOOTSZ1..0 Boot P 207Table 82
RSTDISBL
Table 88.
210
BODLEVEL
BOD
1 ( )
BODEN
BOD
1 ( BOD )
SUT1
1 ( )(1)
SUT0
0 ( )(1)
CKSEL3
0 ( )(2)
CKSEL2
0 ( )(2)
CKSEL1
0 ( )(2)
CKSEL0
1 ( )(2)
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Notes:
1. SUT1..0 P 27Table 10
2. CKSEL3..0RC1 MHz P 23Table 2
1(LB1)
EESAVE
Atmel
ATmega8
1. 0x000: 0x1E ( Atmel )
2. 0x001: 0x93 ( 8 KB Flash )
3. 0x002: 0x07 ( ATmega8)
ATmega8RC
0x000 0x0001 0x0002 0x0003 1 2 4 8 MHz
1 MHz OSCCAL
P 28 OSCCAL
211
2486NAVR07/04
ATmega8 Flash EEPROM

250 ns
ATmega8 Figure 104 Table

89
XA1/XA0 XTAL1 Table 91
WR OE Table 92
Figure 104.
+5V
RDY/BSY
PD1
OE
PD2
WR
PD3
BS1
PD4
XA0
PD5
XA1
PD6
PAGEL
PD7
+12 V
VCC
+5V
AVCC
PC[1:0]:PB[5:0]
DATA
RESET
BS2
PC2
XTAL1
GND
Table 89.
I/O
RDY/BSY
PD1
0: , 1:
OE
PD2
( ).
WR
PD3
( ).
BS1
PD4
1(0 , 1
).
XA0
PD5
XTAL 0
XA1
PD6
XTAL 1
PAGEL
PD7
EEPROM
BS2
PC2
2(0 , 1
)
{PC[1:0]: PB[5:0]}
I/O
DATA
212
(OE )
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 90.
PAGEL
Prog_enable[3]
XA1
Prog_enable[2]
XA0
Prog_enable[1]
BS1
Prog_enable[0]
Table 91. XA1 XA0

XTAL1
XA1
XA0
Flash EEPROM ( BS1 )
( BS1 )
Table 92.
1000 0000
0100 0000
0010 0000
0001 0000
Flash
0001 0001
EEPROM
0000 1000
0000 0100
0000 0010
Flash
0000 0011
EEPROM
Table 93. Flash

Flash
4K (8K )
PCWORD
PCPAGE
PCMSB
32
PC[4:0]
128
PC[11:5]
11
Table 94. EEPROM

EEPROM
512
PCWORD
PCPAGE
EEAMSB
EEA[1:0]
128
EEA[8:2]
213
2486NAVR07/04
1. VCC GND 4.5 - 5.5V 100 s

2. RESET XTAL1 6
3. P 213Table 90 Prog_enable "0000" 100 ns
4. RESET 11.5 - 12.5V RESET +12V 100 ns
Prog_enable
RSTDISBL RESET
RC XTAL1
1. P 213Table 90 Prog_enable 0000
2. VCC GND 4.5 - 5.5V RESET 11.5 - 12.5V
3. 100 ns
4. (CKSEL3:0 = 0b0000)
5. RESET 0b0
6.
0xFF Flash
EEPROM( EESAVE )
Flash EEPROM 256
Flash EEPROM(1)
Flash /
EEPROM
Note:
1. EESAVE EEPRPOM
"
1. XA1 XA0 "10
2. BS1 "0
3. DATA 1000 0000
4. XTAL1
5. WR RDY/BSY
6. RDY/BSY
Flash
Flash P 213Table 93 Flash
Flash
A. " Flash"
1. XA1 XA0 "10"
2. BS1 "0
3. DATA 0001 0000 Flash
4. XTAL1
B.
1. XA1 XA0 "00"
2. BS1 "0
214
ATmega8(L)
2486NAVR07/04
ATmega8(L)
3. DATA (0x00 - 0xFF)
4. XTAL1
C.
1. XA1 XA0 "01"
2. DATA (0x00 - 0xFF)
3. XTAL1
D.
1. BS1 "1
2. XA1 XA0 "01"
3. DATA (0x00 - 0xFF)
4. XTAL1
E.
1. BS1 "1
2. PAGEL ( Figure 106 )
F. B E
FLASH P 216Figure 105
8 ( < 256)
G.
1. XA1 XA0 "00
2. BS1 "1
3. DATA (0x00 - 0xFF)
4. XTAL1
H.
1. BS1 = 0
2. WR RDY/BSY
3. RDY/BSY ( Figure 106 )
I. B H Flash
J.
1. XA1 XA0 "10
2. DATA "0000 0000"
3. XTAL1
215
2486NAVR07/04
Figure 105. Flash (1)

PCMSB
PROGRAM
COUNTER
PAGEMSB
PCPAGE
PCWORD
PAGE ADDRESS
WITHIN THE FLASH
WORD ADDRESS
WITHIN A PAGE
PROGRAM MEMORY
PAGE
PAGE
PCWORD[PAGEMSB:0]:
INSTRUCTION WORD
00
01
02
PAGEEND
1. PCPAGE PCWORD P 213Table 93
Note:
Figure 106. Flash (1)

F
A
DATA
0x10
B
ADDR. LOW
C
DATA LOW
DATA HIGH
XX
ADDR. LOW
DATA LOW
DATA HIGH
XX
G
ADDR. HIGH
H
XX
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note:
EEPROM
216
1. "XX" Flash
P 213Table 94 EEPROM EEPROM

EEPROM (
P 214 Flash )
ATmega8(L)
2486NAVR07/04
ATmega8(L)
1. A 0001 0001
2. G (0x00 - 0xFF)
3. B (0x00 - 0xFF)
4. C (0x00 - 0xFF)
5. E ( PAGEL )
K 3 5
L EEPROM
1. BS1 0
2. WR EEPROM RDY/BSY
3. RDY/BSY ( Figure 107 )
Figure 107. EEPROM
K
A
DATA
0x11
G
ADDR. HIGH
ADDR. LOW
DATA
E
XX
B
ADDR. LOW
C
DATA
XX
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Flash
Flash ( P 214 Flash )

1. A 0000 0010
2. G (0x00 - 0xFF)
3. B (0x00 - 0xFF)
4. OE 0 BS1 0 DATA Flash
5. BS1 1 DATA Flash
6. OE 1
EEPROM
( P 214 Flash )
1. A 0000 0011
2. G (0x00 - 0xFF)
3. B (0x00 - 0xFF)
4. OE "0 BS1 "0 DATA EEPROM
217
2486NAVR07/04
5. OE 1
( P 214 Flash )
1. A 0100 0000
2. C "0
3. BS1 0 BS2 0
4. WR RDY/BSY
218
ATmega8(L)
2486NAVR07/04
ATmega8(L)
( P 214 Flash )
1. A 0100 0000
2. C "0
3. BS1 "1 BS2 "0
4. WR RDY/BSY
5. BS1 "0
( P 214 Flash )
1. A 0010 0000
2. C n "0
3. WR RDY/BSY
( P 214 Flash )
1. A 0000 0100
2. OEBS2 BS1 "0 DATA ("0 )
3. OE "0BS2 BS1 1 DATA ("0
)
4. OE "0BS2 "0BS1 1 DATA ("0
)
5. OE 1
Figure 108. BS1 BS2
Fuse low byte
DATA
Lock bits
0
1
Fuse high byte
BS1
BS2
219
2486NAVR07/04
( P 214 Flash )
1. A 0000 1000
2. B 0x00 - 0x02
3. OE BS1 "0 DATA
4. OE "1
( P 214 Flash )
1. A 0000 1000
2. B
3. OE "0 BS1 1 DATA
4. OE 1
Figure 109.
t XLWL
t XHXL
XTAL1
t DVXH
t XLDX
Data & Contol

(DATA, XA0/1, BS1, BS2)
t PLBX
t BVPH
PAGEL
t BVWL
t WLBX
t PHPL
t WL
WR
WH
t PLWL
WLRL
RDY/BSY
t WLRH
Figure 110. (1)

LOAD ADDRESS
(LOW BYTE)
LOAD DATA LOAD DATA

(HIGH BYTE)
LOAD DATA
(LOW BYTE)
t XLXH
tXLPH
LOAD ADDRESS
(LOW BYTE)
tPLXH
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
220
1. Figure 109 (tDVXH tXHXL tXLDX)
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 111. ( )(1)
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
tXLOL
XTAL1
tBVDV
BS1
tOLDV
OE
tOHDZ
DATA
ADDR0 (Low Byte)
ADDR1 (Low Byte)
DATA (High Byte)
DATA (Low Byte)
XA0
XA1
Note:
1. Figure 109 ( tDVXH tXHXL tXLDX)
Table 95. VCC = 5V 10%
VPP
11.5
IPP
tDVXH
XTAL1
67
ns
tXLXH
XTAL1 XTAL1
200
ns
tXHXL
XTAL1
150
ns
tXLDX
XTAL1
67
ns
tXLWL
XTAL1 WR
ns
tXLPH
XTAL1 PAGEL
ns
tPLXH
PAGEL XTAL1
150
ns
tBVPH
PAGEL BS1
67
ns
tPHPL
PAGEL
150
ns
tPLBX
PAGEL BS1
67
ns
tWLBX
WR BS2/1
67
ns
tPLWL
PAGEL WR
67
ns
tBVWL
BS1 WR
67
ns
tWLWH
WR
150
ns
tWLRL
WR RDY/BSY
tWLRH
WR RDY/BSY (1)
tWLRH_CE
WR RDY/BSY
tXLOL
XTAL1 OE
(2)
12.5
250
3.7
4.5
ms
7.5
ms
ns
221
2486NAVR07/04
Table 95. VCC = 5V 10% (Continued)
250
ns
OE DATA
250
ns
OE DATA
250
ns
tBVDV
BS1 DATA
tOLDV
tOHDZ
Notes:
1.
2.
Flash EEPROM tWLRH

tWLRH_CE
RESET SPI Flash EEPROM

SCK MOSI( ) MISO( ) RESET
P 222Table 96 SPI
SPI SPI
Table 96.
I/O
MOSI
PB3
MISO
PB4
SCK
PB5
Figure 112. (1)

+2.7 - 5.5V
VCC
MOSI
PB3
MISO
PB4
SCK
PB5
+2.7 - 5.5V (2)

AVCC
XTAL1
RESET
GND
Notes:
1. XTAL1
2. VCC - 0.3V < AVCC < VCC + 0.3V AVCC 2.7 - 5.5V
EEPROM MCU
EEPROM 0xFF
CKSEL (SCK)
> fck < 12 MHz 2 CPU fck 12 MHz 3 CPU

> fck < 12 MHz 2 CPU fck 12 MHz 3 CPU
222
ATmega8 SCK
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ATmega8 SCK Figure 113
ATmega8 ( Table 98
4 )
1.
RESET SCK "0 VCC GND
SCK SCK RESET
2 CPU
2. 20 ms MOSI
3.
(0x53)
4 0x53 RESET
4. Flash P 213Table 93
5 LSB
7
tWD_FLASH ( Table 97)
5. EEPROM
EEPROM
tWD_EEPROM ( Table 97)
0xFF
6. MISO
7. RESET
8. ( )
RESET 1
VCC
223
2486NAVR07/04
Flash
Flash 0xFF
Flash
0xFF 0xFF tWD_FLASH
0xFF 0xFF tWD_FLASH
Table 97
EEPROM
EEPROM 0xFF
0xFF 0xFF
0xFF EEPROM
0xFF tWD_EEPROM
tWD_EEPROM Table 97
Table 97. Flash EEPROM
tWD_FUSE
4.5 ms
tWD_FLASH
4.5 ms
tWD_EEPROM
9.0 ms
tWD_ERASE
9.0 ms
Figure 113.
SERIAL DATA INPUT
(MOSI)
MSB
LSB
SERIAL DATA OUTPUT

(MISO)
MSB
LSB
SERIAL CLOCK INPUT

(SCK)
SAMPLE
224
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 98.
1010 1100
0101 0011
xxxx xxxx
xxxx xxxx
RESET
1010 1100
100x xxxx
xxxx xxxx
xxxx xxxx
EEPROM Flash
0010 H000
0000 aaaa
bbbb bbbb
oooo oooo
a:b
H( ) o
0100 H000
0000 xxxx
xxxb bbbb
iiii iiii
b H(
) i
0100 1100
0000 aaaa
bbbx xxxx
xxxx xxxx
a:b
EEPROM
1010 0000
00xx xxxa
bbbb bbbb
oooo oooo
EEPROM a:b
o
EEPROM
1100 0000
00xx xxxa
bbbb bbbb
iiii iiii
EEPROM a:b
i
0101 1000
0000 0000
xxxx xxxx
xxoo oooo
0 "1
P 209Table 85
1010 1100
111x xxxx
xxxx xxxx
11ii iiii
0
P 209Table 85
0011 0000
00xx xxxx
xxxx xxbb
oooo oooo
b o
1010 1100
1010 0000
xxxx xxxx
iiii iiii
0 1
P 210Table 88
1010 1100
1010 1000
xxxx xxxx
iiii iiii
0 1
P 210Table 87
0101 0000
0000 0000
xxxx xxxx
oooo oooo
0 1
P 210Table
88
0101 1000
0000 1000
xxxx xxxx
oooo oooo
0 1
P 210Table
87
0011 1000
00xx xxxx
0000 00bb
oooo oooo
Note:
a = b = H =0 - 1 - o = i = x =
SPI
SPI P 230SPI
225
2486NAVR07/04

Note:
AVR
*
........................................................ -55C +125C
*NOTICE:
........................................................ -65C +150C

RESET............ -0.5V VCC+0.5V
RESET .................................. -0.5V +13.0V
.................................................................... 6.0V
I/O ......................................... 40.0 mA
VCC GND ................................ 200.0 mA
TA = -40C 85C VCC = 2.7V 5.5V ( )
VIL
XTAL1
VIL1
XTAL1
VIH
XTAL1 RESET
VIH1
VIH2
VOL
( A,B,C,D)
IOL = 20 mA, VCC = 5V

IOL = 10 mA, VCC = 3V
VOH
( A,B,C,D)
IOH = -20 mA, VCC = 5V

IOH = -10 mA, VCC = 3V
IIL
I/O
VCC = 5.5V,
( )
IIH
I/O
VCC = 5.5V,
( )
RRST
Reset
30
80
Rpu
I/O
20
50
226
(3)
-0.5
0.2 VCC(1)
-0.5
VCC(1)
0.6
VCC(2)
VCC + 0.5
XTAL1
0.8
VCC(2)
VCC + 0.5
RESET
0.9 VCC(2)
VCC + 0.5
0.7
0.5
V
V
0.1
4.2
2.2
V
V
ATmega8(L)
2486NAVR07/04
ATmega8(L)
TA = -40C 85C VCC = 2.7V 5.5V ( )
ICC
(5)
4 MHz, VCC = 3V
(ATmega8L)
mA
8 MHz, VCC = 5V
(ATmega8)
15
mA
4 MHz, VCC = 3V
(ATmega8L)
mA
8 MHz, VCC = 5V
(ATmega8)
mA
WDT , VCC = 3V
28
WDT , VCC = 3V
20
mV
50
nA
VACIO
VCC = 5V
Vin = VCC/2
IACLK
VCC = 5V
Vin = VCC/2
tACID
VCC = 2.7V
VCC = 4.0V
Notes:
-50
750
500
ns
1.
2.
3. ()I/O(20 mAVCC = 5V 10 mAVCC = 3V)
PDIP
1] IOL 400 mA
2] C0 - C5 IOL 200 mA
3] B0 - B7 C6 D0 - D7 XTAL2 IOL 100 mA
TQFP MLF
1] IOL 400 mA
2] C0 - C5 IOL 200 mA
3] C6 D0 - D4 IOL 300 mA
4] B0 - B7 D5 - D7 IOL 300 mA
IOL VOL
4. ()I/O(20 mAVCC = 5V 10 mAVCC = 3V)
PDIP
1] IOH 400 mA
2] C0 - C5 IOH 100 mA
3] B0 - B7 C6 D0 - D7 XTAL2 IOH 100 mA
TQFP MLF
1] IOH 400 mA
2] C0 - C5 IOH 200 mA
3] C6 D0 - D4 IOH 300 mA
4] B0 - B7 D5 - D7 IOH 300 mA
IOH VOH
5. VCC 2.5V
227
2486NAVR07/04
Figure 114.
V IH1
V IL1
Table 99.
VCC = 2.7V - 5.5V
VCC = 4.5V - 5.5V
16
MHz
1/tCLCL
tCLCL
125
62.5
ns
tCHCX
50
25
ns
tCLCX
50
25
ns
tCLCH
1.6
0.5
tCHCL
1.6
0.5
tCLCL
Table 100. RC
Notes:
228
R [k](1)
C [pF]
f(2)
100
47
87 kHz
33
22
650 kHz
10
22
2.0 MHz
1. R 3 k - 100 kC 20 pF C C
2.
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Table 101 ATmega8

Figure 115
Table 101.
VIL
VIH
-0.5
0.3 VCC
0.7 VCC
VCC + 0.5
(1)
Vhys
VOL
(1)
tr(1)
SDA SCL
tof(1)
VIHmin VILmax
tSP(1)
Ii
I/O
Ci(1)
I/O
fSCL
SCL
Rp
START ( )
tHD;STA
tLOW
SCL
tHIGH
SCL
tSU;STA
STARTS
tHD;DAT
tSU;DAT
tSU;STO
STOP
tBUF
Notes:
STOP START
1.
2.
3.
4.
0.05 VCC
3 mA
0.4
(3)(2)
300
ns
20 + 0.1Cb(3)(2)
250
ns
(2)
ns
20 + 0.1Cb
10 pF < Cb < 400 pF(3)
(2)
0
0.1VCC < Vi < 0.9VCC
50
-10
10
10
pF
fCK(4) > max(16fSCL, 250kHz)(5)
400
kHz
fSCL 100 kHz
V CC 0,4V
-----------------------------3mA
1000ns
------------------Cb
fSCL > 100 kHz
V CC 0,4V
-----------------------------3mA
300ns
---------------Cb
fSCL 100 kHz
4.0
fSCL > 100 kHz
0.6
(6)
4.7
fSCL > 100 kHz(7)
1.3
fSCL 100 kHz
4.0
fSCL > 100 kHz
0.6
fSCL 100 kHz
4.7
fSCL > 100 kHz
0.6
fSCL 100 kHz
3.45
fSCL > 100 kHz
0.9
fSCL 100 kHz
250
ns
fSCL > 100 kHz
100
ns
fSCL 100 kHz
4.0
fSCL > 100 kHz
0.6
fSCL 100 kHz
4.7
fSCL > 100 kHz
1.3
fSCL 100 kHz
ATmega8 100%
fSCL > 100 kHz
Cb =
fCK = CPU
229
2486NAVR07/04
5. ATmega8
fSCL
6. ATmega8 (1/fSCL - 2/fCK)
fSCL = 100 kHz fCK 6 MHz
7. ATmega8 (1/fSCL - 2/fCK) fCK = 8 MHz
fSCL > 308 kHz ATmega8
ATmega8(400 kHz)tLOW
Figure 115.
tof
tHIGH
tLOW
tr
tLOW
SCL
tSU;STA
tHD;STA
tHD;DAT
tSU;DAT
tSU;STO
SDA
tBUF
SPI
Figure 116 Figure 117

Table 102. SPI
SCK
Table 50
SCK /
50%
3.6
10
10
SCK
0.5 tSCK
SCK
10
SCK
10
SS
15
10
SCK
4 tck
11
SCK /
2 tck
12
13
10
14
10
15
SCK
16
SCK SS
17
SS
18
SS SCK
Note:
230
ns
1.6
15
20
10
2 tck
1. SPI SCK /
fCK < 12 MHz- 2tCLCL
fCK > 12 MHz- 3tCLCL
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 116. SPI ( )
SS
6
SCK
(CPOL = 0)
2
SCK
(CPOL = 1)
4
MISO
(Data Input)
MSB
...
LSB
MOSI
(Data Output)
MSB
...
LSB
Figure 117. SPI ( )

18
SS
10
16
SCK
(CPOL = 0)
11
11
SCK
(CPOL = 1)
13
MOSI
(Data Input)
14
12
MSB
...
LSB
15
MISO
(Data Output)
MSB
17
...
LSB
231
2486NAVR07/04

Table 103. ADC
(1)
(1)
(1)
10
Bits
VREF = 4V, VCC = 4V

ADC = 200 kHz
1.75
LSB
VREF = 4V, VCC = 4V

ADC = 1 MHz
LSB
(INL)
VREF = 4V, VCC = 4V

ADC = 200 kHz
0.75
LSB
(DNL)
VREF = 4V, VCC = 4V

ADC = 200 kHz
0.5
LSB
( INL, DNL,
, Gain,
)
VREF = 4V, VCC = 4V

ADC = 200 kHz
LSB
VREF = 4V, VCC = 4V

ADC = 200 kHz
LSB
13
260
50
1000
kHz
AVCC
VCC - 0.3(2)
VCC + 0.3(3)
VREF
2.0
AVCC
VIN
GND
VREF
VINT
RREF
RAIN
Notes:
232
38.5
2.3
55
2.56
kHz
2.7
32
100
1.
2. AVCC 2.7V
3. AVCC 5.5V
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ATmega8
I/O
I/O
CL*VCC*f CL VCC
f
Figure 118. (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz
3
5.5V
5.0V
4.5V
4.0V
3.3V
3.0V
2.7V
2.5
ICC (mA)
1.5
0.5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (MHz)
233
2486NAVR07/04
Figure 119. (1 - 20 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz
30
5.5V
25
5.0V
4.5V
ICC (mA)
20
15
10
3.3V
3.0V
2.7V
0
0
10
12
14
16
18
20
Frequency (MHz)
Figure 120. VCC ( RC 8 MHz)
ACTIVE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 8 MHz
18
16
-40C
25C
85C
14
ICC (mA)
12
10
8
6
4
2
0
2.5
3.5
4.5
5.5
VCC (V)
234
ATmega8(L)
2486NAVR07/04
ATmega8(L)

12
10
-40C
25C
85C
ICC (mA)
0
2.5
3.5
4.5
5.5
VCC (V)

6
25C
-40C
85C
ICC (mA)
0
2.5
3.5
4.5
5.5
VCC (V)
235
2486NAVR07/04

3.5
3
85C
25C
ICC (mA)
2.5
-40C
2
1.5
1
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 124. VCC (32 kHz )

32kHz EXTERNAL OSCILLATOR
120
100
25C
ICC (uA)
80
60
40
20
0
2.5
3.5
4.5
5.5
VCC (V)
236
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 125. (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz
0.7
5.5V
ICC (mA)
0.6
5.0V
0.5
4.5V
0.4
4.0V
3.3V
3.0V
2.7V
0.3
0.2
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (MHz)
Figure 126. (1 - 20 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz
ICC (mA)
14
5.5V
12
5.0V
10
4.5V
4.0V
3.3V
3.0V
2.7V
0
0
10
12
14
16
18
20
Frequency (MHz)
237
2486NAVR07/04
IDLE SUPPLY CURRENT vs. VCC

8
-40C
25C
85C
7
6
ICC (mA)
5
4
3
2
1
0
2.5
3.5
4.5
5.5
VCC (V)

4
-40C
25C
85C
3.5
3
ICC (mA)
2.5
2
1.5
1
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
238
ATmega8(L)
2486NAVR07/04
ATmega8(L)

1.8
-40C
85C
25C
1.6
1.4
ICC (mA)
1.2
1
0.8
0.6
0.4
0.2
0
2.5
3.5
4.5
5.5
VCC (V)

1
85C
25C
-40C
0.9
0.8
ICC (mA)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.5
3.5
4.5
5.5
VCC (V)
239
2486NAVR07/04
Figure 131. VCC (32 kHz )

32kHz EXTERNAL OSCILLATOR
40
35
25C
30
ICC (uA)
25
20
15
10
5
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 132. VCC ( )
POWER-DOWN SUPPLY CURRENT vs. VCC

WATCHDOG TIMER DISABLED
2.5
85C
2
1.5
ICC (uA)
-40C
25C
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
240
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 133. VCC ( )
POWER-DOWN SUPPLY CURRENT vs. V CC
WATCHDOG TIMER ENABLED
80
85C
25C
-40C
70
60
ICC (uA)
50
40
30
20
10
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 134. VCC ( )
POWER-SAVE SUPPLY CURRENT vs. V CC

25
20
25C
ICC (uA)
15
10
0
2.5
3.5
4.5
5.5
VCC (V)
241
2486NAVR07/04
Standby
Figure 135. Standby VCC (455 kHz )
STANDBY SUPPLY CURRENT vs. V CC

455 kHz RESONATOR, WATCHDOG TIMER DISABLED
80
70
60
ICC (uA)
50
40
30
20
10
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 136. Standby VCC (1 MHz )

1 MHz RESONATOR, WATCHDOG TIMER DISABLED
70
60
ICC (uA)
50
40
30
20
10
0
2.5
3.5
4.5
5.5
VCC (V)
242
ATmega8(L)
2486NAVR07/04
ATmega8(L)

90
80
70
ICC (uA)
60
50
40
30
20
10
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 138. Standby VCC (2 MHz Xtal )

2 MHz XTAL, WATCHDOG TIMER DISABLED
90
80
70
ICC (uA)
60
50
40
30
20
10
0
2.5
3.5
4.5
5.5
VCC (V)
243
2486NAVR07/04

140
120
ICC (uA)
100
80
60
40
20
0
2.5
3.5
4.5
5.5
VCC (V)

140
120
ICC (uA)
100
80
60
40
20
0
2.5
3.5
4.5
5.5
VCC (V)
244
ATmega8(L)
2486NAVR07/04
ATmega8(L)

160
140
120
ICC (uA)
100
80
60
40
20
0
2.5
3.5
4.5
5.5
VCC (V)

200
180
160
140
ICC (uA)
120
100
80
60
40
20
0
2.5
3.5
4.5
5.5
VCC (V)
245
2486NAVR07/04
Figure 143. I/O (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 5V
160
85C
140
25C
120
-40C
IIO (uA)
100
80
60
40
20
0
0
VOP (V)
Figure 144. I/O (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 2.7V
90
80
85C
25C
70
-40C
IIO (uA)
60
50
40
30
20
10
0
0
0.5
1.5
2.5
VOP (V)
246
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 145. (Reset) Reset (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

Vcc = 5V
100
- 40 C
25C
80
IRESET (uA)
85C
60
40
20
0
0
2
VRESET (V)
Figure 146. (Reset) Reset (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

Vcc = 2.7V
45
-40C
40
25C
35
85C
IRESET (uA)
30
25
20
15
10
5
0
0
0.5
1.5
2.5
VRESET (V)
247
2486NAVR07/04
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

Vcc = 5V
80
-40C
70
25C
60
85C
IOH (mA)
50
40
30
20
10
0
VOH (V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

Vcc = 2.7V
30
-40C
25
25C
85C
IOH (mA)
20
15
10
0
0
0.5
1.5
2.5
VOH (V)
248
ATmega8(L)
2486NAVR07/04
ATmega8(L)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

Vcc = 5V
90
80
-40C
70
25C
60
IOL (mA)
85C
50
40
30
20
10
0
0
0.5
1.5
2.5
VOL (V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

Vcc = 2.7V
35
-40C
30
25C
25
IOL (mA)
85C
20
15
10
5
0
0
0.5
1.5
2.5
VOL (V)
249
2486NAVR07/04
Figure 151. Reset I/O (VCC = 5V)
RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE

Vcc = 5V
4
3.5
-40C
3
Current (mA)
25C
2.5
85C
2
1.5
1
0.5
0
2
2.5
3.5
4.5
VOH (V)
Figure 152. Reset I/O (VCC = 2.7V)
RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE

Vcc = 2.7V
5
4.5
25C
-40C
Current (mA)
3.5
3
2.5
85C
2
1.5
1
0.5
0
0
0.5
1.5
2.5
VOH (V)
250
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 153. Reset I/O (VCC = 5V)
RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE

Vcc = 5V
14
-40C
12
25C
Current (mA)
10
85C
8
6
4
2
0
0
0.5
1.5
2.5
VOL (V)
Figure 154. Reset I/O (VCC = 2.7V)
RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE

Vcc = 2.7V
4.5
4
-40C
3.5
25C
Current (mA)
85C
2.5
2
1.5
1
0.5
0
0
0.5
1.5
2.5
VOL (V)
251
2486NAVR07/04
Figure 155. I/O VCC (VIH, I/O 1)
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC

VIH, IO PIN READ AS '1'
2.5
-40C
85C
25C
Threshold (V)
1.5
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 156. I/O VCC (VIL, I/O 0)
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC

VIL, IO PIN READ AS '0'
2
-40C
25C
85C
Threshold (V)
1.5
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
252
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 157. I/O VCC
I/O PIN INPUT HYSTERESIS vs. VCC

0.7
Input Hysteresis (V)
0.6
85C
-40C
25C
0.5
0.4
0.3
0.2
0.1
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 158. Reset I/O VCC (VIH,Reset 1)
RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC

VIH, RESET PIN READ AS '1'
4
-40C
85C
25C
3.5
Threshold (V)
3
2.5
2
1.5
1
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
253
2486NAVR07/04
Figure 159. Reset I/O VCC (VIL,Reset 0)
RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC

VIL, RESET PIN READ AS '0'
2.5
85C
25C
-40C
Threshold (V)
1.5
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 160. Reset I/O VCC
RESET PIN AS I/O - PIN HYSTERESIS vs. VCC

2
-40C
85C
25C
1.5
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
254
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 161. Reset VCC (VIH,Reset 1)
RESET INPUT THRESHOLD VOLTAGE vs. VCC

VIH, RESET PIN READ AS '1'
2.5
-40C
25C
85C
Threshold (V)
1.5
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 162. Reset VCC (VIL,Reset 0)
RESET INPUT THRESHOLD VOLTAGE vs. VCC

VIL, RESET PIN READ AS '0'
2.5
85C
25C
-40C
Threshold (V)
1.5
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
255
2486NAVR07/04
Figure 163. Reset VCC
RESET INPUT PIN HYSTERESIS vs. VCC

1
0.8
-40C
0.6
25C
0.4
85C
0.2
0
2
2.5
3.5
4.5
5.5
VCC (V)
BOD
Figure 164. BOD (BOD 4.0V)

BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 4.0V
4.3
4.2
Rising VCC
Threshold (V)
4.1
Falling VCC
3.9
3.8
3.7
-50
-40
-30
-20
-10
10
20
30
40
50
60
70
80
90
100
Temperature (C)
256
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 165. BOD (BOD 2.7v)
BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 2.7V
2.8
2.7
Threshold (V)
Rising VCC
2.6
Falling VCC
2.5
2.4
-50
-40
-30
-20
-10
10
20
30
40
50
60
70
80
90
100
Temperature (C)
Figure 166. VCC
BANDGAP VOLTAGE vs. VCC
Bandgap Voltage (V)
1.315
1.31
-40
1.305
85
25
1.3
1.295
1.29
2.5
3.5
4.5
5.5
Vcc (V)
257
2486NAVR07/04
Figure 167. (VCC = 5V)
ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE

VCC = 5V
0.003
Comparator Offset Voltage (V)
0.002
0.001
0
-0.001
85
-0.002
-0.003
25C
-0.004
-0.005
-40
-0.006
0
0.5
1.5
2.5
3.5
4.5
Common Mode Voltage (V)
Figure 168. (VCC = 2.7V)
ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE

VCC = 2.7V
0.003
Comparator Offset Voltage (V)
0.002
0.001
0
-0.001
85
-0.002
25
-0.003
-0.004
-40
-0.005
0
0.5
1.5
2.5
Common Mode Voltage (V)
258
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 169. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. VCC

1260
-40C
25C
1240
85C
1220
FRC (kHz)
1200
1180
1160
1140
1120
1100
2.5
3.5
4.5
5.5
VCC (V)
Figure 170. 8 MHz RC

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
8.5
5.5V
8.3
8.1
4.0V
FRC (MHz)
7.9
7.7
7.5
2.7V
7.3
7.1
6.9
6.7
6.5
-60
-40
-20
20
40
60
80
100
Temperature (C)
259
2486NAVR07/04
Figure 171. 8 MHz RC VCC
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC

8.5
-40C
8.3
25C
8.1
FRC (MHz)
7.9
85C
7.7
7.5
7.3
7.1
6.9
6.7
6.5
2.5
3.5
4.5
5.5
VCC (V)
Figure 172. 8 MHz RC Osccal
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

16
14
FRC (MHz)
12
10
4
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
OSCCAL VALUE
260
ATmega8(L)
2486NAVR07/04
ATmega8(L)
4.2
5.5V
4.1
4.0V
FRC (MHz)
3.9
2.7V
3.8
3.7
3.6
3.5
-60
-40
-20
20
40
60
80
100
Temperature (C)

4.2
-40C
4.1
25C
4
FRC (MHz)
85C
3.9
3.8
3.7
3.6
3.5
2.5
3.5
4.5
5.5
VCC (V)
261
2486NAVR07/04

8
FRC (MHz)
2
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
OSCCAL VALUE

2.1
5.5V
2.05
4.0V
FRC (MHz)
1.95
2.7V
1.9
1.85
1.8
-60
-40
-20
20
40
60
80
100
Temperature (C)
262
ATmega8(L)
2486NAVR07/04
ATmega8(L)

2.2
2.1
-40C
FRC (MHz)
25C
2
85C
1.9
1.8
1.7
2.5
3.5
4.5
5.5
VCC (V)

3.8
3.3
FRC (MHz)
2.8
2.3
1.8
1.3
0.8
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
OSCCAL VALUE
263
2486NAVR07/04

1.04
5.5V
1.02
4.0V
FRC (MHz)
0.98
2.7V
0.96
0.94
0.92
0.9
-60
-40
-20
20
40
60
80
100
Temperature (C)

1.1
1.05
FRC (MHz)
-40C
25C
1
85C
0.95
0.9
2.5
3.5
4.5
5.5
VCC (V)
264
ATmega8(L)
2486NAVR07/04
ATmega8(L)

1.9
1.7
FRC (MHz)
1.5
1.3
1.1
0.9
0.7
0.5
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
OSCCAL VALUE
Figure 182. BOD VCC
BROWN-OUT DETECTOR CURRENT vs. VCC

30
25
-40C
25C
85C
ICC (uA)
20
15
10
0
2.5
3.5
4.5
5.5
VCC (V)
265
2486NAVR07/04
Figure 183. ADC VCC (AREF = AVCC)
ADC CURRENT vs. VCC

AREF = AVCC
450
400
25C
-40C
350
85C
ICC (uA)
300
250
200
150
100
50
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 184. AREF VCC
AREF EXTERNAL REFERENCE CURRENT vs. V CC

250
85C
200
25C
-40C
ICC (uA)
150
100
50
0
2.5
3.5
4.5
5.5
VCC (V)
266
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 185. 32 kHz TOSC VCC ( )
32 kHz TOSC CURRENT vs. V CC
25
20
25C
ICC (uA)
15
10
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 186. VCC

WATCHDOG TIMER CURRENT vs. V CC
80
70
85C
60
-40C
25C
ICC (uA)
50
40
30
20
10
0
2
2.5
3.5
4.5
5.5
VCC (V)
267
2486NAVR07/04
Figure 187. VCC
ANALOG COMPARATOR CURRENT vs. VCC

100
85C
90
25C
80
-40C
70
ICC (uA)
60
50
40
30
20
10
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 188. VCC

PROGRAMMING CURRENT vs. VCC
7
-40C
6
25C
ICC (mA)
85C
0
2.5
3.5
4.5
5.5
VCC (V)
268
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Figure 189. VCC (0.1 - 1.0 MHz )
RESET SUPPLY CURRENT vs. VCC

0.1 - 1 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP
4
5.5V
3.5
5.0V
4.5V
ICC (mA)
2.5
4.0V
2
3.3V
3.0V
2.7V
1.5
1
0.5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (MHz)
Figure 190. VCC (1 - 20 MHz )
RESET SUPPLY CURRENT vs. VCC

1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP
25
5.5V
20
5.0V
ICC (mA)
4.5V
15
10
3.3V
5
3.0V
2.7V
0
0
10
12
14
16
18
20
Frequency (MHz)
269
2486NAVR07/04
Figure 191. VCC
RESET PULSE WIDTH vs. VCC

1400
1200
Pulsewidth (ns)
1000
800
600
85C
25C
400
-40C
200
0
2.5
3.5
4.5
5.5
VCC (V)
270
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x3F (0x5F)
SREG
0x3E (0x5E)
SPH
SP10
SP9
SP8
11
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
11
0x3C (0x5C)
0x3B (0x5B)
GICR
INT1
INT0
IVSEL
IVCE
46, 63
0x3A (0x5A)
GIFR
INTF1
INTF0
64
0x39 (0x59)
TIMSK
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
TOIE0
68, 94, 113

69, 94, 113
0x38 (0x58)
TIFR
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
TOV0
0x37 (0x57)
SPMCR
SPMIE
RWWSB
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
200
0x36 (0x56)
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
158
0x35 (0x55)
MCUCR
SE
SM2
SM1
SM0
ISC11
ISC10
ISC01
ISC00
30, 62
0x34 (0x54)
MCUCSR
WDRF
BORF
EXTRF
PORF
38
0x33 (0x53)
TCCR0
CS02
CS01
CS00
68
0x32 (0x52)
TCNT0
T/C0 (8 )
0x31 (0x51)
OSCCAL
0x30 (0x50)
SFIOR
68
28
ACME
PUD
PSR2
PSR10
55, 71, 114, 180
0x2F (0x4F)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
FOC1A
FOC1B
WGM11
WGM10
89
0x2E (0x4E)
TCCR1B
ICNC1
ICES1
WGM13
WGM12
CS12
CS11
CS10
92
0x2D (0x4D)
TCNT1H
T/C1
92
0x2C (0x4C)
TCNT1L
92
0x2B (0x4B)
OCR1AH
T/C1
T/C1 A
0x2A (0x4A)
OCR1AL
T/C1 A
93
0x29 (0x49)
OCR1BH
T/C1 B
93
93
0x28 (0x48)
OCR1BL
T/C1 B
93
0x27 (0x47)
ICR1H
T/C1
94
0x26 (0x46)
ICR1L
T/C1
0x25 (0x45)
TCCR2
0x24 (0x44)
TCNT2
0x23 (0x43)
OCR2
FOC2
WGM20
COM21
COM20
WGM21
94
CS22
CS21
CS20
T/C2 (8 )
T/C2
110
110
0x22 (0x42)
ASSR
AS2
TCN2UB
OCR2UB
TCR2UB
0x21 (0x41)
WDTCR
WDCE
WDE
WDP2
WDP1
WDP0
UBRRH
URSEL
0x20(1) (0x40)(1)
108
UBRR[11:8]
110
40
145
UCSRC
URSEL
UMSEL
UPM1
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
0x1F (0x3F)
EEARH
EEAR8
17
0x1E (0x3E)
EEARL
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
17
0x1D (0x3D)
EEDR
0x1C (0x3C)
EECR
EERIE
EEMWE
EEWE
EERE
17
0x1B (0x3B)
0x1A (0x3A)
EEPROM
143
17
0x19 (0x39)
0x18 (0x38)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
61
0x17 (0x37)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
61
0x16 (0x36)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
61
0x15 (0x35)
PORTC
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
61
0x14 (0x34)
DDRC
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
61
0x13 (0x33)
PINC
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
61
0x12 (0x32)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
61
0x11 (0x31)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
61
0x10 (0x30)
PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
0x0F (0x2F)
SPDR
SPI
61
121
0x0E (0x2E)
SPSR
SPIF
WCOL
SPI2X
0x0D (0x2D)
SPCR
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
0x0C (0x2C)
UDR
0x0B (0x2B)
UCSRA
RXC
TXC
UDRE
FE
DOR
PE
U2X
MPCM
142
0x0A (0x2A)
UCSRB
RXCIE
TXCIE
UDRIE
RXEN
TXEN
UCSZ2
RXB8
TXB8
142
0x09 (0x29)
UBRRL
0x08 (0x28)
ACSR
ACD
ACBG
ACO
ACIC
ACIS1
ACIS0
181
USART I/O
ACIE
119
141
USART
ACI
121
145
0x07 (0x27)
ADMUX
REFS1
REFS0
ADLAR
MUX3
MUX2
MUX1
MUX0
192
0x06 (0x26)
ADCSRA
ADEN
ADSC
ADFR
ADIF
ADIE
ADPS2
ADPS1
ADPS0
194
0x05 (0x25)
ADCH
ADC
195
0x04 (0x24)
ADCL
ADC
195
0x03 (0x23)
TWDR
0x02 (0x22)
TWAR
TWA6
TWA5
TWA4
TWA3
TWA2
160
TWA1
TWA0
TWGCE
160
271
2486NAVR07/04
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x01 (0x21)
TWSR
TWS7
TWS6
TWS5
TWS4
TWS3
TWPS1
TWPS0
0x00 (0x20)
TWBR
Notes:
272
160
158
1. UBRRH UCSRC USART

2. 0 I/O
3. 1 AVRCBI SBI
CBI SBI 0x00 - 0x1F
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ADD
Rd, Rr
Rd Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Rd Rd + Rr + C
Z,C,N,V,H
ADIW
Rdl,K
Rdh:Rdl Rdh:Rdl + K
Z,C,N,V,S
SUB
Rd, Rr
Rd Rd - Rr
Z,C,N,V,H
SUBI
Rd, K
Rd Rd - K
Z,C,N,V,H
SBC
Rd, Rr
Rd Rd - Rr - C
Z,C,N,V,H
SBCI
Rd, K
Rd Rd - K - C
Z,C,N,V,H
SBIW
Rdl,K
Rdh:Rdl Rdh:Rdl - K
Z,C,N,V,S
AND
Rd, Rr
Rd Rd Rr
Z,N,V
ANDI
Rd, K
Rd Rd K
Z,N,V
OR
Rd, Rr
Rd Rd v Rr
Z,N,V
ORI
Rd, K
Rd Rd v K
Z,N,V
EOR
Rd, Rr
Rd Rd Rr
Z,N,V
COM
Rd
Rd 0xFF Rd
Z,C,N,V
NEG
Rd
Rd 0x00 Rd
Z,C,N,V,H
SBR
Rd,K
Rd Rd v K
Z,N,V
CBR
Rd,K
Rd Rd (0xFF - K)
Z,N,V
INC
Rd
Rd Rd + 1
Z,N,V
DEC
Rd
Rd Rd 1
Z,N,V
TST
Rd
Rd Rd Rd
Z,N,V
CLR
Rd
Rd Rd Rd
Z,N,V
SER
Rd
Rd 0xFF
None
MUL
Rd, Rr
R1:R0 Rd x Rr
Z,C
MULS
Rd, Rr
R1:R0 Rd x Rr
Z,C
MULSU
Rd, Rr
R1:R0 Rd x Rr
Z,C
FMUL
Rd, Rr
R1:R0 (Rd x Rr) <<
Z,C
FMULS
Rd, Rr
Z,C
FMULSU
Rd, Rr
1
R1:R0 (Rd x Rr) << 1
R1:R0 (Rd x Rr) << 1
Z,C
PC PC + k + 1
(Z)
PC Z
PC PC + k + 1
ICALL
(Z)
PC Z
RET
PC STACK
RETI
PC STACK
Rd,Rr
if (Rd = Rr) PC PC + 2 or 3
CP
Rd,Rr
Rd Rr
Z, N,V,C,H
CPC
Rd,Rr
Rd Rr C
Z, N,V,C,H
CPI
Rd,K
Rd K
Z, N,V,C,H
SBRC
Rr, b
"0
if (Rr(b)=0) PC PC + 2 or 3
1/2/3
SBRS
Rr, b
"1
if (Rr(b)=1) PC PC + 2 or 3
1/2/3
SBIC
P, b
I/O "0
if (P(b)=0) PC PC + 2 or 3
1/2/3
SBIS
P, b
I/O "1
if (P(b)=1) PC PC + 2 or 3
1/2/3
BRBS
s, k
"1
if (SREG(s) = 1) then PCPC+k + 1
1/2
BRBC
s, k
"0
if (SREG(s) = 0) then PCPC+k + 1
1/2
BREQ
if (Z = 1) then PC PC + k + 1
1/2
RJMP
IJMP
RCALL
CPSE
4
1/2/3
BRNE
if (Z = 0) then PC PC + k + 1
1/2
BRCS
"1
if (C = 1) then PC PC + k + 1
1/2
BRCC
"0
1/2
BRSH
1/2
BRLO
1/2
BRMI
if (N = 1) then PC PC + k + 1
1/2
BRPL
if (N = 0) then PC PC + k + 1
1/2
BRGE
if (N V= 0) then PC PC + k + 1
1/2
BRLT
if (N V= 1) then PC PC + k + 1
1/2
BRHS
"1
if (H = 1) then PC PC + k + 1
1/2
BRHC
"0
if (H = 0) then PC PC + k + 1
1/2
BRTS
T "1
if (T = 1) then PC PC + k + 1
1/2
BRTC
T "0
if (T = 0) then PC PC + k + 1
1/2
BRVS
"1
if (V = 1) then PC PC + k + 1
1/2
BRVC
"0
if (V = 0) then PC PC + k + 1
1/2
273
2486NAVR07/04
BRIE
if ( I = 1) then PC PC + k + 1
1/2
BRID
if ( I = 0) then PC PC + k + 1
1/2
MOV
Rd, Rr
Rd, Rr
Rd Rr
Rd+1:Rd Rr+1:Rr
MOVW
LDI
Rd, K
Rd K
LD
Rd, X
Rd (X)
LD
Rd, X+
Rd (X), X X + 1
LD
Rd, - X
X X - 1, Rd (X)
LD
Rd, Y
Rd (Y)
LD
Rd, Y+
Rd (Y), Y Y + 1
LD
Rd, - Y
Y Y - 1, Rd (Y)
LDD
Rd,Y+q
Rd (Y + q)
LD
Rd, Z
Rd (Z)
LD
Rd, Z+
Rd (Z), Z Z+1
LD
Rd, -Z
Z Z - 1, Rd (Z)
LDD
Rd, Z+q
Rd (Z + q)
LDS
Rd, k
SRAM
Rd (k)
ST
X, Rr
(X) Rr
ST
X+, Rr
(X) Rr, X X + 1
ST
- X, Rr
X X - 1, (X) Rr
ST
Y, Rr
(Y) Rr
ST
Y+, Rr
(Y) Rr, Y Y + 1
ST
- Y, Rr
Y Y - 1, (Y) Rr
STD
Y+q,Rr
(Y + q) Rr
ST
Z, Rr
(Z) Rr
ST
Z+, Rr
(Z) Rr, Z Z + 1
ST
-Z, Rr
Z Z - 1, (Z) Rr
STD
Z+q,Rr
(Z + q) Rr
STS
k, Rr
SRAM
(k) Rr
R0 (Z)
LPM
LPM
Rd, Z
Rd (Z)
LPM
Rd, Z+
Rd (Z), Z Z+1
(Z) R1:R0
SPM
IN
Rd, P
I/O
Rd P
OUT
P, Rr
P Rr
PUSH
Rr
STACK Rr
POP
Rd
Rd STACK
SBI
P,b
I/O
I/O(P,b) 1
CBI
P,b
I/O
I/O(P,b) 0
LSL
Rd
Rd(n+1) Rd(n), Rd(0) 0
Z,C,N,V
LSR
Rd
Rd(n) Rd(n+1), Rd(7) 0
Z,C,N,V
ROL
Rd
Rd(0)C,Rd(n+1) Rd(n),CRd(7)
Z,C,N,V
ROR
Rd
Rd(7)C,Rd(n) Rd(n+1),CRd(0)
Z,C,N,V
ASR
Rd
Rd(n) Rd(n+1), n=0..6
Z,C,N,V
SWAP
Rd
Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0)
BSET
SREG(s) 1
SREG(s)
BCLR
SREG(s) 0
SREG(s)
BST
Rr, b
T Rr(b)
BLD
Rd, b
Rd(b) T
SEC
C1
CLC
C0
SEN
N1
CLN
N0
SEZ
Z1
CLZ
Z0
SEI
I1
CLI
I0
SES
S1
CLS
S0
SEV
V1
CLV
V0
SET
SREG T
T1
274
ATmega8(L)
2486NAVR07/04
ATmega8(L)
CLT
SREG T
T0
SEH
CLH
SREG
SREG
H1
H0
H
H
1
1
( )
( WDR/timer )
1
1
1
MCU
NOP
SLEEP
WDR
275
2486NAVR07/04

(MHz)
2.7 - 5.5
ATmega8L-8AC
ATmega8L-8PC
ATmega8L-8MC
32A
28P3
32M1-A
(0C 70C)
ATmega8L-8AI
ATmega8L-8PI
ATmega8L-8MI
32A
28P3
32M1-A
(-40C 85C)
ATmega8-16AC
ATmega8-16PC
ATmega8-16MC
32A
28P3
32M1-A
(0C 70C)
ATmega8-16AI
ATmega8-16PI
ATmega8-16MI
32A
28P3
32M1-A
(-40C 85C)
16
Note:
4.5 - 5.5
wafer Atmel
32A
32- (1.0 mm)TQFP
28P3
28- 0.300 PDIP
32M1-A
32- 5 x 5 x 1.0 0.50 mm MLF
276
ATmega8(L)
2486NAVR07/04
ATmega8(L)
32A
PIN 1
B
PIN 1 IDENTIFIER
E1
D1
D
C
0~7
A1
A2
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
1.20
A1
0.05
0.15
A2
0.95
1.00
1.05
8.75
9.00
9.25
D1
6.90
7.00
7.10
8.75
9.00
9.25
E1
6.90
7.00
7.10
0.30
0.45
0.09
0.20
0.45
0.75
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
2325 Orchard Parkway

San Jose, CA 95131
TITLE
32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
32A
277
2486NAVR07/04
28P3
PIN
1
E1
SEATING PLANE
B2
B1
A1
(4 PLACES)
0 ~ 15
REF
e
E
COMMON DIMENSIONS
eB
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
MIN
NOM
MAX
4.5724
A1
0.508
34.544
34.798
7.620
8.255
E1
7.112
7.493
0.381
0.533
B1
1.143
1.397
B2
0.762
1.143
3.175
3.429
0.203
0.356
eB
10.160
SYMBOL
A
NOTE
Note 1
Note 1
2.540 TYP
09/28/01
278

San Jose, CA 95131
TITLE
28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
28P3
REV.
B
ATmega8(L)
2486NAVR07/04
ATmega8(L)
32M1-A
D
D1
1
2
3
Pin 1 ID
E1
SIDE VIEW
TOP VIEW
A3
A2
A1
A
0.08 C
P
COMMON DIMENSIONS
D2
Pin 1 ID
1
2
3
E2
SYMBOL
MIN
NOM
MAX
0.80
0.90
1.00
A1
0.02
0.05
A2
0.65
1.00
A3
b
0.20 REF
0.18
D2
3.25
4.75BSC
2.95
Notes: 1. JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
3.10
5.00 BSC
E1
E2
0.30
4.75 BSC
2.95
BOTTOM VIEW
0.23
5.00 BSC
D1
e
NOTE
3.10
3.25
0.50 BSC
0.30
0.40
0.50
0.60
12o
01/15/03

San Jose, CA 95131
TITLE
32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm
Micro Lead Frame Package (MLF)
DRAWING NO.
32M1-A
REV.
C
279
2486NAVR07/04
ATmega8
ATmega8
Rev. D, E, F G
32 KHz T/C2 CKOPT XTALn/TOSCn
1. 32 KHzT/C2CKOPTXTALn/TOSCn
RC XTAL1/TOSC1 XTAL2/TOSC2
32 KHz T/C2 RC
CKOPTXTAL1/TOSC1XTAL2/TOSC2
XTAL1/TOSC1 XTAL2/TOSC2 20 - 36 pF ATmega8

Rev. G RC CKOPT
ATmega8 Rev. G CKOPT = 0 ( ) XTAL1 XTAL2
Rev. G CKOPT
(CKOPT = 1)
280
ATmega8(L)
2486NAVR07/04
ATmega8(L)
ATmega8
Rev. 2486M-12/03
Rev. 2486N-07/04
1. P 2 MLF
2. P 39
3. P 226
4. ADC4 ADC5 10
P 183
P 232
5. P 25 RC RC
Rev. 2486L-10/03
Rev. 2486M-12/03
Rev. 2486K-08/03
Rev. 2486L-10/03
1. P 27 RC
1. TBD
2. ICP ICP1
3. CALL JMP
4. P 35Table 15 tRST, P 39Table 16 , P 228Table 100 P 230Table 102
VBG
5. P 27RC Table 9XTAL1XTAL2 (NC)
P 29 / XTAL1/XTAL2 CKOPT
6. P 42
7. P 55 I/O SFIOR bit 4, ADHSM
8. P 201Figure 103 2
9. P 222 4
10. P 224Table 97 tWD_FUSE P 225Table 98 , Byte 3
11. P 226
Rev. 2486J-02/03
Rev. 2486K-08/03
1. P 35Table 15 VBOT
281
2486NAVR07/04
2. P 232
3. P 233ATmega8
4. P 280
Rev. 2486I-12/02
Rev. 2486J-02/03
1. P 23 clkASY
2. 32 kHz
3. P 83Figure 38 OCn
4. 1
5. TWI
6. P 202 ( ) SPM EEPROM
7. ADHSM
8. P 20 EEPROM
9. XTAL1 XTAL2 P
XTAL1/XTAL2/TOSC1/TOSC2
5 B(PB7..PB0)
10. P 230SPI P 225SPI

11. P 57 C PC6
12. P 55 B PB6 PB7
13. P 146 230.4 Mbps 230.4 kbps
14. P 105 PWM 2 PWM
15. P 156Figure 76
16. P 202 Z
17. P 210Table 87 RSTDISBL
18. P 277
Rev. 2486H-09/02
Rev. 2486I-12/02
1. Rev D, E F
Rev. 2486G-09/02
Rev. 2486H-09/02
1. Flash 10,000 /
282
ATmega8(L)
2486NAVR07/04
ATmega8(L)
Rev. 2486F-07/02
Rev. 2486G-09/02
Rev. 2486E-06/02
Rev. 2486F-07/02
1 P 232Table 103ADC .
P 52
P 56MOSI/OC2 B, Bit 3 OCS2
:
P 122Table 51CPOL CPHA P 144Table 59UCPOL
P 182Table 72 (1) P 187Table 73ADC
P 193Table 75 P 208Table 84Figure 103Z

Rev. 2486D-03/02
Rev. 2486E-06/02
P 220
P 35Table 15 P 39Table 16 P 226DC

P 232Table
P 29
P 228Table 99
TWI
TWI P 160Table 65TWI
Rev. 2486C-03/02
Rev. 2486D-03/02
P 25Table 5 P 25Table 6
P 26Table 8 RC P 29Table 12

2 P 233ATmega8
Rev. 2486B-12/01
Rev. 2486C-03/02
TWI
TWI TWBRR TWI
P 157
P 157
283
2486NAVR07/04
OSCCAL
2 4 8 MHz
P 28 OSCCAL P 211
TBD
P 23Table 3 P 35Table 15 P 39Table 16 P 41Table 17 , P 226TA = -40C
85CVCC = 2.7V 5.5V ( ) P 228Table 99 P 230Table 102
P 212Figure 104 P 222Figure 112 AVCC
RESET
P 213
284
ATmega8(L)
2486NAVR07/04

MEGA8

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8 AVR

2.7 - 5.5V (ATmega8L)

TQFP Top View

MLF Top View

PORTC DIGITAL INTERFACE

PORTB DIGITAL INTERFACE

PORTD DIGITAL INTERFACE

ADC CPU ADC I/O

Atmel ISP Flash

RSTDISBL PC6 I/O PC6 C

AVCC A/D C (3..0) ADC (7..6) ADC

Figure 2. AVR MCU

I/O 64 CPU SPI

Figure 3. AVR CPU

POP RET RETI

AVR CPU clkCPU

sbi EECR, EEMWE

out SREG, r16

Flash 10,000 ATmega8 (PC) 12

Application Flash Section

Boot Flash Section

Figure 8 ATmega8 SRAM

Data Address Space

SRAM clkCPU Figure

Memory Vccess Instruction

ATmega8 512 EEPROM

P 209 SPI EEPROM

Bits 15..9 Res:

Bits 8..0 EEAR8..0: EEPROM

Bits 7..0 EEDR7..0: EEPROM

Bits 7..4 Res:

Bit 3 EERIE: EEPROM

CPU EEPROM EEPROM (

ATmega8 I/O P 271

I/O I/O / SPI USARTI/O

Flash Flash CPU

XTAL1 XTAL2 Figure 11

CKOPT 8 MHz CKOPT 16 MHz C1

101, 110, 111

Table 5 CKSEL0 SUT1..0

32.768 kHz CKSEL 1001

RC 1.0 2.0 4.0 8.0 MHz

SUT Table 10 PB6

Bits 7..0 CAL7..0:

/ (TOSC1 TOSC2) AVR

SM2..0 000 SLEEP MCU CPU

SM2..0 001 SLEEP MCU CPU

SM2..0 010 SLEEP MCU

SM2..0 011 SLEEP MCU

SM2..0 110 SLEEP MCU Standby

clkCPU clkFLASH clkIO clkADC clkASY

clkCPU clkFLASH clkIO clkADC clkASY

I/O clkI/O ADC clkADC

MCU Control and Status

(POR) Table 15 VCC

Figure 15. MCU RESET VCC

Figure 16. MCU RESET

ATmega8 BOD(Brown-out Detection)

Bit 7..4 Res:

Bits 7..5 Res:

1. WDCE WDE "1 WDE "1

out WDTCR, r16

out WDTCR, r16

1. WDCE WDE "1 WDE "1