Designing with Multi-PLL and Spread-Spectrum Clocks in Digital Entertainment Equipment

By (Ashwini Raman, Product Marketing Manager, Cypress Semiconductor Corp.)

Executive Summary
The Digital TV industry is growing at a phenomenal rate with LCD and PDP (Flat panel displays) accounting for about 50% of the total shipments. The estimated CAGR for DTV market is a whopping 23% between 2006 and 2010. Rapidly declining finished DTV prices has led OEMs, ODMs and EMSs to focus on component reduction, BOM cost reduction, and integration. With that perspective, it is almost imperative for manufacturers to look at every component that goes into the system, including the heart of it all clocks. Every electronic system irrespective of analog or digital needs a timing reference based off of which the entire circuitry operates. The timing reference or clock has traditionally been crystals (piezoelectric quartz devices) or crystal oscillators (crystal + electronics to control the oscillations). With this integration trend, PLL based (Silicon) timing solutions are becoming more common to provide cleaner, stabler clocking options for designs that need multiple frequencies. The objective of this article is to articulate the value proposition of using silicon based timing solutions for solving design challenges vs. traditional methods of using several independent crystals or crystal oscillators (XOs).

Need for Multiple Frequencies in HDTV Systems: Different Standards and Interfaces
Nearly every electronic system, whether analog or digital, needs a timing reference for its circuitry. The timing reference or clock has traditionally used crystals or crystal oscillators (crystal plus circuitry to control the oscillations). With increasing integration, PLL-based silicon timing devices are becoming more common to provide cleaner, stabler clocking options for designs that need multiple frequencies. This article explores the difference between using silicon-based timing devices for solving design challenges versus traditional methods employing several independent crystals or crystal oscillators (XO). A basic LCD TV tuner diagram, Figure 1, processes an incoming data stream into the appropriate audio and video format of the television set in your living room. Figure 1: Generic LCD TV architecture

Designing with Multi-PLL and Spread-Spectrum Clocks in Digital Entertainment Equipment Published in Planet Analog (http://www.planetanalog.com)

Page 1 of 5 September 2007

[+] Feedback

There are multiple subsystems that go into the tuner boards. Basic functions can be broadly classified under the following blocks: 1. 2. 3. 4. Analog Front End (Demodulator) Audio/Video encoding and decoding (MPEG video decoder/ MPEG audio decoder) Interfaces Display Panel

Almost all the blocks shown in the diagram need a clocking signal. The CPU requires clocks typically in the range 30 to 100 MHz, while the MPEG standard requires a 27-MHz-based clock input. The decoder and encoder need to be synchronized, which is achieved by a VCXO (voltage-controlled crystal oscillator). Audio clocks that source the DACs have stringent partsper-million (ppm) accuracy and stability requirements, since their frequencies depend on sampling frequency and oversampling ratios. For the interfaces, clocks are defined by their respective standards, such as USB, Ethernet, Modem, PCI, PCIExpress, SATA, among others. The flat panel clocks are dependent on the display size and the display standard, with high definition at 1080i, 1080p, and 720p, and standard definition for NTSC and PAL. The panel controller subsystem must convert incoming picture data rate to match the size of the actual panel, such as. 74.17582418 MHz.

TV Architectures and Clock Tree Implementations

One of the key decisions that designers are now forced to make early on in the design process is whether to use the digital or analog signal format. A few years ago, the TV signal chain was primarily analog-based, but now a digital audio-data path is much more common. Both digital and analog paths have inherent advantages and disadvantages. However, there is a worldwide mandate in place to move all transmission to digital in a series of staged phases. HDTV transmissions are digital, so newer TVs tend to use the digital path. The advantage of digital transmission is that it has a higher tolerance of noise, compared to analog signals. Board designers need to take special care while routing, use differential signals with better SNR performance, or use shielding techniques to avoid signal degradation.

Traditional clock-tree design

This uses discrete crystals/XOs for each frequency requirement. The good thing about this approach is that clocks can be placed quite close to the components using them, simplifying routing. The downside is that each of these crystals/XOs has to be procured from vendors ahead of time and does not easily allow last-minute design changes. If even one of the frequencies changes, there is significant lead time that could lead to delays in the overall shipping schedule.

Silicon timing devices

For over a decade, PLL-based timing devices have become increasingly popular, compared to traditional clocking methods. Silicon timing devices enable complex system designs by supporting features that discrete crystals and crystal oscillators do not. While these devices impart flexibility and cost savings, they do come at a tradeoff. Every architectural change eventually needs to be cost-effective to occur, and for the effort to be justifiable. The most compelling benefit that silicon-based timing devices offer by integrating several crystals/XOs is reducing overall bill of materials (BOM) and maintaining, or stepping up, the level of performance. For example, in the typical TV tuner board example shown , with 5 to 6 discrete crystals (each costing $0.12 to $0.50), a silicon-based clock generator with programmable features capable of providing those frequencies reduces system cost if it
Designing with Multi-PLL and Spread-Spectrum Clocks in Digital Entertainment Equipment Published in Planet Analog (http://www.planetanalog.com) Page 2 of 5 September 2007

[+] Feedback

costs under $2.00. Although cost is the major driver for crystal/oscillator integration, there are other benefits that OEMs and end users perceive:

1. Reliability: Crystals are quartz-based devices whihc have a higher failure rate than PLL-based timing devices. Each crystal removed from the system can help increase overall system reliability. Integration also reduces component count on the board, leading to higher stability and lower return rates. 2. Availability of crystals: Crystals in the range of 10-40 MHz are readily available. However, high-frequency crystals, above 40 MHz, are more difficult to manufacture and procure. These higher-order overtone crystals range from $1 to $10. Siliconbased timing devices use one low-frequency crystal (or an available clock reference) to generate several high-frequency outputs. 3. Crystal aging: Crystals are prone to aging, with a +/-2ppm to +/-5ppm error per every few years, caused by impurities in the crystal material and on the crystal surface, as well as mechanical stresses between the crystal material and the deposited electrodes. This error may cause slow system-wide degradation. Long-term frequency drift is a common issue with the use of crystals. PLL-based timing devices maintain their accuracy over their entire lifetime. 4. Programmability: PLL-based clock generators have in-built programmability features that provide flexibility during design. Programmable features include changing output frequencies, drive strength settings, spread spectrum percentages, and pin programming for frequency selection, which means one output can give different frequencies based on need. Programmability can be done in-system, typically using an I2C-interface, to modify certain parameters "on the fly". This is a compelling feature for manufacturers using the same set of frequencies for multiple platforms. 5. Component reduction and board space savings: Programmable clock generators reduce number of components through integration, as system designers migrate towards fewer components to reduce problems caused by routing and maintaining signal integrity. PLL-based clock generators, with the ability to generate several outputs from a low-frequency crystal, reduce the number of total components used in a system and conserve board space. 6. EMI Reduction by Spread Spectrum Clocking: TV tuner boards are typically 5- to 7-layer boards, with dedicated ground planes for keeping interference low. Several high-speed signals must be routed carefully to help improve system performance and avoid crosstalk, skew, and signal-integrity issues. Silicon timing devices help alleviate these board design issues by offering features such as spread spectrum that reduce the peak energy of high-speed signals. EMI must be below limits set by regulatory standards such as CISPR 22 or FCC Part 15 Class B. All consumer products must pass stringent FCC regulations in order to be released to the market. Unfortunately, high-speed designs with frequency harmonics may source energy into inappropriate bands. The spread-spectrum approach reduces, and often eliminates, the need for ferrite beads, filters, coils, and chokes that add to the BOM. This is important because there is a significant redesign effort when a system fails any electromagnetic compliance test. Using a spread-spectrum device is somewhat like having insurance. Programmability allows this to be used when needed and turned off if not required. This feature is especially useful during development and testing. 7. Inventory management: One of the key challenges that procurement teams face today is managing inventory, demand, and forecast planning for every device that goes into a system. Since each OEM has several platforms as well as subplatforms of products, managing this supply chain could be quite cumbersome. (Imagine managing 10 different crystals of different frequencies from different vendors across the globe.) Silicon timing devices resolve this problem by generating different frequencies using software at the designer's desk, which not only simplifies design, but also allows purchasing to procure a single device for multiple platforms. 8. Perfectly synchronized outputs: Some applications may need several copies of the basic clock to be perfectly in sync or aligned. This feature is offered by programmable PLL devices. When using several discrete crystals, it may be difficult to achieve accurate synchronization. 9. Power management: Programmable PLL-based clock generators can cater to the niche demands of the portable market including gaming, smartphones, personal media players, digital cameras, and camcorders. In these power-intensive applications, certain frequencies can be turned off selectively using I2C or pin-programming. This is not easily achieved with traditional crystal designs.

Designing with Multi-PLL and Spread-Spectrum Clocks in Digital Entertainment Equipment Published in Planet Analog (http://www.planetanalog.com)

Page 3 of 5 September 2007

[+] Feedback

Why LCD Panel Controllers Need EMI Reduction

LCD screens are ubiquitous and are becoming increasingly popular. Whether it is the 3.5 inch touch screen of the iPhone, the Sharp Aquos TV, or a laptop PC\, the technology for driving all these displays is nearly the same. This pervasiveness of LCD panels has shown that the technology which drives it has matured. Newer models are now more affordable than ever, and the demands on panel performance continue to grow: create larger panels, reduce electromagnetic interference, reduce power consumption, and provide higher image quality. An LCD panel is essentially an array of transistors that modulates the voltage across the liquid crystal, and thereby controls the amount of light passing through the panel. Color is achieved by virtue of filters that allow red, green, or blue light to pass through a given pixel. Row drivers are attached to the transistor's gates. These control which row of pixels is being programmed at any given time by applying either an "on" or "off" voltage. The sources of the transistors are tied to the column drivers, which supply the specific voltage required to achieve proper pixel luminance. The timing controller takes the display data from the host and transmits it to the column drivers and row drivers through the panel interface. It may include additional features such as overdrive to reduce motion blur and enhance images, as well as gamma correction. The row-driver interface uses TTL signaling levels. The column-driver interface, which needs significant bandwidth for higher-resolution displays, uses a differential bus architecture; typically, this is reduced-swing differential signaling (RSDS), Figure 2. Figure 2: LCD panel-controller block diagram

One of the major challenges in panel electronics is reducing interference to comply with EMC regulations. Panel manufacturers typically support different panel sizes but prefer using a single board for all of them. The challenge is to design a two-layer, size-constrained board for the various sizes and still meet the EMI testing requirements. One approach is to improve the PCB material, and add extra board layers with dedicated ground planes. A dominant percentage of LCD panels use standard FR4 material for their PC boards; higher-cost PCB material and additional layers is not a viable option. Another method used for EMI reduction is filtering, but this is not an assured method that works for all panel sizes. Spread-spectrum clock generators have become a popular method adopted to solve EMI issues. They offer the ability to have a systemic approach to solving EMI issues early in the design process. The spread spectrum feature can be selectively turned on, and the spread percentage can be adjusted to achieve the right amount of spread and pass EMC tests. Spread percentage can be varied for various panel sizes, based on need, with the same device.

Designing with Multi-PLL and Spread-Spectrum Clocks in Digital Entertainment Equipment Published in Planet Analog (http://www.planetanalog.com)

Page 4 of 5 September 2007

[+] Feedback

References

Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone: 408-943-2600 Fax: 408-943-4730 http://www.cypress.com
Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PSoC Designer, Programmable System-on-Chip, and PSoC Express are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.

Designing with Multi-PLL and Spread-Spectrum Clocks in Digital Entertainment Equipment Published in Planet Analog (http://www.planetanalog.com)

Page 5 of 5 September 2007

[+] Feedback